[deliverable/linux.git] / arch / arm / mach-omap2 / pm24xx.c

/*
 * OMAP2 Power Management Routines
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 * Copyright (C) 2006-2008 Nokia Corporation
 *
 * Written by:
 * Richard Woodruff <r-woodruff2@ti.com>
 * Tony Lindgren
 * Juha Yrjola
 * Amit Kucheria <amit.kucheria@nokia.com>
 * Igor Stoppa <igor.stoppa@nokia.com>
 *
 * Based on pm.c for omap1
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/suspend.h>
#include <linux/sched.h>
#include <linux/proc_fs.h>
#include <linux/interrupt.h>
#include <linux/sysfs.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/time.h>
#include <linux/gpio.h>
#include <linux/console.h>

#include <asm/mach/time.h>
#include <asm/mach/irq.h>
#include <asm/mach-types.h>

#include <mach/irqs.h>
#include <plat/clock.h>
#include <plat/sram.h>
#include <plat/dma.h>
#include <plat/board.h>

#include "prm2xxx_3xxx.h"
#include "prm-regbits-24xx.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-24xx.h"
#include "sdrc.h"
#include "pm.h"
#include "control.h"

#include "powerdomain.h"
#include "clockdomain.h"

#ifdef CONFIG_SUSPEND
static suspend_state_t suspend_state = PM_SUSPEND_ON;
static inline bool is_suspending(void)
{
	return (suspend_state != PM_SUSPEND_ON);
}
#else
static inline bool is_suspending(void)
{
	return false;
}
#endif

static void (*omap2_sram_idle)(void);
static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
				  void __iomem *sdrc_power);

static struct powerdomain *mpu_pwrdm, *core_pwrdm;
static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;

static struct clk *osc_ck, *emul_ck;

static int omap2_fclks_active(void)
{
	u32 f1, f2;

	f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);

	/* Ignore UART clocks.  These are handled by UART core (serial.c) */
	f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK);
	f2 &= ~OMAP24XX_EN_UART3_MASK;

	if (f1 | f2)
		return 1;
	return 0;
}

static void omap2_enter_full_retention(void)
{
	u32 l;

	/* There is 1 reference hold for all children of the oscillator
	 * clock, the following will remove it. If no one else uses the
	 * oscillator itself it will be disabled if/when we enter retention
	 * mode.
	 */
	clk_disable(osc_ck);

	/* Clear old wake-up events */
	/* REVISIT: These write to reserved bits? */
	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
	omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);

	/*
	 * Set MPU powerdomain's next power state to RETENTION;
	 * preserve logic state during retention
	 */
	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);

	/* Workaround to kill USB */
	l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
	omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);

	omap2_gpio_prepare_for_idle(0);

	/* One last check for pending IRQs to avoid extra latency due
	 * to sleeping unnecessarily. */
	if (omap_irq_pending())
		goto no_sleep;

	/* Block console output in case it is on one of the OMAP UARTs */
	if (!is_suspending())
		if (!console_trylock())
			goto no_sleep;

	omap_uart_prepare_idle(0);
	omap_uart_prepare_idle(1);
	omap_uart_prepare_idle(2);

	/* Jump to SRAM suspend code */
	omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
			   OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
			   OMAP_SDRC_REGADDR(SDRC_POWER));

	omap_uart_resume_idle(2);
	omap_uart_resume_idle(1);
	omap_uart_resume_idle(0);

	if (!is_suspending())
		console_unlock();

no_sleep:
	omap2_gpio_resume_after_idle();

	clk_enable(osc_ck);

	/* clear CORE wake-up events */
	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);

	/* wakeup domain events - bit 1: GPT1, bit5 GPIO */
	omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);

	/* MPU domain wake events */
	l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	if (l & 0x01)
		omap2_prm_write_mod_reg(0x01, OCP_MOD,
				  OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	if (l & 0x20)
		omap2_prm_write_mod_reg(0x20, OCP_MOD,
				  OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);

	/* Mask future PRCM-to-MPU interrupts */
	omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
}

static int omap2_i2c_active(void)
{
	u32 l;

	l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
}

static int sti_console_enabled;

static int omap2_allow_mpu_retention(void)
{
	u32 l;

	/* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
	l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
		 OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
		 OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
		return 0;
	/* Check for UART3. */
	l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
	if (l & OMAP24XX_EN_UART3_MASK)
		return 0;
	if (sti_console_enabled)
		return 0;

	return 1;
}

static void omap2_enter_mpu_retention(void)
{
	int only_idle = 0;

	/* Putting MPU into the WFI state while a transfer is active
	 * seems to cause the I2C block to timeout. Why? Good question. */
	if (omap2_i2c_active())
		return;

	/* The peripherals seem not to be able to wake up the MPU when
	 * it is in retention mode. */
	if (omap2_allow_mpu_retention()) {
		/* REVISIT: These write to reserved bits? */
		omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
		omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
		omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);

		/* Try to enter MPU retention */
		omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
				  OMAP_LOGICRETSTATE_MASK,
				  MPU_MOD, OMAP2_PM_PWSTCTRL);
	} else {
		/* Block MPU retention */

		omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
						 OMAP2_PM_PWSTCTRL);
		only_idle = 1;
	}

	omap2_sram_idle();
}

static int omap2_can_sleep(void)
{
	if (omap2_fclks_active())
		return 0;
	if (!omap_uart_can_sleep())
		return 0;
	if (osc_ck->usecount > 1)
		return 0;
	if (omap_dma_running())
		return 0;

	return 1;
}

static void omap2_pm_idle(void)
{
	local_irq_disable();
	local_fiq_disable();

	if (!omap2_can_sleep()) {
		if (omap_irq_pending())
			goto out;
		omap2_enter_mpu_retention();
		goto out;
	}

	if (omap_irq_pending())
		goto out;

	omap2_enter_full_retention();

out:
	local_fiq_enable();
	local_irq_enable();
}

#ifdef CONFIG_SUSPEND
static int omap2_pm_begin(suspend_state_t state)
{
	disable_hlt();
	suspend_state = state;
	return 0;
}

static int omap2_pm_suspend(void)
{
	u32 wken_wkup, mir1;

	wken_wkup = omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
	wken_wkup &= ~OMAP24XX_EN_GPT1_MASK;
	omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);

	/* Mask GPT1 */
	mir1 = omap_readl(0x480fe0a4);
	omap_writel(1 << 5, 0x480fe0ac);

	omap_uart_prepare_suspend();
	omap2_enter_full_retention();

	omap_writel(mir1, 0x480fe0a4);
	omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);

	return 0;
}

static int omap2_pm_enter(suspend_state_t state)
{
	int ret = 0;

	switch (state) {
	case PM_SUSPEND_STANDBY:
	case PM_SUSPEND_MEM:
		ret = omap2_pm_suspend();
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

static void omap2_pm_end(void)
{
	suspend_state = PM_SUSPEND_ON;
	enable_hlt();
}

static const struct platform_suspend_ops omap_pm_ops = {
	.begin		= omap2_pm_begin,
	.enter		= omap2_pm_enter,
	.end		= omap2_pm_end,
	.valid		= suspend_valid_only_mem,
};
#else
static const struct platform_suspend_ops __initdata omap_pm_ops;
#endif /* CONFIG_SUSPEND */

/* XXX This function should be shareable between OMAP2xxx and OMAP3 */
static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
{
	if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
		clkdm_allow_idle(clkdm);
	else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
		 atomic_read(&clkdm->usecount) == 0)
		clkdm_sleep(clkdm);
	return 0;
}

static void __init prcm_setup_regs(void)
{
	int i, num_mem_banks;
	struct powerdomain *pwrdm;

	/*
	 * Enable autoidle
	 * XXX This should be handled by hwmod code or PRCM init code
	 */
	omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
			  OMAP2_PRCM_SYSCONFIG_OFFSET);

	/*
	 * Set CORE powerdomain memory banks to retain their contents
	 * during RETENTION
	 */
	num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
	for (i = 0; i < num_mem_banks; i++)
		pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);

	/* Set CORE powerdomain's next power state to RETENTION */
	pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);

	/*
	 * Set MPU powerdomain's next power state to RETENTION;
	 * preserve logic state during retention
	 */
	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);

	/* Force-power down DSP, GFX powerdomains */

	pwrdm = clkdm_get_pwrdm(dsp_clkdm);
	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
	clkdm_sleep(dsp_clkdm);

	pwrdm = clkdm_get_pwrdm(gfx_clkdm);
	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
	clkdm_sleep(gfx_clkdm);

	/* Enable hardware-supervised idle for all clkdms */
	clkdm_for_each(clkdms_setup, NULL);
	clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);

	/* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
	 * stabilisation */
	omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
				OMAP2_PRCM_CLKSSETUP_OFFSET);

	/* Configure automatic voltage transition */
	omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
				OMAP2_PRCM_VOLTSETUP_OFFSET);
	omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
				(0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
				OMAP24XX_MEMRETCTRL_MASK |
				(0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
				(0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
				OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);

	/* Enable wake-up events */
	omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
				WKUP_MOD, PM_WKEN);
}

static int __init omap2_pm_init(void)
{
	u32 l;

	if (!cpu_is_omap24xx())
		return -ENODEV;

	printk(KERN_INFO "Power Management for OMAP2 initializing\n");
	l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
	printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);

	/* Look up important powerdomains */

	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
	if (!mpu_pwrdm)
		pr_err("PM: mpu_pwrdm not found\n");

	core_pwrdm = pwrdm_lookup("core_pwrdm");
	if (!core_pwrdm)
		pr_err("PM: core_pwrdm not found\n");

	/* Look up important clockdomains */

	mpu_clkdm = clkdm_lookup("mpu_clkdm");
	if (!mpu_clkdm)
		pr_err("PM: mpu_clkdm not found\n");

	wkup_clkdm = clkdm_lookup("wkup_clkdm");
	if (!wkup_clkdm)
		pr_err("PM: wkup_clkdm not found\n");

	dsp_clkdm = clkdm_lookup("dsp_clkdm");
	if (!dsp_clkdm)
		pr_err("PM: dsp_clkdm not found\n");

	gfx_clkdm = clkdm_lookup("gfx_clkdm");
	if (!gfx_clkdm)
		pr_err("PM: gfx_clkdm not found\n");


	osc_ck = clk_get(NULL, "osc_ck");
	if (IS_ERR(osc_ck)) {
		printk(KERN_ERR "could not get osc_ck\n");
		return -ENODEV;
	}

	if (cpu_is_omap242x()) {
		emul_ck = clk_get(NULL, "emul_ck");
		if (IS_ERR(emul_ck)) {
			printk(KERN_ERR "could not get emul_ck\n");
			clk_put(osc_ck);
			return -ENODEV;
		}
	}

	prcm_setup_regs();

	/* Hack to prevent MPU retention when STI console is enabled. */
	{
		const struct omap_sti_console_config *sti;

		sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
				      struct omap_sti_console_config);
		if (sti != NULL && sti->enable)
			sti_console_enabled = 1;
	}

	/*
	 * We copy the assembler sleep/wakeup routines to SRAM.
	 * These routines need to be in SRAM as that's the only
	 * memory the MPU can see when it wakes up.
	 */
	if (cpu_is_omap24xx()) {
		omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
						 omap24xx_idle_loop_suspend_sz);

		omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
						    omap24xx_cpu_suspend_sz);
	}

	suspend_set_ops(&omap_pm_ops);
	pm_idle = omap2_pm_idle;

	return 0;
}

late_initcall(omap2_pm_init);
Commit	Line	Data
8bd22949 KH	1	/*
	2	* OMAP2 Power Management Routines
	3	*
	4	* Copyright (C) 2005 Texas Instruments, Inc.
	5	* Copyright (C) 2006-2008 Nokia Corporation
	6	*
	7	* Written by:
	8	* Richard Woodruff <r-woodruff2@ti.com>
	9	* Tony Lindgren
	10	* Juha Yrjola
	11	* Amit Kucheria <amit.kucheria@nokia.com>
	12	* Igor Stoppa <igor.stoppa@nokia.com>
	13	*
	14	* Based on pm.c for omap1
	15	*
	16	* This program is free software; you can redistribute it and/or modify
	17	* it under the terms of the GNU General Public License version 2 as
	18	* published by the Free Software Foundation.
	19	*/
	20
	21	#include <linux/suspend.h>
	22	#include <linux/sched.h>
	23	#include <linux/proc_fs.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/sysfs.h>
	26	#include <linux/module.h>
	27	#include <linux/delay.h>
	28	#include <linux/clk.h>
	29	#include <linux/io.h>
	30	#include <linux/irq.h>
	31	#include <linux/time.h>
	32	#include <linux/gpio.h>
0d8e2d0d	33	#include <linux/console.h>
8bd22949 KH	34
	35	#include <asm/mach/time.h>
	36	#include <asm/mach/irq.h>
	37	#include <asm/mach-types.h>
	38
	39	#include <mach/irqs.h>
ce491cf8 TL	40	#include <plat/clock.h>
ce491cf8 TL	41	#include <plat/sram.h>
ce491cf8 TL	42	#include <plat/dma.h>
ce491cf8 TL	43	#include <plat/board.h>
8bd22949	44
59fb659b	45	#include "prm2xxx_3xxx.h"
8bd22949	46	#include "prm-regbits-24xx.h"
59fb659b	47	#include "cm2xxx_3xxx.h"
8bd22949 KH	48	#include "cm-regbits-24xx.h"
	49	#include "sdrc.h"
	50	#include "pm.h"
4814ced5	51	#include "control.h"
8bd22949	52
72e06d08	53	#include "powerdomain.h"
1540f214	54	#include "clockdomain.h"
8bd22949	55
e83df17f KH	56	#ifdef CONFIG_SUSPEND
	57	static suspend_state_t suspend_state = PM_SUSPEND_ON;
	58	static inline bool is_suspending(void)
	59	{
	60	return (suspend_state != PM_SUSPEND_ON);
	61	}
	62	#else
	63	static inline bool is_suspending(void)
	64	{
	65	return false;
	66	}
	67	#endif
	68
8bd22949 KH	69	static void (*omap2_sram_idle)(void);
	70	static void (omap2_sram_suspend)(u32 dllctrl, void __iomem sdrc_dlla_ctrl,
	71	void __iomem *sdrc_power);
	72
369d5614 PW	73	static struct powerdomain mpu_pwrdm, core_pwrdm;
369d5614 PW	74	static struct clockdomain dsp_clkdm, mpu_clkdm, wkup_clkdm, gfx_clkdm;
8bd22949 KH	75
	76	static struct clk osc_ck, emul_ck;
	77
	78	static int omap2_fclks_active(void)
	79	{
	80	u32 f1, f2;
	81
c4d7e58f PW	82	f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
c4d7e58f PW	83	f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
4af4016c KH	84
4af4016c KH	85	/* Ignore UART clocks. These are handled by UART core (serial.c) */
2fd0f75c PW	86	f1 &= ~(OMAP24XX_EN_UART1_MASK \| OMAP24XX_EN_UART2_MASK);
2fd0f75c PW	87	f2 &= ~OMAP24XX_EN_UART3_MASK;
4af4016c	88
8bd22949 KH	89	if (f1 \| f2)
	90	return 1;
	91	return 0;
	92	}
	93
8bd22949 KH	94	static void omap2_enter_full_retention(void)
	95	{
	96	u32 l;
8bd22949 KH	97
	98	/* There is 1 reference hold for all children of the oscillator
	99	* clock, the following will remove it. If no one else uses the
	100	* oscillator itself it will be disabled if/when we enter retention
	101	* mode.
	102	*/
	103	clk_disable(osc_ck);
	104
	105	/* Clear old wake-up events */
	106	/* REVISIT: These write to reserved bits? */
c4d7e58f PW	107	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	108	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
	109	omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
8bd22949 KH	110
	111	/*
	112	* Set MPU powerdomain's next power state to RETENTION;
	113	* preserve logic state during retention
	114	*/
	115	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
	116	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
	117
	118	/* Workaround to kill USB */
	119	l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) \| OMAP24XX_USBSTANDBYCTRL;
	120	omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
	121
72e06d08	122	omap2_gpio_prepare_for_idle(0);
8bd22949	123
8bd22949 KH	124	/* One last check for pending IRQs to avoid extra latency due
8bd22949 KH	125	* to sleeping unnecessarily. */
94434535	126	if (omap_irq_pending())
8bd22949 KH	127	goto no_sleep;
8bd22949 KH	128
0d8e2d0d	129	/* Block console output in case it is on one of the OMAP UARTs */
e83df17f	130	if (!is_suspending())
ac751efa	131	if (!console_trylock())
e83df17f	132	goto no_sleep;
0d8e2d0d	133
4af4016c KH	134	omap_uart_prepare_idle(0);
	135	omap_uart_prepare_idle(1);
	136	omap_uart_prepare_idle(2);
	137
8bd22949 KH	138	/* Jump to SRAM suspend code */
	139	omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
	140	OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
	141	OMAP_SDRC_REGADDR(SDRC_POWER));
8bd22949	142
4af4016c KH	143	omap_uart_resume_idle(2);
	144	omap_uart_resume_idle(1);
	145	omap_uart_resume_idle(0);
	146
e83df17f	147	if (!is_suspending())
ac751efa	148	console_unlock();
0d8e2d0d	149
4af4016c	150	no_sleep:
43ffcd9a	151	omap2_gpio_resume_after_idle();
8bd22949 KH	152
	153	clk_enable(osc_ck);
	154
	155	/* clear CORE wake-up events */
c4d7e58f PW	156	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
c4d7e58f PW	157	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
8bd22949 KH	158
8bd22949 KH	159	/* wakeup domain events - bit 1: GPT1, bit5 GPIO */
c4d7e58f	160	omap2_prm_clear_mod_reg_bits(0x4 \| 0x1, WKUP_MOD, PM_WKST);
8bd22949 KH	161
8bd22949 KH	162	/* MPU domain wake events */
c4d7e58f	163	l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
8bd22949	164	if (l & 0x01)
c4d7e58f	165	omap2_prm_write_mod_reg(0x01, OCP_MOD,
8bd22949 KH	166	OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
8bd22949 KH	167	if (l & 0x20)
c4d7e58f	168	omap2_prm_write_mod_reg(0x20, OCP_MOD,
8bd22949 KH	169	OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	170
	171	/* Mask future PRCM-to-MPU interrupts */
c4d7e58f	172	omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
8bd22949 KH	173	}
	174
	175	static int omap2_i2c_active(void)
	176	{
	177	u32 l;
	178
c4d7e58f	179	l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
f38ca10a	180	return l & (OMAP2420_EN_I2C2_MASK \| OMAP2420_EN_I2C1_MASK);
8bd22949 KH	181	}
	182
	183	static int sti_console_enabled;
	184
	185	static int omap2_allow_mpu_retention(void)
	186	{
	187	u32 l;
	188
	189	/* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
c4d7e58f	190	l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
2fd0f75c PW	191	if (l & (OMAP2420_EN_MMC_MASK \| OMAP24XX_EN_UART2_MASK \|
	192	OMAP24XX_EN_UART1_MASK \| OMAP24XX_EN_MCSPI2_MASK \|
	193	OMAP24XX_EN_MCSPI1_MASK \| OMAP24XX_EN_DSS1_MASK))
8bd22949 KH	194	return 0;
8bd22949 KH	195	/* Check for UART3. */
c4d7e58f	196	l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
2fd0f75c	197	if (l & OMAP24XX_EN_UART3_MASK)
8bd22949 KH	198	return 0;
	199	if (sti_console_enabled)
	200	return 0;
	201
	202	return 1;
	203	}
	204
	205	static void omap2_enter_mpu_retention(void)
	206	{
	207	int only_idle = 0;
8bd22949 KH	208
	209	/* Putting MPU into the WFI state while a transfer is active
	210	* seems to cause the I2C block to timeout. Why? Good question. */
	211	if (omap2_i2c_active())
	212	return;
	213
	214	/* The peripherals seem not to be able to wake up the MPU when
	215	* it is in retention mode. */
	216	if (omap2_allow_mpu_retention()) {
	217	/* REVISIT: These write to reserved bits? */
c4d7e58f PW	218	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	219	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
	220	omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
8bd22949 KH	221
8bd22949 KH	222	/* Try to enter MPU retention */
c4d7e58f	223	omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) \|
2fd0f75c	224	OMAP_LOGICRETSTATE_MASK,
37903009	225	MPU_MOD, OMAP2_PM_PWSTCTRL);
8bd22949 KH	226	} else {
	227	/* Block MPU retention */
	228
c4d7e58f	229	omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
37903009	230	OMAP2_PM_PWSTCTRL);
8bd22949 KH	231	only_idle = 1;
	232	}
	233
8bd22949	234	omap2_sram_idle();
8bd22949 KH	235	}
	236
	237	static int omap2_can_sleep(void)
	238	{
	239	if (omap2_fclks_active())
	240	return 0;
503923ee KH	241	if (!omap_uart_can_sleep())
503923ee KH	242	return 0;
8bd22949 KH	243	if (osc_ck->usecount > 1)
	244	return 0;
	245	if (omap_dma_running())
	246	return 0;
	247
	248	return 1;
	249	}
	250
	251	static void omap2_pm_idle(void)
	252	{
	253	local_irq_disable();
	254	local_fiq_disable();
	255
	256	if (!omap2_can_sleep()) {
94434535	257	if (omap_irq_pending())
8bd22949 KH	258	goto out;
	259	omap2_enter_mpu_retention();
	260	goto out;
	261	}
	262
94434535	263	if (omap_irq_pending())
8bd22949 KH	264	goto out;
	265
	266	omap2_enter_full_retention();
	267
	268	out:
	269	local_fiq_enable();
	270	local_irq_enable();
	271	}
	272
05fad3e7	273	#ifdef CONFIG_SUSPEND
e83df17f KH	274	static int omap2_pm_begin(suspend_state_t state)
e83df17f KH	275	{
8bd22949	276	disable_hlt();
c166381d	277	suspend_state = state;
8bd22949 KH	278	return 0;
	279	}
	280
	281	static int omap2_pm_suspend(void)
	282	{
	283	u32 wken_wkup, mir1;
	284
c4d7e58f	285	wken_wkup = omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
2fd0f75c	286	wken_wkup &= ~OMAP24XX_EN_GPT1_MASK;
c4d7e58f	287	omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
8bd22949 KH	288
	289	/* Mask GPT1 */
	290	mir1 = omap_readl(0x480fe0a4);
	291	omap_writel(1 << 5, 0x480fe0ac);
	292
4af4016c	293	omap_uart_prepare_suspend();
8bd22949 KH	294	omap2_enter_full_retention();
	295
	296	omap_writel(mir1, 0x480fe0a4);
c4d7e58f	297	omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
8bd22949 KH	298
	299	return 0;
	300	}
	301
	302	static int omap2_pm_enter(suspend_state_t state)
	303	{
	304	int ret = 0;
	305
	306	switch (state) {
	307	case PM_SUSPEND_STANDBY:
	308	case PM_SUSPEND_MEM:
	309	ret = omap2_pm_suspend();
	310	break;
	311	default:
	312	ret = -EINVAL;
	313	}
	314
	315	return ret;
	316	}
	317
e83df17f KH	318	static void omap2_pm_end(void)
	319	{
	320	suspend_state = PM_SUSPEND_ON;
c166381d	321	enable_hlt();
e83df17f KH	322	}
e83df17f KH	323
2f55ac07	324	static const struct platform_suspend_ops omap_pm_ops = {
e83df17f	325	.begin = omap2_pm_begin,
8bd22949	326	.enter = omap2_pm_enter,
e83df17f	327	.end = omap2_pm_end,
8bd22949 KH	328	.valid = suspend_valid_only_mem,
8bd22949 KH	329	};
05fad3e7 KH	330	#else
	331	static const struct platform_suspend_ops __initdata omap_pm_ops;
	332	#endif /* CONFIG_SUSPEND */
8bd22949	333
369d5614 PW	334	/* XXX This function should be shareable between OMAP2xxx and OMAP3 */
369d5614 PW	335	static int __init clkdms_setup(struct clockdomain clkdm, void unused)
8bd22949	336	{
369d5614	337	if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
5cd1937b	338	clkdm_allow_idle(clkdm);
369d5614 PW	339	else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
369d5614 PW	340	atomic_read(&clkdm->usecount) == 0)
68b921ad	341	clkdm_sleep(clkdm);
8bd22949 KH	342	return 0;
	343	}
	344
	345	static void __init prcm_setup_regs(void)
	346	{
	347	int i, num_mem_banks;
	348	struct powerdomain *pwrdm;
	349
4ef70c06 PW	350	/*
	351	* Enable autoidle
	352	* XXX This should be handled by hwmod code or PRCM init code
	353	*/
c4d7e58f	354	omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
8bd22949 KH	355	OMAP2_PRCM_SYSCONFIG_OFFSET);
8bd22949 KH	356
8bd22949 KH	357	/*
	358	* Set CORE powerdomain memory banks to retain their contents
	359	* during RETENTION
	360	*/
	361	num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
	362	for (i = 0; i < num_mem_banks; i++)
	363	pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
	364
	365	/* Set CORE powerdomain's next power state to RETENTION */
	366	pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
	367
	368	/*
	369	* Set MPU powerdomain's next power state to RETENTION;
	370	* preserve logic state during retention
	371	*/
	372	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
	373	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
	374
	375	/* Force-power down DSP, GFX powerdomains */
	376
	377	pwrdm = clkdm_get_pwrdm(dsp_clkdm);
	378	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
68b921ad	379	clkdm_sleep(dsp_clkdm);
8bd22949 KH	380
	381	pwrdm = clkdm_get_pwrdm(gfx_clkdm);
	382	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
68b921ad	383	clkdm_sleep(gfx_clkdm);
8bd22949	384
51d070af	385	/* Enable hardware-supervised idle for all clkdms */
369d5614 PW	386	clkdm_for_each(clkdms_setup, NULL);
369d5614 PW	387	clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
8bd22949	388
8bd22949 KH	389	/* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
8bd22949 KH	390	* stabilisation */
c4d7e58f PW	391	omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
c4d7e58f PW	392	OMAP2_PRCM_CLKSSETUP_OFFSET);
8bd22949 KH	393
8bd22949 KH	394	/* Configure automatic voltage transition */
c4d7e58f PW	395	omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
	396	OMAP2_PRCM_VOLTSETUP_OFFSET);
	397	omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK \|
	398	(0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) \|
	399	OMAP24XX_MEMRETCTRL_MASK \|
	400	(0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) \|
	401	(0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
	402	OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
8bd22949 KH	403
8bd22949 KH	404	/* Enable wake-up events */
c4d7e58f PW	405	omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK \| OMAP24XX_EN_GPT1_MASK,
c4d7e58f PW	406	WKUP_MOD, PM_WKEN);
8bd22949 KH	407	}
8bd22949 KH	408
7cc515f7	409	static int __init omap2_pm_init(void)
8bd22949 KH	410	{
	411	u32 l;
	412
	413	if (!cpu_is_omap24xx())
	414	return -ENODEV;
	415
	416	printk(KERN_INFO "Power Management for OMAP2 initializing\n");
c4d7e58f	417	l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
8bd22949 KH	418	printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
8bd22949 KH	419
369d5614	420	/* Look up important powerdomains */
8bd22949 KH	421
	422	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
	423	if (!mpu_pwrdm)
	424	pr_err("PM: mpu_pwrdm not found\n");
	425
	426	core_pwrdm = pwrdm_lookup("core_pwrdm");
	427	if (!core_pwrdm)
	428	pr_err("PM: core_pwrdm not found\n");
	429
369d5614 PW	430	/* Look up important clockdomains */
	431
	432	mpu_clkdm = clkdm_lookup("mpu_clkdm");
	433	if (!mpu_clkdm)
	434	pr_err("PM: mpu_clkdm not found\n");
	435
	436	wkup_clkdm = clkdm_lookup("wkup_clkdm");
	437	if (!wkup_clkdm)
	438	pr_err("PM: wkup_clkdm not found\n");
	439
8bd22949 KH	440	dsp_clkdm = clkdm_lookup("dsp_clkdm");
8bd22949 KH	441	if (!dsp_clkdm)
369d5614	442	pr_err("PM: dsp_clkdm not found\n");
8bd22949 KH	443
	444	gfx_clkdm = clkdm_lookup("gfx_clkdm");
	445	if (!gfx_clkdm)
	446	pr_err("PM: gfx_clkdm not found\n");
	447
	448
	449	osc_ck = clk_get(NULL, "osc_ck");
	450	if (IS_ERR(osc_ck)) {
	451	printk(KERN_ERR "could not get osc_ck\n");
	452	return -ENODEV;
	453	}
	454
	455	if (cpu_is_omap242x()) {
	456	emul_ck = clk_get(NULL, "emul_ck");
	457	if (IS_ERR(emul_ck)) {
	458	printk(KERN_ERR "could not get emul_ck\n");
	459	clk_put(osc_ck);
	460	return -ENODEV;
	461	}
	462	}
	463
	464	prcm_setup_regs();
	465
	466	/* Hack to prevent MPU retention when STI console is enabled. */
	467	{
	468	const struct omap_sti_console_config *sti;
	469
	470	sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
	471	struct omap_sti_console_config);
	472	if (sti != NULL && sti->enable)
	473	sti_console_enabled = 1;
	474	}
	475
	476	/*
	477	* We copy the assembler sleep/wakeup routines to SRAM.
	478	* These routines need to be in SRAM as that's the only
	479	* memory the MPU can see when it wakes up.
	480	*/
	481	if (cpu_is_omap24xx()) {
	482	omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
	483	omap24xx_idle_loop_suspend_sz);
	484
	485	omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
	486	omap24xx_cpu_suspend_sz);
	487	}
	488
	489	suspend_set_ops(&omap_pm_ops);
	490	pm_idle = omap2_pm_idle;
	491
	492	return 0;
	493	}
	494
	495	late_initcall(omap2_pm_init);