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8bd22949 KH |
1 | /* |
2 | * OMAP2 Power Management Routines | |
3 | * | |
4 | * Copyright (C) 2005 Texas Instruments, Inc. | |
5 | * Copyright (C) 2006-2008 Nokia Corporation | |
6 | * | |
7 | * Written by: | |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
9 | * Tony Lindgren | |
10 | * Juha Yrjola | |
11 | * Amit Kucheria <amit.kucheria@nokia.com> | |
12 | * Igor Stoppa <igor.stoppa@nokia.com> | |
13 | * | |
14 | * Based on pm.c for omap1 | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/suspend.h> | |
22 | #include <linux/sched.h> | |
23 | #include <linux/proc_fs.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/sysfs.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/clk.h> | |
8bd22949 KH |
29 | #include <linux/irq.h> |
30 | #include <linux/time.h> | |
31 | #include <linux/gpio.h> | |
32 | ||
33 | #include <asm/mach/time.h> | |
34 | #include <asm/mach/irq.h> | |
35 | #include <asm/mach-types.h> | |
9f97da78 | 36 | #include <asm/system_misc.h> |
8bd22949 | 37 | |
ce491cf8 TL |
38 | #include <plat/clock.h> |
39 | #include <plat/sram.h> | |
ce491cf8 | 40 | #include <plat/dma.h> |
8bd22949 | 41 | |
ee0839c2 TL |
42 | #include <mach/irqs.h> |
43 | ||
4e65331c | 44 | #include "common.h" |
59fb659b | 45 | #include "prm2xxx_3xxx.h" |
8bd22949 | 46 | #include "prm-regbits-24xx.h" |
59fb659b | 47 | #include "cm2xxx_3xxx.h" |
8bd22949 KH |
48 | #include "cm-regbits-24xx.h" |
49 | #include "sdrc.h" | |
50 | #include "pm.h" | |
4814ced5 | 51 | #include "control.h" |
72e06d08 | 52 | #include "powerdomain.h" |
1540f214 | 53 | #include "clockdomain.h" |
8bd22949 KH |
54 | |
55 | static void (*omap2_sram_idle)(void); | |
56 | static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl, | |
57 | void __iomem *sdrc_power); | |
58 | ||
369d5614 PW |
59 | static struct powerdomain *mpu_pwrdm, *core_pwrdm; |
60 | static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm; | |
8bd22949 KH |
61 | |
62 | static struct clk *osc_ck, *emul_ck; | |
63 | ||
64 | static int omap2_fclks_active(void) | |
65 | { | |
66 | u32 f1, f2; | |
67 | ||
c4d7e58f PW |
68 | f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); |
69 | f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); | |
4af4016c | 70 | |
1e056ddd | 71 | return (f1 | f2) ? 1 : 0; |
8bd22949 KH |
72 | } |
73 | ||
1416408d | 74 | static int omap2_enter_full_retention(void) |
8bd22949 KH |
75 | { |
76 | u32 l; | |
8bd22949 KH |
77 | |
78 | /* There is 1 reference hold for all children of the oscillator | |
79 | * clock, the following will remove it. If no one else uses the | |
80 | * oscillator itself it will be disabled if/when we enter retention | |
81 | * mode. | |
82 | */ | |
83 | clk_disable(osc_ck); | |
84 | ||
85 | /* Clear old wake-up events */ | |
86 | /* REVISIT: These write to reserved bits? */ | |
c4d7e58f PW |
87 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); |
88 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); | |
89 | omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); | |
8bd22949 KH |
90 | |
91 | /* | |
92 | * Set MPU powerdomain's next power state to RETENTION; | |
93 | * preserve logic state during retention | |
94 | */ | |
95 | pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET); | |
96 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); | |
97 | ||
98 | /* Workaround to kill USB */ | |
99 | l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL; | |
100 | omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0); | |
101 | ||
72e06d08 | 102 | omap2_gpio_prepare_for_idle(0); |
8bd22949 | 103 | |
8bd22949 KH |
104 | /* One last check for pending IRQs to avoid extra latency due |
105 | * to sleeping unnecessarily. */ | |
94434535 | 106 | if (omap_irq_pending()) |
8bd22949 KH |
107 | goto no_sleep; |
108 | ||
109 | /* Jump to SRAM suspend code */ | |
110 | omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL), | |
111 | OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL), | |
112 | OMAP_SDRC_REGADDR(SDRC_POWER)); | |
8bd22949 | 113 | |
4af4016c | 114 | no_sleep: |
43ffcd9a | 115 | omap2_gpio_resume_after_idle(); |
8bd22949 KH |
116 | |
117 | clk_enable(osc_ck); | |
118 | ||
119 | /* clear CORE wake-up events */ | |
c4d7e58f PW |
120 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); |
121 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); | |
8bd22949 KH |
122 | |
123 | /* wakeup domain events - bit 1: GPT1, bit5 GPIO */ | |
c4d7e58f | 124 | omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST); |
8bd22949 KH |
125 | |
126 | /* MPU domain wake events */ | |
c4d7e58f | 127 | l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); |
8bd22949 | 128 | if (l & 0x01) |
c4d7e58f | 129 | omap2_prm_write_mod_reg(0x01, OCP_MOD, |
8bd22949 KH |
130 | OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); |
131 | if (l & 0x20) | |
c4d7e58f | 132 | omap2_prm_write_mod_reg(0x20, OCP_MOD, |
8bd22949 KH |
133 | OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); |
134 | ||
135 | /* Mask future PRCM-to-MPU interrupts */ | |
c4d7e58f | 136 | omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); |
1416408d PW |
137 | |
138 | return 0; | |
8bd22949 KH |
139 | } |
140 | ||
141 | static int omap2_i2c_active(void) | |
142 | { | |
143 | u32 l; | |
144 | ||
c4d7e58f | 145 | l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); |
f38ca10a | 146 | return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK); |
8bd22949 KH |
147 | } |
148 | ||
149 | static int sti_console_enabled; | |
150 | ||
151 | static int omap2_allow_mpu_retention(void) | |
152 | { | |
153 | u32 l; | |
154 | ||
155 | /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */ | |
c4d7e58f | 156 | l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); |
2fd0f75c PW |
157 | if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK | |
158 | OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK | | |
159 | OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK)) | |
8bd22949 KH |
160 | return 0; |
161 | /* Check for UART3. */ | |
c4d7e58f | 162 | l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); |
2fd0f75c | 163 | if (l & OMAP24XX_EN_UART3_MASK) |
8bd22949 KH |
164 | return 0; |
165 | if (sti_console_enabled) | |
166 | return 0; | |
167 | ||
168 | return 1; | |
169 | } | |
170 | ||
171 | static void omap2_enter_mpu_retention(void) | |
172 | { | |
8bd22949 KH |
173 | /* Putting MPU into the WFI state while a transfer is active |
174 | * seems to cause the I2C block to timeout. Why? Good question. */ | |
175 | if (omap2_i2c_active()) | |
176 | return; | |
177 | ||
178 | /* The peripherals seem not to be able to wake up the MPU when | |
179 | * it is in retention mode. */ | |
180 | if (omap2_allow_mpu_retention()) { | |
181 | /* REVISIT: These write to reserved bits? */ | |
c4d7e58f PW |
182 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); |
183 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); | |
184 | omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); | |
8bd22949 KH |
185 | |
186 | /* Try to enter MPU retention */ | |
c4d7e58f | 187 | omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | |
2fd0f75c | 188 | OMAP_LOGICRETSTATE_MASK, |
37903009 | 189 | MPU_MOD, OMAP2_PM_PWSTCTRL); |
8bd22949 KH |
190 | } else { |
191 | /* Block MPU retention */ | |
192 | ||
c4d7e58f | 193 | omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD, |
37903009 | 194 | OMAP2_PM_PWSTCTRL); |
8bd22949 KH |
195 | } |
196 | ||
8bd22949 | 197 | omap2_sram_idle(); |
8bd22949 KH |
198 | } |
199 | ||
200 | static int omap2_can_sleep(void) | |
201 | { | |
202 | if (omap2_fclks_active()) | |
203 | return 0; | |
204 | if (osc_ck->usecount > 1) | |
205 | return 0; | |
206 | if (omap_dma_running()) | |
207 | return 0; | |
208 | ||
209 | return 1; | |
210 | } | |
211 | ||
212 | static void omap2_pm_idle(void) | |
213 | { | |
8bd22949 KH |
214 | local_fiq_disable(); |
215 | ||
216 | if (!omap2_can_sleep()) { | |
94434535 | 217 | if (omap_irq_pending()) |
8bd22949 KH |
218 | goto out; |
219 | omap2_enter_mpu_retention(); | |
220 | goto out; | |
221 | } | |
222 | ||
94434535 | 223 | if (omap_irq_pending()) |
8bd22949 KH |
224 | goto out; |
225 | ||
226 | omap2_enter_full_retention(); | |
227 | ||
228 | out: | |
229 | local_fiq_enable(); | |
8bd22949 KH |
230 | } |
231 | ||
8bd22949 KH |
232 | static void __init prcm_setup_regs(void) |
233 | { | |
234 | int i, num_mem_banks; | |
235 | struct powerdomain *pwrdm; | |
236 | ||
4ef70c06 PW |
237 | /* |
238 | * Enable autoidle | |
239 | * XXX This should be handled by hwmod code or PRCM init code | |
240 | */ | |
c4d7e58f | 241 | omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD, |
8bd22949 KH |
242 | OMAP2_PRCM_SYSCONFIG_OFFSET); |
243 | ||
8bd22949 KH |
244 | /* |
245 | * Set CORE powerdomain memory banks to retain their contents | |
246 | * during RETENTION | |
247 | */ | |
248 | num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm); | |
249 | for (i = 0; i < num_mem_banks; i++) | |
250 | pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET); | |
251 | ||
252 | /* Set CORE powerdomain's next power state to RETENTION */ | |
253 | pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET); | |
254 | ||
255 | /* | |
256 | * Set MPU powerdomain's next power state to RETENTION; | |
257 | * preserve logic state during retention | |
258 | */ | |
259 | pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET); | |
260 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); | |
261 | ||
262 | /* Force-power down DSP, GFX powerdomains */ | |
263 | ||
264 | pwrdm = clkdm_get_pwrdm(dsp_clkdm); | |
265 | pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); | |
68b921ad | 266 | clkdm_sleep(dsp_clkdm); |
8bd22949 KH |
267 | |
268 | pwrdm = clkdm_get_pwrdm(gfx_clkdm); | |
269 | pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF); | |
68b921ad | 270 | clkdm_sleep(gfx_clkdm); |
8bd22949 | 271 | |
51d070af | 272 | /* Enable hardware-supervised idle for all clkdms */ |
92206fd2 | 273 | clkdm_for_each(omap_pm_clkdms_setup, NULL); |
369d5614 | 274 | clkdm_add_wkdep(mpu_clkdm, wkup_clkdm); |
8bd22949 | 275 | |
1416408d PW |
276 | #ifdef CONFIG_SUSPEND |
277 | omap_pm_suspend = omap2_enter_full_retention; | |
278 | #endif | |
279 | ||
8bd22949 KH |
280 | /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk |
281 | * stabilisation */ | |
c4d7e58f PW |
282 | omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, |
283 | OMAP2_PRCM_CLKSSETUP_OFFSET); | |
8bd22949 KH |
284 | |
285 | /* Configure automatic voltage transition */ | |
c4d7e58f PW |
286 | omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, |
287 | OMAP2_PRCM_VOLTSETUP_OFFSET); | |
288 | omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK | | |
289 | (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) | | |
290 | OMAP24XX_MEMRETCTRL_MASK | | |
291 | (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) | | |
292 | (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT), | |
293 | OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET); | |
8bd22949 KH |
294 | |
295 | /* Enable wake-up events */ | |
c4d7e58f PW |
296 | omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK, |
297 | WKUP_MOD, PM_WKEN); | |
8bd22949 KH |
298 | } |
299 | ||
bbd707ac | 300 | int __init omap2_pm_init(void) |
8bd22949 KH |
301 | { |
302 | u32 l; | |
303 | ||
8bd22949 | 304 | printk(KERN_INFO "Power Management for OMAP2 initializing\n"); |
c4d7e58f | 305 | l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET); |
8bd22949 KH |
306 | printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); |
307 | ||
369d5614 | 308 | /* Look up important powerdomains */ |
8bd22949 KH |
309 | |
310 | mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); | |
311 | if (!mpu_pwrdm) | |
312 | pr_err("PM: mpu_pwrdm not found\n"); | |
313 | ||
314 | core_pwrdm = pwrdm_lookup("core_pwrdm"); | |
315 | if (!core_pwrdm) | |
316 | pr_err("PM: core_pwrdm not found\n"); | |
317 | ||
369d5614 PW |
318 | /* Look up important clockdomains */ |
319 | ||
320 | mpu_clkdm = clkdm_lookup("mpu_clkdm"); | |
321 | if (!mpu_clkdm) | |
322 | pr_err("PM: mpu_clkdm not found\n"); | |
323 | ||
324 | wkup_clkdm = clkdm_lookup("wkup_clkdm"); | |
325 | if (!wkup_clkdm) | |
326 | pr_err("PM: wkup_clkdm not found\n"); | |
327 | ||
8bd22949 KH |
328 | dsp_clkdm = clkdm_lookup("dsp_clkdm"); |
329 | if (!dsp_clkdm) | |
369d5614 | 330 | pr_err("PM: dsp_clkdm not found\n"); |
8bd22949 KH |
331 | |
332 | gfx_clkdm = clkdm_lookup("gfx_clkdm"); | |
333 | if (!gfx_clkdm) | |
334 | pr_err("PM: gfx_clkdm not found\n"); | |
335 | ||
336 | ||
337 | osc_ck = clk_get(NULL, "osc_ck"); | |
338 | if (IS_ERR(osc_ck)) { | |
339 | printk(KERN_ERR "could not get osc_ck\n"); | |
340 | return -ENODEV; | |
341 | } | |
342 | ||
343 | if (cpu_is_omap242x()) { | |
344 | emul_ck = clk_get(NULL, "emul_ck"); | |
345 | if (IS_ERR(emul_ck)) { | |
346 | printk(KERN_ERR "could not get emul_ck\n"); | |
347 | clk_put(osc_ck); | |
348 | return -ENODEV; | |
349 | } | |
350 | } | |
351 | ||
352 | prcm_setup_regs(); | |
353 | ||
8bd22949 KH |
354 | /* |
355 | * We copy the assembler sleep/wakeup routines to SRAM. | |
356 | * These routines need to be in SRAM as that's the only | |
357 | * memory the MPU can see when it wakes up. | |
358 | */ | |
bbd707ac SG |
359 | omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend, |
360 | omap24xx_idle_loop_suspend_sz); | |
8bd22949 | 361 | |
bbd707ac SG |
362 | omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend, |
363 | omap24xx_cpu_suspend_sz); | |
8bd22949 | 364 | |
0bcd24b0 | 365 | arm_pm_idle = omap2_pm_idle; |
8bd22949 KH |
366 | |
367 | return 0; | |
368 | } |