[deliverable/linux.git] / arch / arm / mach-omap2 / pm24xx.c

/*
 * OMAP2 Power Management Routines
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 * Copyright (C) 2006-2008 Nokia Corporation
 *
 * Written by:
 * Richard Woodruff <r-woodruff2@ti.com>
 * Tony Lindgren
 * Juha Yrjola
 * Amit Kucheria <amit.kucheria@nokia.com>
 * Igor Stoppa <igor.stoppa@nokia.com>
 *
 * Based on pm.c for omap1
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/suspend.h>
#include <linux/sched.h>
#include <linux/proc_fs.h>
#include <linux/interrupt.h>
#include <linux/sysfs.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/time.h>
#include <linux/gpio.h>

#include <asm/mach/time.h>
#include <asm/mach/irq.h>
#include <asm/mach-types.h>

#include <mach/irqs.h>
#include <plat/clock.h>
#include <plat/sram.h>
#include <plat/control.h>
#include <plat/dma.h>
#include <plat/board.h>

#include "prm.h"
#include "prm-regbits-24xx.h"
#include "cm.h"
#include "cm-regbits-24xx.h"
#include "sdrc.h"
#include "pm.h"

#include <plat/powerdomain.h>
#include <plat/clockdomain.h>

static void (*omap2_sram_idle)(void);
static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
				  void __iomem *sdrc_power);

static struct powerdomain *mpu_pwrdm, *core_pwrdm;
static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;

static struct clk *osc_ck, *emul_ck;

static int omap2_fclks_active(void)
{
	u32 f1, f2;

	f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);

	/* Ignore UART clocks.  These are handled by UART core (serial.c) */
	f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK);
	f2 &= ~OMAP24XX_EN_UART3_MASK;

	if (f1 | f2)
		return 1;
	return 0;
}

static void omap2_enter_full_retention(void)
{
	u32 l;
	struct timespec ts_preidle, ts_postidle, ts_idle;

	/* There is 1 reference hold for all children of the oscillator
	 * clock, the following will remove it. If no one else uses the
	 * oscillator itself it will be disabled if/when we enter retention
	 * mode.
	 */
	clk_disable(osc_ck);

	/* Clear old wake-up events */
	/* REVISIT: These write to reserved bits? */
	prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
	prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);

	/*
	 * Set MPU powerdomain's next power state to RETENTION;
	 * preserve logic state during retention
	 */
	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);

	/* Workaround to kill USB */
	l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
	omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);

	omap2_gpio_prepare_for_idle(PWRDM_POWER_RET);

	if (omap2_pm_debug) {
		omap2_pm_dump(0, 0, 0);
		getnstimeofday(&ts_preidle);
	}

	/* One last check for pending IRQs to avoid extra latency due
	 * to sleeping unnecessarily. */
	if (omap_irq_pending())
		goto no_sleep;

	omap_uart_prepare_idle(0);
	omap_uart_prepare_idle(1);
	omap_uart_prepare_idle(2);

	/* Jump to SRAM suspend code */
	omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
			   OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
			   OMAP_SDRC_REGADDR(SDRC_POWER));

	omap_uart_resume_idle(2);
	omap_uart_resume_idle(1);
	omap_uart_resume_idle(0);

no_sleep:
	if (omap2_pm_debug) {
		unsigned long long tmp;

		getnstimeofday(&ts_postidle);
		ts_idle = timespec_sub(ts_postidle, ts_preidle);
		tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
		omap2_pm_dump(0, 1, tmp);
	}
	omap2_gpio_resume_after_idle();

	clk_enable(osc_ck);

	/* clear CORE wake-up events */
	prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);

	/* wakeup domain events - bit 1: GPT1, bit5 GPIO */
	prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);

	/* MPU domain wake events */
	l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	if (l & 0x01)
		prm_write_mod_reg(0x01, OCP_MOD,
				  OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	if (l & 0x20)
		prm_write_mod_reg(0x20, OCP_MOD,
				  OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);

	/* Mask future PRCM-to-MPU interrupts */
	prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
}

static int omap2_i2c_active(void)
{
	u32 l;

	l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
}

static int sti_console_enabled;

static int omap2_allow_mpu_retention(void)
{
	u32 l;

	/* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
	l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
		 OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
		 OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
		return 0;
	/* Check for UART3. */
	l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
	if (l & OMAP24XX_EN_UART3_MASK)
		return 0;
	if (sti_console_enabled)
		return 0;

	return 1;
}

static void omap2_enter_mpu_retention(void)
{
	int only_idle = 0;
	struct timespec ts_preidle, ts_postidle, ts_idle;

	/* Putting MPU into the WFI state while a transfer is active
	 * seems to cause the I2C block to timeout. Why? Good question. */
	if (omap2_i2c_active())
		return;

	/* The peripherals seem not to be able to wake up the MPU when
	 * it is in retention mode. */
	if (omap2_allow_mpu_retention()) {
		/* REVISIT: These write to reserved bits? */
		prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
		prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
		prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);

		/* Try to enter MPU retention */
		prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
				  OMAP_LOGICRETSTATE_MASK,
				  MPU_MOD, OMAP2_PM_PWSTCTRL);
	} else {
		/* Block MPU retention */

		prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
						 OMAP2_PM_PWSTCTRL);
		only_idle = 1;
	}

	if (omap2_pm_debug) {
		omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
		getnstimeofday(&ts_preidle);
	}

	omap2_sram_idle();

	if (omap2_pm_debug) {
		unsigned long long tmp;

		getnstimeofday(&ts_postidle);
		ts_idle = timespec_sub(ts_postidle, ts_preidle);
		tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
		omap2_pm_dump(only_idle ? 2 : 1, 1, tmp);
	}
}

static int omap2_can_sleep(void)
{
	if (omap2_fclks_active())
		return 0;
	if (!omap_uart_can_sleep())
		return 0;
	if (osc_ck->usecount > 1)
		return 0;
	if (omap_dma_running())
		return 0;

	return 1;
}

static void omap2_pm_idle(void)
{
	local_irq_disable();
	local_fiq_disable();

	if (!omap2_can_sleep()) {
		if (omap_irq_pending())
			goto out;
		omap2_enter_mpu_retention();
		goto out;
	}

	if (omap_irq_pending())
		goto out;

	omap2_enter_full_retention();

out:
	local_fiq_enable();
	local_irq_enable();
}

static int omap2_pm_prepare(void)
{
	/* We cannot sleep in idle until we have resumed */
	disable_hlt();
	return 0;
}

static int omap2_pm_suspend(void)
{
	u32 wken_wkup, mir1;

	wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
	wken_wkup &= ~OMAP24XX_EN_GPT1_MASK;
	prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);

	/* Mask GPT1 */
	mir1 = omap_readl(0x480fe0a4);
	omap_writel(1 << 5, 0x480fe0ac);

	omap_uart_prepare_suspend();
	omap2_enter_full_retention();

	omap_writel(mir1, 0x480fe0a4);
	prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);

	return 0;
}

static int omap2_pm_enter(suspend_state_t state)
{
	int ret = 0;

	switch (state) {
	case PM_SUSPEND_STANDBY:
	case PM_SUSPEND_MEM:
		ret = omap2_pm_suspend();
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

static void omap2_pm_finish(void)
{
	enable_hlt();
}

static struct platform_suspend_ops omap_pm_ops = {
	.prepare	= omap2_pm_prepare,
	.enter		= omap2_pm_enter,
	.finish		= omap2_pm_finish,
	.valid		= suspend_valid_only_mem,
};

/* XXX This function should be shareable between OMAP2xxx and OMAP3 */
static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
{
	clkdm_clear_all_wkdeps(clkdm);
	clkdm_clear_all_sleepdeps(clkdm);

	if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
		omap2_clkdm_allow_idle(clkdm);
	else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
		 atomic_read(&clkdm->usecount) == 0)
		omap2_clkdm_sleep(clkdm);
	return 0;
}

static void __init prcm_setup_regs(void)
{
	int i, num_mem_banks;
	struct powerdomain *pwrdm;

	/* Enable autoidle */
	prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
			  OMAP2_PRCM_SYSCONFIG_OFFSET);

	/*
	 * Set CORE powerdomain memory banks to retain their contents
	 * during RETENTION
	 */
	num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
	for (i = 0; i < num_mem_banks; i++)
		pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);

	/* Set CORE powerdomain's next power state to RETENTION */
	pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);

	/*
	 * Set MPU powerdomain's next power state to RETENTION;
	 * preserve logic state during retention
	 */
	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);

	/* Force-power down DSP, GFX powerdomains */

	pwrdm = clkdm_get_pwrdm(dsp_clkdm);
	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
	omap2_clkdm_sleep(dsp_clkdm);

	pwrdm = clkdm_get_pwrdm(gfx_clkdm);
	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
	omap2_clkdm_sleep(gfx_clkdm);

	/*
	 * Clear clockdomain wakeup dependencies and enable
	 * hardware-supervised idle for all clkdms
	 */
	clkdm_for_each(clkdms_setup, NULL);
	clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);

	/* Enable clock autoidle for all domains */
	cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK |
			 OMAP24XX_AUTO_MAILBOXES_MASK |
			 OMAP24XX_AUTO_WDT4_MASK |
			 OMAP2420_AUTO_WDT3_MASK |
			 OMAP24XX_AUTO_MSPRO_MASK |
			 OMAP2420_AUTO_MMC_MASK |
			 OMAP24XX_AUTO_FAC_MASK |
			 OMAP2420_AUTO_EAC_MASK |
			 OMAP24XX_AUTO_HDQ_MASK |
			 OMAP24XX_AUTO_UART2_MASK |
			 OMAP24XX_AUTO_UART1_MASK |
			 OMAP24XX_AUTO_I2C2_MASK |
			 OMAP24XX_AUTO_I2C1_MASK |
			 OMAP24XX_AUTO_MCSPI2_MASK |
			 OMAP24XX_AUTO_MCSPI1_MASK |
			 OMAP24XX_AUTO_MCBSP2_MASK |
			 OMAP24XX_AUTO_MCBSP1_MASK |
			 OMAP24XX_AUTO_GPT12_MASK |
			 OMAP24XX_AUTO_GPT11_MASK |
			 OMAP24XX_AUTO_GPT10_MASK |
			 OMAP24XX_AUTO_GPT9_MASK |
			 OMAP24XX_AUTO_GPT8_MASK |
			 OMAP24XX_AUTO_GPT7_MASK |
			 OMAP24XX_AUTO_GPT6_MASK |
			 OMAP24XX_AUTO_GPT5_MASK |
			 OMAP24XX_AUTO_GPT4_MASK |
			 OMAP24XX_AUTO_GPT3_MASK |
			 OMAP24XX_AUTO_GPT2_MASK |
			 OMAP2420_AUTO_VLYNQ_MASK |
			 OMAP24XX_AUTO_DSS_MASK,
			 CORE_MOD, CM_AUTOIDLE1);
	cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK |
			 OMAP24XX_AUTO_SSI_MASK |
			 OMAP24XX_AUTO_USB_MASK,
			 CORE_MOD, CM_AUTOIDLE2);
	cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK |
			 OMAP24XX_AUTO_GPMC_MASK |
			 OMAP24XX_AUTO_SDMA_MASK,
			 CORE_MOD, CM_AUTOIDLE3);
	cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK |
			 OMAP24XX_AUTO_AES_MASK |
			 OMAP24XX_AUTO_RNG_MASK |
			 OMAP24XX_AUTO_SHA_MASK |
			 OMAP24XX_AUTO_DES_MASK,
			 CORE_MOD, OMAP24XX_CM_AUTOIDLE4);

	cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD,
			 CM_AUTOIDLE);

	/* Put DPLL and both APLLs into autoidle mode */
	cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
			 (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
			 (0x03 << OMAP24XX_AUTO_54M_SHIFT),
			 PLL_MOD, CM_AUTOIDLE);

	cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK |
			 OMAP24XX_AUTO_WDT1_MASK |
			 OMAP24XX_AUTO_MPU_WDT_MASK |
			 OMAP24XX_AUTO_GPIOS_MASK |
			 OMAP24XX_AUTO_32KSYNC_MASK |
			 OMAP24XX_AUTO_GPT1_MASK,
			 WKUP_MOD, CM_AUTOIDLE);

	/* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
	 * stabilisation */
	prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
			  OMAP2_PRCM_CLKSSETUP_OFFSET);

	/* Configure automatic voltage transition */
	prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
			  OMAP2_PRCM_VOLTSETUP_OFFSET);
	prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
			  (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
			  OMAP24XX_MEMRETCTRL_MASK |
			  (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
			  (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
			  OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);

	/* Enable wake-up events */
	prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
			  WKUP_MOD, PM_WKEN);
}

static int __init omap2_pm_init(void)
{
	u32 l;

	if (!cpu_is_omap24xx())
		return -ENODEV;

	printk(KERN_INFO "Power Management for OMAP2 initializing\n");
	l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
	printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);

	/* Look up important powerdomains */

	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
	if (!mpu_pwrdm)
		pr_err("PM: mpu_pwrdm not found\n");

	core_pwrdm = pwrdm_lookup("core_pwrdm");
	if (!core_pwrdm)
		pr_err("PM: core_pwrdm not found\n");

	/* Look up important clockdomains */

	mpu_clkdm = clkdm_lookup("mpu_clkdm");
	if (!mpu_clkdm)
		pr_err("PM: mpu_clkdm not found\n");

	wkup_clkdm = clkdm_lookup("wkup_clkdm");
	if (!wkup_clkdm)
		pr_err("PM: wkup_clkdm not found\n");

	dsp_clkdm = clkdm_lookup("dsp_clkdm");
	if (!dsp_clkdm)
		pr_err("PM: dsp_clkdm not found\n");

	gfx_clkdm = clkdm_lookup("gfx_clkdm");
	if (!gfx_clkdm)
		pr_err("PM: gfx_clkdm not found\n");


	osc_ck = clk_get(NULL, "osc_ck");
	if (IS_ERR(osc_ck)) {
		printk(KERN_ERR "could not get osc_ck\n");
		return -ENODEV;
	}

	if (cpu_is_omap242x()) {
		emul_ck = clk_get(NULL, "emul_ck");
		if (IS_ERR(emul_ck)) {
			printk(KERN_ERR "could not get emul_ck\n");
			clk_put(osc_ck);
			return -ENODEV;
		}
	}

	prcm_setup_regs();

	/* Hack to prevent MPU retention when STI console is enabled. */
	{
		const struct omap_sti_console_config *sti;

		sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
				      struct omap_sti_console_config);
		if (sti != NULL && sti->enable)
			sti_console_enabled = 1;
	}

	/*
	 * We copy the assembler sleep/wakeup routines to SRAM.
	 * These routines need to be in SRAM as that's the only
	 * memory the MPU can see when it wakes up.
	 */
	if (cpu_is_omap24xx()) {
		omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
						 omap24xx_idle_loop_suspend_sz);

		omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
						    omap24xx_cpu_suspend_sz);
	}

	suspend_set_ops(&omap_pm_ops);
	pm_idle = omap2_pm_idle;

	return 0;
}

late_initcall(omap2_pm_init);
Commit	Line	Data
8bd22949 KH	1	/*
	2	* OMAP2 Power Management Routines
	3	*
	4	* Copyright (C) 2005 Texas Instruments, Inc.
	5	* Copyright (C) 2006-2008 Nokia Corporation
	6	*
	7	* Written by:
	8	* Richard Woodruff <r-woodruff2@ti.com>
	9	* Tony Lindgren
	10	* Juha Yrjola
	11	* Amit Kucheria <amit.kucheria@nokia.com>
	12	* Igor Stoppa <igor.stoppa@nokia.com>
	13	*
	14	* Based on pm.c for omap1
	15	*
	16	* This program is free software; you can redistribute it and/or modify
	17	* it under the terms of the GNU General Public License version 2 as
	18	* published by the Free Software Foundation.
	19	*/
	20
	21	#include <linux/suspend.h>
	22	#include <linux/sched.h>
	23	#include <linux/proc_fs.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/sysfs.h>
	26	#include <linux/module.h>
	27	#include <linux/delay.h>
	28	#include <linux/clk.h>
	29	#include <linux/io.h>
	30	#include <linux/irq.h>
	31	#include <linux/time.h>
	32	#include <linux/gpio.h>
	33
	34	#include <asm/mach/time.h>
	35	#include <asm/mach/irq.h>
	36	#include <asm/mach-types.h>
	37
	38	#include <mach/irqs.h>
ce491cf8 TL	39	#include <plat/clock.h>
	40	#include <plat/sram.h>
	41	#include <plat/control.h>
ce491cf8 TL	42	#include <plat/dma.h>
ce491cf8 TL	43	#include <plat/board.h>
8bd22949 KH	44
	45	#include "prm.h"
	46	#include "prm-regbits-24xx.h"
	47	#include "cm.h"
	48	#include "cm-regbits-24xx.h"
	49	#include "sdrc.h"
	50	#include "pm.h"
	51
ce491cf8 TL	52	#include <plat/powerdomain.h>
ce491cf8 TL	53	#include <plat/clockdomain.h>
8bd22949 KH	54
	55	static void (*omap2_sram_idle)(void);
	56	static void (omap2_sram_suspend)(u32 dllctrl, void __iomem sdrc_dlla_ctrl,
	57	void __iomem *sdrc_power);
	58
369d5614 PW	59	static struct powerdomain mpu_pwrdm, core_pwrdm;
369d5614 PW	60	static struct clockdomain dsp_clkdm, mpu_clkdm, wkup_clkdm, gfx_clkdm;
8bd22949 KH	61
	62	static struct clk osc_ck, emul_ck;
	63
	64	static int omap2_fclks_active(void)
	65	{
	66	u32 f1, f2;
	67
	68	f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	69	f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
4af4016c KH	70
4af4016c KH	71	/* Ignore UART clocks. These are handled by UART core (serial.c) */
2fd0f75c PW	72	f1 &= ~(OMAP24XX_EN_UART1_MASK \| OMAP24XX_EN_UART2_MASK);
2fd0f75c PW	73	f2 &= ~OMAP24XX_EN_UART3_MASK;
4af4016c	74
8bd22949 KH	75	if (f1 \| f2)
	76	return 1;
	77	return 0;
	78	}
	79
8bd22949 KH	80	static void omap2_enter_full_retention(void)
	81	{
	82	u32 l;
	83	struct timespec ts_preidle, ts_postidle, ts_idle;
	84
	85	/* There is 1 reference hold for all children of the oscillator
	86	* clock, the following will remove it. If no one else uses the
	87	* oscillator itself it will be disabled if/when we enter retention
	88	* mode.
	89	*/
	90	clk_disable(osc_ck);
	91
	92	/* Clear old wake-up events */
	93	/* REVISIT: These write to reserved bits? */
	94	prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	95	prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
	96	prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
	97
	98	/*
	99	* Set MPU powerdomain's next power state to RETENTION;
	100	* preserve logic state during retention
	101	*/
	102	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
	103	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
	104
	105	/* Workaround to kill USB */
	106	l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) \| OMAP24XX_USBSTANDBYCTRL;
	107	omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
	108
43ffcd9a	109	omap2_gpio_prepare_for_idle(PWRDM_POWER_RET);
8bd22949 KH	110
	111	if (omap2_pm_debug) {
	112	omap2_pm_dump(0, 0, 0);
	113	getnstimeofday(&ts_preidle);
	114	}
	115
	116	/* One last check for pending IRQs to avoid extra latency due
	117	* to sleeping unnecessarily. */
94434535	118	if (omap_irq_pending())
8bd22949 KH	119	goto no_sleep;
8bd22949 KH	120
4af4016c KH	121	omap_uart_prepare_idle(0);
	122	omap_uart_prepare_idle(1);
	123	omap_uart_prepare_idle(2);
	124
8bd22949 KH	125	/* Jump to SRAM suspend code */
	126	omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
	127	OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
	128	OMAP_SDRC_REGADDR(SDRC_POWER));
8bd22949	129
4af4016c KH	130	omap_uart_resume_idle(2);
	131	omap_uart_resume_idle(1);
	132	omap_uart_resume_idle(0);
	133
	134	no_sleep:
8bd22949 KH	135	if (omap2_pm_debug) {
	136	unsigned long long tmp;
	137
	138	getnstimeofday(&ts_postidle);
	139	ts_idle = timespec_sub(ts_postidle, ts_preidle);
	140	tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
	141	omap2_pm_dump(0, 1, tmp);
	142	}
43ffcd9a	143	omap2_gpio_resume_after_idle();
8bd22949 KH	144
	145	clk_enable(osc_ck);
	146
	147	/* clear CORE wake-up events */
	148	prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	149	prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
	150
	151	/* wakeup domain events - bit 1: GPT1, bit5 GPIO */
	152	prm_clear_mod_reg_bits(0x4 \| 0x1, WKUP_MOD, PM_WKST);
	153
	154	/* MPU domain wake events */
	155	l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	156	if (l & 0x01)
	157	prm_write_mod_reg(0x01, OCP_MOD,
	158	OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	159	if (l & 0x20)
	160	prm_write_mod_reg(0x20, OCP_MOD,
	161	OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	162
	163	/* Mask future PRCM-to-MPU interrupts */
	164	prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	165	}
	166
	167	static int omap2_i2c_active(void)
	168	{
	169	u32 l;
	170
	171	l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
f38ca10a	172	return l & (OMAP2420_EN_I2C2_MASK \| OMAP2420_EN_I2C1_MASK);
8bd22949 KH	173	}
	174
	175	static int sti_console_enabled;
	176
	177	static int omap2_allow_mpu_retention(void)
	178	{
	179	u32 l;
	180
	181	/* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
	182	l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
2fd0f75c PW	183	if (l & (OMAP2420_EN_MMC_MASK \| OMAP24XX_EN_UART2_MASK \|
	184	OMAP24XX_EN_UART1_MASK \| OMAP24XX_EN_MCSPI2_MASK \|
	185	OMAP24XX_EN_MCSPI1_MASK \| OMAP24XX_EN_DSS1_MASK))
8bd22949 KH	186	return 0;
	187	/* Check for UART3. */
	188	l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
2fd0f75c	189	if (l & OMAP24XX_EN_UART3_MASK)
8bd22949 KH	190	return 0;
	191	if (sti_console_enabled)
	192	return 0;
	193
	194	return 1;
	195	}
	196
	197	static void omap2_enter_mpu_retention(void)
	198	{
	199	int only_idle = 0;
	200	struct timespec ts_preidle, ts_postidle, ts_idle;
	201
	202	/* Putting MPU into the WFI state while a transfer is active
	203	* seems to cause the I2C block to timeout. Why? Good question. */
	204	if (omap2_i2c_active())
	205	return;
	206
	207	/* The peripherals seem not to be able to wake up the MPU when
	208	* it is in retention mode. */
	209	if (omap2_allow_mpu_retention()) {
	210	/* REVISIT: These write to reserved bits? */
	211	prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	212	prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
	213	prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
	214
	215	/* Try to enter MPU retention */
	216	prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) \|
2fd0f75c	217	OMAP_LOGICRETSTATE_MASK,
37903009	218	MPU_MOD, OMAP2_PM_PWSTCTRL);
8bd22949 KH	219	} else {
	220	/* Block MPU retention */
	221
2fd0f75c	222	prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
37903009	223	OMAP2_PM_PWSTCTRL);
8bd22949 KH	224	only_idle = 1;
	225	}
	226
	227	if (omap2_pm_debug) {
	228	omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
	229	getnstimeofday(&ts_preidle);
	230	}
	231
	232	omap2_sram_idle();
	233
	234	if (omap2_pm_debug) {
	235	unsigned long long tmp;
	236
	237	getnstimeofday(&ts_postidle);
	238	ts_idle = timespec_sub(ts_postidle, ts_preidle);
	239	tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
	240	omap2_pm_dump(only_idle ? 2 : 1, 1, tmp);
	241	}
	242	}
	243
	244	static int omap2_can_sleep(void)
	245	{
	246	if (omap2_fclks_active())
	247	return 0;
503923ee KH	248	if (!omap_uart_can_sleep())
503923ee KH	249	return 0;
8bd22949 KH	250	if (osc_ck->usecount > 1)
	251	return 0;
	252	if (omap_dma_running())
	253	return 0;
	254
	255	return 1;
	256	}
	257
	258	static void omap2_pm_idle(void)
	259	{
	260	local_irq_disable();
	261	local_fiq_disable();
	262
	263	if (!omap2_can_sleep()) {
94434535	264	if (omap_irq_pending())
8bd22949 KH	265	goto out;
	266	omap2_enter_mpu_retention();
	267	goto out;
	268	}
	269
94434535	270	if (omap_irq_pending())
8bd22949 KH	271	goto out;
	272
	273	omap2_enter_full_retention();
	274
	275	out:
	276	local_fiq_enable();
	277	local_irq_enable();
	278	}
	279
	280	static int omap2_pm_prepare(void)
	281	{
	282	/* We cannot sleep in idle until we have resumed */
	283	disable_hlt();
	284	return 0;
	285	}
	286
	287	static int omap2_pm_suspend(void)
	288	{
	289	u32 wken_wkup, mir1;
	290
	291	wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
2fd0f75c PW	292	wken_wkup &= ~OMAP24XX_EN_GPT1_MASK;
2fd0f75c PW	293	prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
8bd22949 KH	294
	295	/* Mask GPT1 */
	296	mir1 = omap_readl(0x480fe0a4);
	297	omap_writel(1 << 5, 0x480fe0ac);
	298
4af4016c	299	omap_uart_prepare_suspend();
8bd22949 KH	300	omap2_enter_full_retention();
	301
	302	omap_writel(mir1, 0x480fe0a4);
	303	prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
	304
	305	return 0;
	306	}
	307
	308	static int omap2_pm_enter(suspend_state_t state)
	309	{
	310	int ret = 0;
	311
	312	switch (state) {
	313	case PM_SUSPEND_STANDBY:
	314	case PM_SUSPEND_MEM:
	315	ret = omap2_pm_suspend();
	316	break;
	317	default:
	318	ret = -EINVAL;
	319	}
	320
	321	return ret;
	322	}
	323
	324	static void omap2_pm_finish(void)
	325	{
	326	enable_hlt();
	327	}
	328
	329	static struct platform_suspend_ops omap_pm_ops = {
	330	.prepare = omap2_pm_prepare,
	331	.enter = omap2_pm_enter,
	332	.finish = omap2_pm_finish,
	333	.valid = suspend_valid_only_mem,
	334	};
	335
369d5614 PW	336	/* XXX This function should be shareable between OMAP2xxx and OMAP3 */
369d5614 PW	337	static int __init clkdms_setup(struct clockdomain clkdm, void unused)
8bd22949	338	{
369d5614 PW	339	clkdm_clear_all_wkdeps(clkdm);
	340	clkdm_clear_all_sleepdeps(clkdm);
	341
	342	if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
	343	omap2_clkdm_allow_idle(clkdm);
	344	else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
	345	atomic_read(&clkdm->usecount) == 0)
	346	omap2_clkdm_sleep(clkdm);
8bd22949 KH	347	return 0;
	348	}
	349
	350	static void __init prcm_setup_regs(void)
	351	{
	352	int i, num_mem_banks;
	353	struct powerdomain *pwrdm;
	354
	355	/* Enable autoidle */
f38ca10a	356	prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
8bd22949 KH	357	OMAP2_PRCM_SYSCONFIG_OFFSET);
8bd22949 KH	358
8bd22949 KH	359	/*
	360	* Set CORE powerdomain memory banks to retain their contents
	361	* during RETENTION
	362	*/
	363	num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
	364	for (i = 0; i < num_mem_banks; i++)
	365	pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
	366
	367	/* Set CORE powerdomain's next power state to RETENTION */
	368	pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
	369
	370	/*
	371	* Set MPU powerdomain's next power state to RETENTION;
	372	* preserve logic state during retention
	373	*/
	374	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
	375	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
	376
	377	/* Force-power down DSP, GFX powerdomains */
	378
	379	pwrdm = clkdm_get_pwrdm(dsp_clkdm);
	380	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
	381	omap2_clkdm_sleep(dsp_clkdm);
	382
	383	pwrdm = clkdm_get_pwrdm(gfx_clkdm);
	384	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
	385	omap2_clkdm_sleep(gfx_clkdm);
	386
369d5614 PW	387	/*
	388	* Clear clockdomain wakeup dependencies and enable
	389	* hardware-supervised idle for all clkdms
	390	*/
	391	clkdm_for_each(clkdms_setup, NULL);
	392	clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
8bd22949 KH	393
8bd22949 KH	394	/* Enable clock autoidle for all domains */
f38ca10a PW	395	cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK \|
	396	OMAP24XX_AUTO_MAILBOXES_MASK \|
	397	OMAP24XX_AUTO_WDT4_MASK \|
	398	OMAP2420_AUTO_WDT3_MASK \|
	399	OMAP24XX_AUTO_MSPRO_MASK \|
	400	OMAP2420_AUTO_MMC_MASK \|
	401	OMAP24XX_AUTO_FAC_MASK \|
	402	OMAP2420_AUTO_EAC_MASK \|
	403	OMAP24XX_AUTO_HDQ_MASK \|
	404	OMAP24XX_AUTO_UART2_MASK \|
	405	OMAP24XX_AUTO_UART1_MASK \|
	406	OMAP24XX_AUTO_I2C2_MASK \|
	407	OMAP24XX_AUTO_I2C1_MASK \|
	408	OMAP24XX_AUTO_MCSPI2_MASK \|
	409	OMAP24XX_AUTO_MCSPI1_MASK \|
	410	OMAP24XX_AUTO_MCBSP2_MASK \|
	411	OMAP24XX_AUTO_MCBSP1_MASK \|
	412	OMAP24XX_AUTO_GPT12_MASK \|
	413	OMAP24XX_AUTO_GPT11_MASK \|
	414	OMAP24XX_AUTO_GPT10_MASK \|
	415	OMAP24XX_AUTO_GPT9_MASK \|
	416	OMAP24XX_AUTO_GPT8_MASK \|
	417	OMAP24XX_AUTO_GPT7_MASK \|
	418	OMAP24XX_AUTO_GPT6_MASK \|
	419	OMAP24XX_AUTO_GPT5_MASK \|
	420	OMAP24XX_AUTO_GPT4_MASK \|
	421	OMAP24XX_AUTO_GPT3_MASK \|
	422	OMAP24XX_AUTO_GPT2_MASK \|
	423	OMAP2420_AUTO_VLYNQ_MASK \|
	424	OMAP24XX_AUTO_DSS_MASK,
8bd22949	425	CORE_MOD, CM_AUTOIDLE1);
f38ca10a PW	426	cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK \|
	427	OMAP24XX_AUTO_SSI_MASK \|
	428	OMAP24XX_AUTO_USB_MASK,
8bd22949	429	CORE_MOD, CM_AUTOIDLE2);
f38ca10a PW	430	cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK \|
	431	OMAP24XX_AUTO_GPMC_MASK \|
	432	OMAP24XX_AUTO_SDMA_MASK,
8bd22949	433	CORE_MOD, CM_AUTOIDLE3);
f38ca10a PW	434	cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK \|
	435	OMAP24XX_AUTO_AES_MASK \|
	436	OMAP24XX_AUTO_RNG_MASK \|
	437	OMAP24XX_AUTO_SHA_MASK \|
	438	OMAP24XX_AUTO_DES_MASK,
8bd22949 KH	439	CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
8bd22949 KH	440
f38ca10a PW	441	cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD,
f38ca10a PW	442	CM_AUTOIDLE);
8bd22949 KH	443
	444	/* Put DPLL and both APLLs into autoidle mode */
	445	cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) \|
	446	(0x03 << OMAP24XX_AUTO_96M_SHIFT) \|
	447	(0x03 << OMAP24XX_AUTO_54M_SHIFT),
	448	PLL_MOD, CM_AUTOIDLE);
	449
f38ca10a PW	450	cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK \|
	451	OMAP24XX_AUTO_WDT1_MASK \|
	452	OMAP24XX_AUTO_MPU_WDT_MASK \|
	453	OMAP24XX_AUTO_GPIOS_MASK \|
	454	OMAP24XX_AUTO_32KSYNC_MASK \|
	455	OMAP24XX_AUTO_GPT1_MASK,
8bd22949 KH	456	WKUP_MOD, CM_AUTOIDLE);
	457
	458	/* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
	459	* stabilisation */
	460	prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
	461	OMAP2_PRCM_CLKSSETUP_OFFSET);
	462
	463	/* Configure automatic voltage transition */
	464	prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
	465	OMAP2_PRCM_VOLTSETUP_OFFSET);
f38ca10a	466	prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK \|
8bd22949	467	(0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) \|
f38ca10a	468	OMAP24XX_MEMRETCTRL_MASK \|
8bd22949 KH	469	(0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) \|
	470	(0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
	471	OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
	472
	473	/* Enable wake-up events */
2fd0f75c	474	prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK \| OMAP24XX_EN_GPT1_MASK,
8bd22949 KH	475	WKUP_MOD, PM_WKEN);
	476	}
	477
7cc515f7	478	static int __init omap2_pm_init(void)
8bd22949 KH	479	{
	480	u32 l;
	481
	482	if (!cpu_is_omap24xx())
	483	return -ENODEV;
	484
	485	printk(KERN_INFO "Power Management for OMAP2 initializing\n");
	486	l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
	487	printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
	488
369d5614	489	/* Look up important powerdomains */
8bd22949 KH	490
	491	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
	492	if (!mpu_pwrdm)
	493	pr_err("PM: mpu_pwrdm not found\n");
	494
	495	core_pwrdm = pwrdm_lookup("core_pwrdm");
	496	if (!core_pwrdm)
	497	pr_err("PM: core_pwrdm not found\n");
	498
369d5614 PW	499	/* Look up important clockdomains */
	500
	501	mpu_clkdm = clkdm_lookup("mpu_clkdm");
	502	if (!mpu_clkdm)
	503	pr_err("PM: mpu_clkdm not found\n");
	504
	505	wkup_clkdm = clkdm_lookup("wkup_clkdm");
	506	if (!wkup_clkdm)
	507	pr_err("PM: wkup_clkdm not found\n");
	508
8bd22949 KH	509	dsp_clkdm = clkdm_lookup("dsp_clkdm");
8bd22949 KH	510	if (!dsp_clkdm)
369d5614	511	pr_err("PM: dsp_clkdm not found\n");
8bd22949 KH	512
	513	gfx_clkdm = clkdm_lookup("gfx_clkdm");
	514	if (!gfx_clkdm)
	515	pr_err("PM: gfx_clkdm not found\n");
	516
	517
	518	osc_ck = clk_get(NULL, "osc_ck");
	519	if (IS_ERR(osc_ck)) {
	520	printk(KERN_ERR "could not get osc_ck\n");
	521	return -ENODEV;
	522	}
	523
	524	if (cpu_is_omap242x()) {
	525	emul_ck = clk_get(NULL, "emul_ck");
	526	if (IS_ERR(emul_ck)) {
	527	printk(KERN_ERR "could not get emul_ck\n");
	528	clk_put(osc_ck);
	529	return -ENODEV;
	530	}
	531	}
	532
	533	prcm_setup_regs();
	534
	535	/* Hack to prevent MPU retention when STI console is enabled. */
	536	{
	537	const struct omap_sti_console_config *sti;
	538
	539	sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
	540	struct omap_sti_console_config);
	541	if (sti != NULL && sti->enable)
	542	sti_console_enabled = 1;
	543	}
	544
	545	/*
	546	* We copy the assembler sleep/wakeup routines to SRAM.
	547	* These routines need to be in SRAM as that's the only
	548	* memory the MPU can see when it wakes up.
	549	*/
	550	if (cpu_is_omap24xx()) {
	551	omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
	552	omap24xx_idle_loop_suspend_sz);
	553
	554	omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
	555	omap24xx_cpu_suspend_sz);
	556	}
	557
	558	suspend_set_ops(&omap_pm_ops);
	559	pm_idle = omap2_pm_idle;
	560
	561	return 0;
	562	}
	563
	564	late_initcall(omap2_pm_init);