[deliverable/linux.git] / arch / arm / mach-omap2 / pm24xx.c

/*
 * OMAP2 Power Management Routines
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 * Copyright (C) 2006-2008 Nokia Corporation
 *
 * Written by:
 * Richard Woodruff <r-woodruff2@ti.com>
 * Tony Lindgren
 * Juha Yrjola
 * Amit Kucheria <amit.kucheria@nokia.com>
 * Igor Stoppa <igor.stoppa@nokia.com>
 *
 * Based on pm.c for omap1
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/suspend.h>
#include <linux/sched.h>
#include <linux/proc_fs.h>
#include <linux/interrupt.h>
#include <linux/sysfs.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/time.h>
#include <linux/gpio.h>

#include <asm/mach/time.h>
#include <asm/mach/irq.h>
#include <asm/mach-types.h>

#include <mach/irqs.h>
#include <plat/clock.h>
#include <plat/sram.h>
#include <plat/control.h>
#include <plat/mux.h>
#include <plat/dma.h>
#include <plat/board.h>

#include "prm.h"
#include "prm-regbits-24xx.h"
#include "cm.h"
#include "cm-regbits-24xx.h"
#include "sdrc.h"
#include "pm.h"

#include <plat/powerdomain.h>
#include <plat/clockdomain.h>

static void (*omap2_sram_idle)(void);
static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
				  void __iomem *sdrc_power);

static struct powerdomain *mpu_pwrdm;
static struct powerdomain *core_pwrdm;

static struct clockdomain *dsp_clkdm;
static struct clockdomain *gfx_clkdm;

static struct clk *osc_ck, *emul_ck;

static int omap2_fclks_active(void)
{
	u32 f1, f2;

	f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);

	/* Ignore UART clocks.  These are handled by UART core (serial.c) */
	f1 &= ~(OMAP24XX_EN_UART1 | OMAP24XX_EN_UART2);
	f2 &= ~OMAP24XX_EN_UART3;

	if (f1 | f2)
		return 1;
	return 0;
}

static void omap2_enter_full_retention(void)
{
	u32 l;
	struct timespec ts_preidle, ts_postidle, ts_idle;

	/* There is 1 reference hold for all children of the oscillator
	 * clock, the following will remove it. If no one else uses the
	 * oscillator itself it will be disabled if/when we enter retention
	 * mode.
	 */
	clk_disable(osc_ck);

	/* Clear old wake-up events */
	/* REVISIT: These write to reserved bits? */
	prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
	prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);

	/*
	 * Set MPU powerdomain's next power state to RETENTION;
	 * preserve logic state during retention
	 */
	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);

	/* Workaround to kill USB */
	l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
	omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);

	omap2_gpio_prepare_for_retention();

	if (omap2_pm_debug) {
		omap2_pm_dump(0, 0, 0);
		getnstimeofday(&ts_preidle);
	}

	/* One last check for pending IRQs to avoid extra latency due
	 * to sleeping unnecessarily. */
	if (omap_irq_pending())
		goto no_sleep;

	omap_uart_prepare_idle(0);
	omap_uart_prepare_idle(1);
	omap_uart_prepare_idle(2);

	/* Jump to SRAM suspend code */
	omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
			   OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
			   OMAP_SDRC_REGADDR(SDRC_POWER));

	omap_uart_resume_idle(2);
	omap_uart_resume_idle(1);
	omap_uart_resume_idle(0);

no_sleep:
	if (omap2_pm_debug) {
		unsigned long long tmp;

		getnstimeofday(&ts_postidle);
		ts_idle = timespec_sub(ts_postidle, ts_preidle);
		tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
		omap2_pm_dump(0, 1, tmp);
	}
	omap2_gpio_resume_after_retention();

	clk_enable(osc_ck);

	/* clear CORE wake-up events */
	prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);

	/* wakeup domain events - bit 1: GPT1, bit5 GPIO */
	prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);

	/* MPU domain wake events */
	l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	if (l & 0x01)
		prm_write_mod_reg(0x01, OCP_MOD,
				  OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	if (l & 0x20)
		prm_write_mod_reg(0x20, OCP_MOD,
				  OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);

	/* Mask future PRCM-to-MPU interrupts */
	prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
}

static int omap2_i2c_active(void)
{
	u32 l;

	l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	return l & (OMAP2420_EN_I2C2 | OMAP2420_EN_I2C1);
}

static int sti_console_enabled;

static int omap2_allow_mpu_retention(void)
{
	u32 l;

	/* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
	l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	if (l & (OMAP2420_EN_MMC | OMAP24XX_EN_UART2 |
		 OMAP24XX_EN_UART1 | OMAP24XX_EN_MCSPI2 |
		 OMAP24XX_EN_MCSPI1 | OMAP24XX_EN_DSS1))
		return 0;
	/* Check for UART3. */
	l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
	if (l & OMAP24XX_EN_UART3)
		return 0;
	if (sti_console_enabled)
		return 0;

	return 1;
}

static void omap2_enter_mpu_retention(void)
{
	int only_idle = 0;
	struct timespec ts_preidle, ts_postidle, ts_idle;

	/* Putting MPU into the WFI state while a transfer is active
	 * seems to cause the I2C block to timeout. Why? Good question. */
	if (omap2_i2c_active())
		return;

	/* The peripherals seem not to be able to wake up the MPU when
	 * it is in retention mode. */
	if (omap2_allow_mpu_retention()) {
		/* REVISIT: These write to reserved bits? */
		prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
		prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
		prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);

		/* Try to enter MPU retention */
		prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
				  OMAP_LOGICRETSTATE,
				  MPU_MOD, OMAP2_PM_PWSTCTRL);
	} else {
		/* Block MPU retention */

		prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD,
						 OMAP2_PM_PWSTCTRL);
		only_idle = 1;
	}

	if (omap2_pm_debug) {
		omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
		getnstimeofday(&ts_preidle);
	}

	omap2_sram_idle();

	if (omap2_pm_debug) {
		unsigned long long tmp;

		getnstimeofday(&ts_postidle);
		ts_idle = timespec_sub(ts_postidle, ts_preidle);
		tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
		omap2_pm_dump(only_idle ? 2 : 1, 1, tmp);
	}
}

static int omap2_can_sleep(void)
{
	if (omap2_fclks_active())
		return 0;
	if (osc_ck->usecount > 1)
		return 0;
	if (omap_dma_running())
		return 0;

	return 1;
}

static void omap2_pm_idle(void)
{
	local_irq_disable();
	local_fiq_disable();

	if (!omap2_can_sleep()) {
		if (omap_irq_pending())
			goto out;
		omap2_enter_mpu_retention();
		goto out;
	}

	if (omap_irq_pending())
		goto out;

	omap2_enter_full_retention();

out:
	local_fiq_enable();
	local_irq_enable();
}

static int omap2_pm_prepare(void)
{
	/* We cannot sleep in idle until we have resumed */
	disable_hlt();
	return 0;
}

static int omap2_pm_suspend(void)
{
	u32 wken_wkup, mir1;

	wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
	prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);

	/* Mask GPT1 */
	mir1 = omap_readl(0x480fe0a4);
	omap_writel(1 << 5, 0x480fe0ac);

	omap_uart_prepare_suspend();
	omap2_enter_full_retention();

	omap_writel(mir1, 0x480fe0a4);
	prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);

	return 0;
}

static int omap2_pm_enter(suspend_state_t state)
{
	int ret = 0;

	switch (state) {
	case PM_SUSPEND_STANDBY:
	case PM_SUSPEND_MEM:
		ret = omap2_pm_suspend();
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

static void omap2_pm_finish(void)
{
	enable_hlt();
}

static struct platform_suspend_ops omap_pm_ops = {
	.prepare	= omap2_pm_prepare,
	.enter		= omap2_pm_enter,
	.finish		= omap2_pm_finish,
	.valid		= suspend_valid_only_mem,
};

static int _pm_clkdm_enable_hwsup(struct clockdomain *clkdm, void *unused)
{
	omap2_clkdm_allow_idle(clkdm);
	return 0;
}

static void __init prcm_setup_regs(void)
{
	int i, num_mem_banks;
	struct powerdomain *pwrdm;

	/* Enable autoidle */
	prm_write_mod_reg(OMAP24XX_AUTOIDLE, OCP_MOD,
			  OMAP2_PRCM_SYSCONFIG_OFFSET);

	/* Set all domain wakeup dependencies */
	prm_write_mod_reg(OMAP_EN_WKUP_MASK, MPU_MOD, PM_WKDEP);
	prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
	prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
	prm_write_mod_reg(0, CORE_MOD, PM_WKDEP);
	if (cpu_is_omap2430())
		prm_write_mod_reg(0, OMAP2430_MDM_MOD, PM_WKDEP);

	/*
	 * Set CORE powerdomain memory banks to retain their contents
	 * during RETENTION
	 */
	num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
	for (i = 0; i < num_mem_banks; i++)
		pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);

	/* Set CORE powerdomain's next power state to RETENTION */
	pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);

	/*
	 * Set MPU powerdomain's next power state to RETENTION;
	 * preserve logic state during retention
	 */
	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);

	/* Force-power down DSP, GFX powerdomains */

	pwrdm = clkdm_get_pwrdm(dsp_clkdm);
	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
	omap2_clkdm_sleep(dsp_clkdm);

	pwrdm = clkdm_get_pwrdm(gfx_clkdm);
	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
	omap2_clkdm_sleep(gfx_clkdm);

	/* Enable clockdomain hardware-supervised control for all clkdms */
	clkdm_for_each(_pm_clkdm_enable_hwsup, NULL);

	/* Enable clock autoidle for all domains */
	cm_write_mod_reg(OMAP24XX_AUTO_CAM |
			 OMAP24XX_AUTO_MAILBOXES |
			 OMAP24XX_AUTO_WDT4 |
			 OMAP2420_AUTO_WDT3 |
			 OMAP24XX_AUTO_MSPRO |
			 OMAP2420_AUTO_MMC |
			 OMAP24XX_AUTO_FAC |
			 OMAP2420_AUTO_EAC |
			 OMAP24XX_AUTO_HDQ |
			 OMAP24XX_AUTO_UART2 |
			 OMAP24XX_AUTO_UART1 |
			 OMAP24XX_AUTO_I2C2 |
			 OMAP24XX_AUTO_I2C1 |
			 OMAP24XX_AUTO_MCSPI2 |
			 OMAP24XX_AUTO_MCSPI1 |
			 OMAP24XX_AUTO_MCBSP2 |
			 OMAP24XX_AUTO_MCBSP1 |
			 OMAP24XX_AUTO_GPT12 |
			 OMAP24XX_AUTO_GPT11 |
			 OMAP24XX_AUTO_GPT10 |
			 OMAP24XX_AUTO_GPT9 |
			 OMAP24XX_AUTO_GPT8 |
			 OMAP24XX_AUTO_GPT7 |
			 OMAP24XX_AUTO_GPT6 |
			 OMAP24XX_AUTO_GPT5 |
			 OMAP24XX_AUTO_GPT4 |
			 OMAP24XX_AUTO_GPT3 |
			 OMAP24XX_AUTO_GPT2 |
			 OMAP2420_AUTO_VLYNQ |
			 OMAP24XX_AUTO_DSS,
			 CORE_MOD, CM_AUTOIDLE1);
	cm_write_mod_reg(OMAP24XX_AUTO_UART3 |
			 OMAP24XX_AUTO_SSI |
			 OMAP24XX_AUTO_USB,
			 CORE_MOD, CM_AUTOIDLE2);
	cm_write_mod_reg(OMAP24XX_AUTO_SDRC |
			 OMAP24XX_AUTO_GPMC |
			 OMAP24XX_AUTO_SDMA,
			 CORE_MOD, CM_AUTOIDLE3);
	cm_write_mod_reg(OMAP24XX_AUTO_PKA |
			 OMAP24XX_AUTO_AES |
			 OMAP24XX_AUTO_RNG |
			 OMAP24XX_AUTO_SHA |
			 OMAP24XX_AUTO_DES,
			 CORE_MOD, OMAP24XX_CM_AUTOIDLE4);

	cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);

	/* Put DPLL and both APLLs into autoidle mode */
	cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
			 (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
			 (0x03 << OMAP24XX_AUTO_54M_SHIFT),
			 PLL_MOD, CM_AUTOIDLE);

	cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL |
			 OMAP24XX_AUTO_WDT1 |
			 OMAP24XX_AUTO_MPU_WDT |
			 OMAP24XX_AUTO_GPIOS |
			 OMAP24XX_AUTO_32KSYNC |
			 OMAP24XX_AUTO_GPT1,
			 WKUP_MOD, CM_AUTOIDLE);

	/* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
	 * stabilisation */
	prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
			  OMAP2_PRCM_CLKSSETUP_OFFSET);

	/* Configure automatic voltage transition */
	prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
			  OMAP2_PRCM_VOLTSETUP_OFFSET);
	prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT |
			  (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
			  OMAP24XX_MEMRETCTRL |
			  (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
			  (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
			  OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);

	/* Enable wake-up events */
	prm_write_mod_reg(OMAP24XX_EN_GPIOS | OMAP24XX_EN_GPT1,
			  WKUP_MOD, PM_WKEN);
}

static int __init omap2_pm_init(void)
{
	u32 l;

	if (!cpu_is_omap24xx())
		return -ENODEV;

	printk(KERN_INFO "Power Management for OMAP2 initializing\n");
	l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
	printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);

	/* Look up important powerdomains, clockdomains */

	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
	if (!mpu_pwrdm)
		pr_err("PM: mpu_pwrdm not found\n");

	core_pwrdm = pwrdm_lookup("core_pwrdm");
	if (!core_pwrdm)
		pr_err("PM: core_pwrdm not found\n");

	dsp_clkdm = clkdm_lookup("dsp_clkdm");
	if (!dsp_clkdm)
		pr_err("PM: mpu_clkdm not found\n");

	gfx_clkdm = clkdm_lookup("gfx_clkdm");
	if (!gfx_clkdm)
		pr_err("PM: gfx_clkdm not found\n");


	osc_ck = clk_get(NULL, "osc_ck");
	if (IS_ERR(osc_ck)) {
		printk(KERN_ERR "could not get osc_ck\n");
		return -ENODEV;
	}

	if (cpu_is_omap242x()) {
		emul_ck = clk_get(NULL, "emul_ck");
		if (IS_ERR(emul_ck)) {
			printk(KERN_ERR "could not get emul_ck\n");
			clk_put(osc_ck);
			return -ENODEV;
		}
	}

	prcm_setup_regs();

	/* Hack to prevent MPU retention when STI console is enabled. */
	{
		const struct omap_sti_console_config *sti;

		sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
				      struct omap_sti_console_config);
		if (sti != NULL && sti->enable)
			sti_console_enabled = 1;
	}

	/*
	 * We copy the assembler sleep/wakeup routines to SRAM.
	 * These routines need to be in SRAM as that's the only
	 * memory the MPU can see when it wakes up.
	 */
	if (cpu_is_omap24xx()) {
		omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
						 omap24xx_idle_loop_suspend_sz);

		omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
						    omap24xx_cpu_suspend_sz);
	}

	suspend_set_ops(&omap_pm_ops);
	pm_idle = omap2_pm_idle;

	return 0;
}

late_initcall(omap2_pm_init);
Commit	Line	Data
8bd22949 KH	1	/*
	2	* OMAP2 Power Management Routines
	3	*
	4	* Copyright (C) 2005 Texas Instruments, Inc.
	5	* Copyright (C) 2006-2008 Nokia Corporation
	6	*
	7	* Written by:
	8	* Richard Woodruff <r-woodruff2@ti.com>
	9	* Tony Lindgren
	10	* Juha Yrjola
	11	* Amit Kucheria <amit.kucheria@nokia.com>
	12	* Igor Stoppa <igor.stoppa@nokia.com>
	13	*
	14	* Based on pm.c for omap1
	15	*
	16	* This program is free software; you can redistribute it and/or modify
	17	* it under the terms of the GNU General Public License version 2 as
	18	* published by the Free Software Foundation.
	19	*/
	20
	21	#include <linux/suspend.h>
	22	#include <linux/sched.h>
	23	#include <linux/proc_fs.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/sysfs.h>
	26	#include <linux/module.h>
	27	#include <linux/delay.h>
	28	#include <linux/clk.h>
	29	#include <linux/io.h>
	30	#include <linux/irq.h>
	31	#include <linux/time.h>
	32	#include <linux/gpio.h>
	33
	34	#include <asm/mach/time.h>
	35	#include <asm/mach/irq.h>
	36	#include <asm/mach-types.h>
	37
	38	#include <mach/irqs.h>
ce491cf8 TL	39	#include <plat/clock.h>
	40	#include <plat/sram.h>
	41	#include <plat/control.h>
	42	#include <plat/mux.h>
	43	#include <plat/dma.h>
	44	#include <plat/board.h>
8bd22949 KH	45
	46	#include "prm.h"
	47	#include "prm-regbits-24xx.h"
	48	#include "cm.h"
	49	#include "cm-regbits-24xx.h"
	50	#include "sdrc.h"
	51	#include "pm.h"
	52
ce491cf8 TL	53	#include <plat/powerdomain.h>
ce491cf8 TL	54	#include <plat/clockdomain.h>
8bd22949 KH	55
	56	static void (*omap2_sram_idle)(void);
	57	static void (omap2_sram_suspend)(u32 dllctrl, void __iomem sdrc_dlla_ctrl,
	58	void __iomem *sdrc_power);
	59
	60	static struct powerdomain *mpu_pwrdm;
	61	static struct powerdomain *core_pwrdm;
	62
	63	static struct clockdomain *dsp_clkdm;
	64	static struct clockdomain *gfx_clkdm;
	65
	66	static struct clk osc_ck, emul_ck;
	67
	68	static int omap2_fclks_active(void)
	69	{
	70	u32 f1, f2;
	71
	72	f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	73	f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
4af4016c KH	74
	75	/* Ignore UART clocks. These are handled by UART core (serial.c) */
	76	f1 &= ~(OMAP24XX_EN_UART1 \| OMAP24XX_EN_UART2);
	77	f2 &= ~OMAP24XX_EN_UART3;
	78
8bd22949 KH	79	if (f1 \| f2)
	80	return 1;
	81	return 0;
	82	}
	83
8bd22949 KH	84	static void omap2_enter_full_retention(void)
	85	{
	86	u32 l;
	87	struct timespec ts_preidle, ts_postidle, ts_idle;
	88
	89	/* There is 1 reference hold for all children of the oscillator
	90	* clock, the following will remove it. If no one else uses the
	91	* oscillator itself it will be disabled if/when we enter retention
	92	* mode.
	93	*/
	94	clk_disable(osc_ck);
	95
	96	/* Clear old wake-up events */
	97	/* REVISIT: These write to reserved bits? */
	98	prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	99	prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
	100	prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
	101
	102	/*
	103	* Set MPU powerdomain's next power state to RETENTION;
	104	* preserve logic state during retention
	105	*/
	106	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
	107	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
	108
	109	/* Workaround to kill USB */
	110	l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) \| OMAP24XX_USBSTANDBYCTRL;
	111	omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
	112
	113	omap2_gpio_prepare_for_retention();
	114
	115	if (omap2_pm_debug) {
	116	omap2_pm_dump(0, 0, 0);
	117	getnstimeofday(&ts_preidle);
	118	}
	119
	120	/* One last check for pending IRQs to avoid extra latency due
	121	* to sleeping unnecessarily. */
94434535	122	if (omap_irq_pending())
8bd22949 KH	123	goto no_sleep;
8bd22949 KH	124
4af4016c KH	125	omap_uart_prepare_idle(0);
	126	omap_uart_prepare_idle(1);
	127	omap_uart_prepare_idle(2);
	128
8bd22949 KH	129	/* Jump to SRAM suspend code */
	130	omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
	131	OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
	132	OMAP_SDRC_REGADDR(SDRC_POWER));
8bd22949	133
4af4016c KH	134	omap_uart_resume_idle(2);
	135	omap_uart_resume_idle(1);
	136	omap_uart_resume_idle(0);
	137
	138	no_sleep:
8bd22949 KH	139	if (omap2_pm_debug) {
	140	unsigned long long tmp;
	141
	142	getnstimeofday(&ts_postidle);
	143	ts_idle = timespec_sub(ts_postidle, ts_preidle);
	144	tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
	145	omap2_pm_dump(0, 1, tmp);
	146	}
	147	omap2_gpio_resume_after_retention();
	148
	149	clk_enable(osc_ck);
	150
	151	/* clear CORE wake-up events */
	152	prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	153	prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
	154
	155	/* wakeup domain events - bit 1: GPT1, bit5 GPIO */
	156	prm_clear_mod_reg_bits(0x4 \| 0x1, WKUP_MOD, PM_WKST);
	157
	158	/* MPU domain wake events */
	159	l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	160	if (l & 0x01)
	161	prm_write_mod_reg(0x01, OCP_MOD,
	162	OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	163	if (l & 0x20)
	164	prm_write_mod_reg(0x20, OCP_MOD,
	165	OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	166
	167	/* Mask future PRCM-to-MPU interrupts */
	168	prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	169	}
	170
	171	static int omap2_i2c_active(void)
	172	{
	173	u32 l;
	174
	175	l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	176	return l & (OMAP2420_EN_I2C2 \| OMAP2420_EN_I2C1);
	177	}
	178
	179	static int sti_console_enabled;
	180
	181	static int omap2_allow_mpu_retention(void)
	182	{
	183	u32 l;
	184
	185	/* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
	186	l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	187	if (l & (OMAP2420_EN_MMC \| OMAP24XX_EN_UART2 \|
	188	OMAP24XX_EN_UART1 \| OMAP24XX_EN_MCSPI2 \|
	189	OMAP24XX_EN_MCSPI1 \| OMAP24XX_EN_DSS1))
	190	return 0;
	191	/* Check for UART3. */
	192	l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
	193	if (l & OMAP24XX_EN_UART3)
	194	return 0;
	195	if (sti_console_enabled)
	196	return 0;
	197
	198	return 1;
	199	}
	200
	201	static void omap2_enter_mpu_retention(void)
	202	{
203	int only_idle = 0;
204	struct timespec ts_preidle, ts_postidle, ts_idle;
205
206	/* Putting MPU into the WFI state while a transfer is active
207	* seems to cause the I2C block to timeout. Why? Good question. */
208	if (omap2_i2c_active())
209	return;
210
211	/* The peripherals seem not to be able to wake up the MPU when
212	* it is in retention mode. */
213	if (omap2_allow_mpu_retention()) {
214	/* REVISIT: These write to reserved bits? */
215	prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
216	prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
217	prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
218
219	/* Try to enter MPU retention */
220	prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) \|
221	OMAP_LOGICRETSTATE,
37903009	222	MPU_MOD, OMAP2_PM_PWSTCTRL);
8bd22949 KH	223	} else {
	224	/* Block MPU retention */
	225
37903009 AP	226	prm_write_mod_reg(OMAP_LOGICRETSTATE, MPU_MOD,
37903009 AP	227	OMAP2_PM_PWSTCTRL);
8bd22949 KH	228	only_idle = 1;
	229	}
	230
	231	if (omap2_pm_debug) {
	232	omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
	233	getnstimeofday(&ts_preidle);
	234	}
	235
	236	omap2_sram_idle();
	237
	238	if (omap2_pm_debug) {
	239	unsigned long long tmp;
	240
	241	getnstimeofday(&ts_postidle);
	242	ts_idle = timespec_sub(ts_postidle, ts_preidle);
	243	tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
	244	omap2_pm_dump(only_idle ? 2 : 1, 1, tmp);
	245	}
	246	}
	247
	248	static int omap2_can_sleep(void)
	249	{
	250	if (omap2_fclks_active())
	251	return 0;
	252	if (osc_ck->usecount > 1)
	253	return 0;
	254	if (omap_dma_running())
	255	return 0;
	256
	257	return 1;
	258	}
	259
	260	static void omap2_pm_idle(void)
	261	{
	262	local_irq_disable();
	263	local_fiq_disable();
	264
	265	if (!omap2_can_sleep()) {
94434535	266	if (omap_irq_pending())
8bd22949 KH	267	goto out;
	268	omap2_enter_mpu_retention();
	269	goto out;
	270	}
	271
94434535	272	if (omap_irq_pending())
8bd22949 KH	273	goto out;
	274
	275	omap2_enter_full_retention();
	276
	277	out:
	278	local_fiq_enable();
	279	local_irq_enable();
	280	}
	281
	282	static int omap2_pm_prepare(void)
	283	{
	284	/* We cannot sleep in idle until we have resumed */
	285	disable_hlt();
	286	return 0;
	287	}
	288
	289	static int omap2_pm_suspend(void)
	290	{
	291	u32 wken_wkup, mir1;
	292
	293	wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
	294	prm_write_mod_reg(wken_wkup & ~OMAP24XX_EN_GPT1, WKUP_MOD, PM_WKEN);
	295
	296	/* Mask GPT1 */
	297	mir1 = omap_readl(0x480fe0a4);
	298	omap_writel(1 << 5, 0x480fe0ac);
	299
4af4016c	300	omap_uart_prepare_suspend();
8bd22949 KH	301	omap2_enter_full_retention();
	302
	303	omap_writel(mir1, 0x480fe0a4);
	304	prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN);
	305
	306	return 0;
	307	}
	308
	309	static int omap2_pm_enter(suspend_state_t state)
	310	{
	311	int ret = 0;
	312
	313	switch (state) {
	314	case PM_SUSPEND_STANDBY:
	315	case PM_SUSPEND_MEM:
	316	ret = omap2_pm_suspend();
	317	break;
	318	default:
	319	ret = -EINVAL;
	320	}
	321
	322	return ret;
	323	}
	324
	325	static void omap2_pm_finish(void)
	326	{
	327	enable_hlt();
	328	}
	329
	330	static struct platform_suspend_ops omap_pm_ops = {
	331	.prepare = omap2_pm_prepare,
	332	.enter = omap2_pm_enter,
	333	.finish = omap2_pm_finish,
	334	.valid = suspend_valid_only_mem,
	335	};
	336
a23456e9	337	static int _pm_clkdm_enable_hwsup(struct clockdomain clkdm, void unused)
8bd22949 KH	338	{
	339	omap2_clkdm_allow_idle(clkdm);
	340	return 0;
	341	}
	342
	343	static void __init prcm_setup_regs(void)
	344	{
	345	int i, num_mem_banks;
	346	struct powerdomain *pwrdm;
	347
	348	/* Enable autoidle */
	349	prm_write_mod_reg(OMAP24XX_AUTOIDLE, OCP_MOD,
	350	OMAP2_PRCM_SYSCONFIG_OFFSET);
	351
	352	/* Set all domain wakeup dependencies */
	353	prm_write_mod_reg(OMAP_EN_WKUP_MASK, MPU_MOD, PM_WKDEP);
	354	prm_write_mod_reg(0, OMAP24XX_DSP_MOD, PM_WKDEP);
	355	prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
	356	prm_write_mod_reg(0, CORE_MOD, PM_WKDEP);
	357	if (cpu_is_omap2430())
	358	prm_write_mod_reg(0, OMAP2430_MDM_MOD, PM_WKDEP);
	359
	360	/*
	361	* Set CORE powerdomain memory banks to retain their contents
	362	* during RETENTION
	363	*/
	364	num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
	365	for (i = 0; i < num_mem_banks; i++)
	366	pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
	367
	368	/* Set CORE powerdomain's next power state to RETENTION */
	369	pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
	370
	371	/*
	372	* Set MPU powerdomain's next power state to RETENTION;
	373	* preserve logic state during retention
	374	*/
	375	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
	376	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
	377
	378	/* Force-power down DSP, GFX powerdomains */
	379
	380	pwrdm = clkdm_get_pwrdm(dsp_clkdm);
	381	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
	382	omap2_clkdm_sleep(dsp_clkdm);
	383
	384	pwrdm = clkdm_get_pwrdm(gfx_clkdm);
	385	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
	386	omap2_clkdm_sleep(gfx_clkdm);
	387
	388	/* Enable clockdomain hardware-supervised control for all clkdms */
a23456e9	389	clkdm_for_each(_pm_clkdm_enable_hwsup, NULL);
8bd22949 KH	390
	391	/* Enable clock autoidle for all domains */
	392	cm_write_mod_reg(OMAP24XX_AUTO_CAM \|
	393	OMAP24XX_AUTO_MAILBOXES \|
	394	OMAP24XX_AUTO_WDT4 \|
	395	OMAP2420_AUTO_WDT3 \|
	396	OMAP24XX_AUTO_MSPRO \|
	397	OMAP2420_AUTO_MMC \|
	398	OMAP24XX_AUTO_FAC \|
	399	OMAP2420_AUTO_EAC \|
	400	OMAP24XX_AUTO_HDQ \|
	401	OMAP24XX_AUTO_UART2 \|
	402	OMAP24XX_AUTO_UART1 \|
	403	OMAP24XX_AUTO_I2C2 \|
	404	OMAP24XX_AUTO_I2C1 \|
	405	OMAP24XX_AUTO_MCSPI2 \|
	406	OMAP24XX_AUTO_MCSPI1 \|
	407	OMAP24XX_AUTO_MCBSP2 \|
	408	OMAP24XX_AUTO_MCBSP1 \|
	409	OMAP24XX_AUTO_GPT12 \|
	410	OMAP24XX_AUTO_GPT11 \|
	411	OMAP24XX_AUTO_GPT10 \|
	412	OMAP24XX_AUTO_GPT9 \|
	413	OMAP24XX_AUTO_GPT8 \|
	414	OMAP24XX_AUTO_GPT7 \|
	415	OMAP24XX_AUTO_GPT6 \|
	416	OMAP24XX_AUTO_GPT5 \|
	417	OMAP24XX_AUTO_GPT4 \|
	418	OMAP24XX_AUTO_GPT3 \|
	419	OMAP24XX_AUTO_GPT2 \|
	420	OMAP2420_AUTO_VLYNQ \|
	421	OMAP24XX_AUTO_DSS,
	422	CORE_MOD, CM_AUTOIDLE1);
	423	cm_write_mod_reg(OMAP24XX_AUTO_UART3 \|
	424	OMAP24XX_AUTO_SSI \|
	425	OMAP24XX_AUTO_USB,
	426	CORE_MOD, CM_AUTOIDLE2);
	427	cm_write_mod_reg(OMAP24XX_AUTO_SDRC \|
	428	OMAP24XX_AUTO_GPMC \|
	429	OMAP24XX_AUTO_SDMA,
	430	CORE_MOD, CM_AUTOIDLE3);
	431	cm_write_mod_reg(OMAP24XX_AUTO_PKA \|
	432	OMAP24XX_AUTO_AES \|
	433	OMAP24XX_AUTO_RNG \|
	434	OMAP24XX_AUTO_SHA \|
	435	OMAP24XX_AUTO_DES,
	436	CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
	437
	438	cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI, OMAP24XX_DSP_MOD, CM_AUTOIDLE);
	439
	440	/* Put DPLL and both APLLs into autoidle mode */
	441	cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) \|
	442	(0x03 << OMAP24XX_AUTO_96M_SHIFT) \|
	443	(0x03 << OMAP24XX_AUTO_54M_SHIFT),
	444	PLL_MOD, CM_AUTOIDLE);
	445
	446	cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL \|
	447	OMAP24XX_AUTO_WDT1 \|
	448	OMAP24XX_AUTO_MPU_WDT \|
	449	OMAP24XX_AUTO_GPIOS \|
	450	OMAP24XX_AUTO_32KSYNC \|
	451	OMAP24XX_AUTO_GPT1,
	452	WKUP_MOD, CM_AUTOIDLE);
	453
454	/* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
455	* stabilisation */
456	prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
457	OMAP2_PRCM_CLKSSETUP_OFFSET);
458
459	/* Configure automatic voltage transition */
460	prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
461	OMAP2_PRCM_VOLTSETUP_OFFSET);
462	prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT \|
463	(0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) \|
464	OMAP24XX_MEMRETCTRL \|
465	(0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) \|
466	(0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
467	OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
468
469	/* Enable wake-up events */
470	prm_write_mod_reg(OMAP24XX_EN_GPIOS \| OMAP24XX_EN_GPT1,
471	WKUP_MOD, PM_WKEN);
472	}
473
7cc515f7	474	static int __init omap2_pm_init(void)
8bd22949 KH	475	{
	476	u32 l;
	477
	478	if (!cpu_is_omap24xx())
	479	return -ENODEV;
	480
	481	printk(KERN_INFO "Power Management for OMAP2 initializing\n");
	482	l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
	483	printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
	484
	485	/* Look up important powerdomains, clockdomains */
	486
	487	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
	488	if (!mpu_pwrdm)
	489	pr_err("PM: mpu_pwrdm not found\n");
	490
	491	core_pwrdm = pwrdm_lookup("core_pwrdm");
	492	if (!core_pwrdm)
	493	pr_err("PM: core_pwrdm not found\n");
	494
	495	dsp_clkdm = clkdm_lookup("dsp_clkdm");
	496	if (!dsp_clkdm)
	497	pr_err("PM: mpu_clkdm not found\n");
	498
	499	gfx_clkdm = clkdm_lookup("gfx_clkdm");
	500	if (!gfx_clkdm)
	501	pr_err("PM: gfx_clkdm not found\n");
	502
	503
	504	osc_ck = clk_get(NULL, "osc_ck");
	505	if (IS_ERR(osc_ck)) {
	506	printk(KERN_ERR "could not get osc_ck\n");
	507	return -ENODEV;
	508	}
	509
	510	if (cpu_is_omap242x()) {
	511	emul_ck = clk_get(NULL, "emul_ck");
	512	if (IS_ERR(emul_ck)) {
	513	printk(KERN_ERR "could not get emul_ck\n");
	514	clk_put(osc_ck);
	515	return -ENODEV;
	516	}
	517	}
	518
	519	prcm_setup_regs();
	520
	521	/* Hack to prevent MPU retention when STI console is enabled. */
	522	{
	523	const struct omap_sti_console_config *sti;
	524
	525	sti = omap_get_config(OMAP_TAG_STI_CONSOLE,
	526	struct omap_sti_console_config);
	527	if (sti != NULL && sti->enable)
	528	sti_console_enabled = 1;
	529	}
	530
	531	/*
	532	* We copy the assembler sleep/wakeup routines to SRAM.
	533	* These routines need to be in SRAM as that's the only
	534	* memory the MPU can see when it wakes up.
	535	*/
	536	if (cpu_is_omap24xx()) {
	537	omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
	538	omap24xx_idle_loop_suspend_sz);
539
540	omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
541	omap24xx_cpu_suspend_sz);
542	}
543
544	suspend_set_ops(&omap_pm_ops);
545	pm_idle = omap2_pm_idle;
546
547	return 0;
548	}
549
550	late_initcall(omap2_pm_init);