[deliverable/linux.git] / arch / arm / mach-omap2 / pm24xx.c

/*
 * OMAP2 Power Management Routines
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 * Copyright (C) 2006-2008 Nokia Corporation
 *
 * Written by:
 * Richard Woodruff <r-woodruff2@ti.com>
 * Tony Lindgren
 * Juha Yrjola
 * Amit Kucheria <amit.kucheria@nokia.com>
 * Igor Stoppa <igor.stoppa@nokia.com>
 *
 * Based on pm.c for omap1
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/suspend.h>
#include <linux/sched.h>
#include <linux/proc_fs.h>
#include <linux/interrupt.h>
#include <linux/sysfs.h>
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/irq.h>
#include <linux/time.h>
#include <linux/gpio.h>
#include <linux/platform_data/gpio-omap.h>

#include <asm/mach/time.h>
#include <asm/mach/irq.h>
#include <asm/mach-types.h>
#include <asm/system_misc.h>

#include <plat-omap/dma-omap.h>

#include "../plat-omap/sram.h"

#include "soc.h"
#include "common.h"
#include "clock.h"
#include "prm2xxx_3xxx.h"
#include "prm-regbits-24xx.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-24xx.h"
#include "sdrc.h"
#include "pm.h"
#include "control.h"
#include "powerdomain.h"
#include "clockdomain.h"

static void (*omap2_sram_idle)(void);
static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
				  void __iomem *sdrc_power);

static struct powerdomain *mpu_pwrdm, *core_pwrdm;
static struct clockdomain *dsp_clkdm, *mpu_clkdm, *wkup_clkdm, *gfx_clkdm;

static struct clk *osc_ck, *emul_ck;

static int omap2_fclks_active(void)
{
	u32 f1, f2;

	f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);

	return (f1 | f2) ? 1 : 0;
}

static int omap2_enter_full_retention(void)
{
	u32 l;

	/* There is 1 reference hold for all children of the oscillator
	 * clock, the following will remove it. If no one else uses the
	 * oscillator itself it will be disabled if/when we enter retention
	 * mode.
	 */
	clk_disable(osc_ck);

	/* Clear old wake-up events */
	/* REVISIT: These write to reserved bits? */
	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
	omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);

	/*
	 * Set MPU powerdomain's next power state to RETENTION;
	 * preserve logic state during retention
	 */
	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);

	/* Workaround to kill USB */
	l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL;
	omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);

	omap2_gpio_prepare_for_idle(0);

	/* One last check for pending IRQs to avoid extra latency due
	 * to sleeping unnecessarily. */
	if (omap_irq_pending())
		goto no_sleep;

	/* Jump to SRAM suspend code */
	omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
			   OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
			   OMAP_SDRC_REGADDR(SDRC_POWER));

no_sleep:
	omap2_gpio_resume_after_idle();

	clk_enable(osc_ck);

	/* clear CORE wake-up events */
	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);

	/* wakeup domain events - bit 1: GPT1, bit5 GPIO */
	omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST);

	/* MPU domain wake events */
	l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	if (l & 0x01)
		omap2_prm_write_mod_reg(0x01, OCP_MOD,
				  OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	if (l & 0x20)
		omap2_prm_write_mod_reg(0x20, OCP_MOD,
				  OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);

	/* Mask future PRCM-to-MPU interrupts */
	omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);

	return 0;
}

static int omap2_i2c_active(void)
{
	u32 l;

	l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK);
}

static int sti_console_enabled;

static int omap2_allow_mpu_retention(void)
{
	u32 l;

	/* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
	l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK |
		 OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK |
		 OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK))
		return 0;
	/* Check for UART3. */
	l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
	if (l & OMAP24XX_EN_UART3_MASK)
		return 0;
	if (sti_console_enabled)
		return 0;

	return 1;
}

static void omap2_enter_mpu_retention(void)
{
	/* Putting MPU into the WFI state while a transfer is active
	 * seems to cause the I2C block to timeout. Why? Good question. */
	if (omap2_i2c_active())
		return;

	/* The peripherals seem not to be able to wake up the MPU when
	 * it is in retention mode. */
	if (omap2_allow_mpu_retention()) {
		/* REVISIT: These write to reserved bits? */
		omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
		omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
		omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);

		/* Try to enter MPU retention */
		omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) |
				  OMAP_LOGICRETSTATE_MASK,
				  MPU_MOD, OMAP2_PM_PWSTCTRL);
	} else {
		/* Block MPU retention */

		omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
						 OMAP2_PM_PWSTCTRL);
	}

	omap2_sram_idle();
}

static int omap2_can_sleep(void)
{
	if (omap2_fclks_active())
		return 0;
	if (osc_ck->usecount > 1)
		return 0;
	if (omap_dma_running())
		return 0;

	return 1;
}

static void omap2_pm_idle(void)
{
	local_fiq_disable();

	if (!omap2_can_sleep()) {
		if (omap_irq_pending())
			goto out;
		omap2_enter_mpu_retention();
		goto out;
	}

	if (omap_irq_pending())
		goto out;

	omap2_enter_full_retention();

out:
	local_fiq_enable();
}

static void __init prcm_setup_regs(void)
{
	int i, num_mem_banks;
	struct powerdomain *pwrdm;

	/*
	 * Enable autoidle
	 * XXX This should be handled by hwmod code or PRCM init code
	 */
	omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
			  OMAP2_PRCM_SYSCONFIG_OFFSET);

	/*
	 * Set CORE powerdomain memory banks to retain their contents
	 * during RETENTION
	 */
	num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
	for (i = 0; i < num_mem_banks; i++)
		pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);

	/* Set CORE powerdomain's next power state to RETENTION */
	pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);

	/*
	 * Set MPU powerdomain's next power state to RETENTION;
	 * preserve logic state during retention
	 */
	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);

	/* Force-power down DSP, GFX powerdomains */

	pwrdm = clkdm_get_pwrdm(dsp_clkdm);
	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
	clkdm_sleep(dsp_clkdm);

	pwrdm = clkdm_get_pwrdm(gfx_clkdm);
	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
	clkdm_sleep(gfx_clkdm);

	/* Enable hardware-supervised idle for all clkdms */
	clkdm_for_each(omap_pm_clkdms_setup, NULL);
	clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);

#ifdef CONFIG_SUSPEND
	omap_pm_suspend = omap2_enter_full_retention;
#endif

	/* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
	 * stabilisation */
	omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
				OMAP2_PRCM_CLKSSETUP_OFFSET);

	/* Configure automatic voltage transition */
	omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
				OMAP2_PRCM_VOLTSETUP_OFFSET);
	omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK |
				(0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) |
				OMAP24XX_MEMRETCTRL_MASK |
				(0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) |
				(0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
				OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);

	/* Enable wake-up events */
	omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
				WKUP_MOD, PM_WKEN);
}

int __init omap2_pm_init(void)
{
	u32 l;

	printk(KERN_INFO "Power Management for OMAP2 initializing\n");
	l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
	printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);

	/* Look up important powerdomains */

	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
	if (!mpu_pwrdm)
		pr_err("PM: mpu_pwrdm not found\n");

	core_pwrdm = pwrdm_lookup("core_pwrdm");
	if (!core_pwrdm)
		pr_err("PM: core_pwrdm not found\n");

	/* Look up important clockdomains */

	mpu_clkdm = clkdm_lookup("mpu_clkdm");
	if (!mpu_clkdm)
		pr_err("PM: mpu_clkdm not found\n");

	wkup_clkdm = clkdm_lookup("wkup_clkdm");
	if (!wkup_clkdm)
		pr_err("PM: wkup_clkdm not found\n");

	dsp_clkdm = clkdm_lookup("dsp_clkdm");
	if (!dsp_clkdm)
		pr_err("PM: dsp_clkdm not found\n");

	gfx_clkdm = clkdm_lookup("gfx_clkdm");
	if (!gfx_clkdm)
		pr_err("PM: gfx_clkdm not found\n");


	osc_ck = clk_get(NULL, "osc_ck");
	if (IS_ERR(osc_ck)) {
		printk(KERN_ERR "could not get osc_ck\n");
		return -ENODEV;
	}

	if (cpu_is_omap242x()) {
		emul_ck = clk_get(NULL, "emul_ck");
		if (IS_ERR(emul_ck)) {
			printk(KERN_ERR "could not get emul_ck\n");
			clk_put(osc_ck);
			return -ENODEV;
		}
	}

	prcm_setup_regs();

	/*
	 * We copy the assembler sleep/wakeup routines to SRAM.
	 * These routines need to be in SRAM as that's the only
	 * memory the MPU can see when it wakes up.
	 */
	omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
					 omap24xx_idle_loop_suspend_sz);

	omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
					    omap24xx_cpu_suspend_sz);

	arm_pm_idle = omap2_pm_idle;

	return 0;
}
Commit	Line	Data
8bd22949 KH	1	/*
	2	* OMAP2 Power Management Routines
	3	*
	4	* Copyright (C) 2005 Texas Instruments, Inc.
	5	* Copyright (C) 2006-2008 Nokia Corporation
	6	*
	7	* Written by:
	8	* Richard Woodruff <r-woodruff2@ti.com>
	9	* Tony Lindgren
	10	* Juha Yrjola
	11	* Amit Kucheria <amit.kucheria@nokia.com>
	12	* Igor Stoppa <igor.stoppa@nokia.com>
	13	*
	14	* Based on pm.c for omap1
	15	*
	16	* This program is free software; you can redistribute it and/or modify
	17	* it under the terms of the GNU General Public License version 2 as
	18	* published by the Free Software Foundation.
	19	*/
	20
	21	#include <linux/suspend.h>
	22	#include <linux/sched.h>
	23	#include <linux/proc_fs.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/sysfs.h>
	26	#include <linux/module.h>
	27	#include <linux/delay.h>
	28	#include <linux/clk.h>
8bd22949 KH	29	#include <linux/irq.h>
	30	#include <linux/time.h>
	31	#include <linux/gpio.h>
4b25408f	32	#include <linux/platform_data/gpio-omap.h>
8bd22949 KH	33
	34	#include <asm/mach/time.h>
	35	#include <asm/mach/irq.h>
	36	#include <asm/mach-types.h>
9f97da78	37	#include <asm/system_misc.h>
8bd22949	38
2b6c4e73	39	#include <plat-omap/dma-omap.h>
8bd22949	40
622297fd TL	41	#include "../plat-omap/sram.h"
622297fd TL	42
e4c060db	43	#include "soc.h"
4e65331c	44	#include "common.h"
a135eaae	45	#include "clock.h"
59fb659b	46	#include "prm2xxx_3xxx.h"
8bd22949	47	#include "prm-regbits-24xx.h"
59fb659b	48	#include "cm2xxx_3xxx.h"
8bd22949 KH	49	#include "cm-regbits-24xx.h"
	50	#include "sdrc.h"
	51	#include "pm.h"
4814ced5	52	#include "control.h"
72e06d08	53	#include "powerdomain.h"
1540f214	54	#include "clockdomain.h"
8bd22949 KH	55
	56	static void (*omap2_sram_idle)(void);
	57	static void (omap2_sram_suspend)(u32 dllctrl, void __iomem sdrc_dlla_ctrl,
	58	void __iomem *sdrc_power);
	59
369d5614 PW	60	static struct powerdomain mpu_pwrdm, core_pwrdm;
369d5614 PW	61	static struct clockdomain dsp_clkdm, mpu_clkdm, wkup_clkdm, gfx_clkdm;
8bd22949 KH	62
	63	static struct clk osc_ck, emul_ck;
	64
	65	static int omap2_fclks_active(void)
	66	{
	67	u32 f1, f2;
	68
c4d7e58f PW	69	f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
c4d7e58f PW	70	f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
4af4016c	71
1e056ddd	72	return (f1 \| f2) ? 1 : 0;
8bd22949 KH	73	}
8bd22949 KH	74
1416408d	75	static int omap2_enter_full_retention(void)
8bd22949 KH	76	{
8bd22949 KH	77	u32 l;
8bd22949 KH	78
	79	/* There is 1 reference hold for all children of the oscillator
	80	* clock, the following will remove it. If no one else uses the
	81	* oscillator itself it will be disabled if/when we enter retention
	82	* mode.
	83	*/
	84	clk_disable(osc_ck);
	85
	86	/* Clear old wake-up events */
	87	/* REVISIT: These write to reserved bits? */
c4d7e58f PW	88	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	89	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
	90	omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
8bd22949 KH	91
	92	/*
	93	* Set MPU powerdomain's next power state to RETENTION;
	94	* preserve logic state during retention
	95	*/
	96	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
	97	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
	98
	99	/* Workaround to kill USB */
	100	l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) \| OMAP24XX_USBSTANDBYCTRL;
	101	omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0);
	102
72e06d08	103	omap2_gpio_prepare_for_idle(0);
8bd22949	104
8bd22949 KH	105	/* One last check for pending IRQs to avoid extra latency due
8bd22949 KH	106	* to sleeping unnecessarily. */
94434535	107	if (omap_irq_pending())
8bd22949 KH	108	goto no_sleep;
	109
	110	/* Jump to SRAM suspend code */
	111	omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL),
	112	OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL),
	113	OMAP_SDRC_REGADDR(SDRC_POWER));
8bd22949	114
4af4016c	115	no_sleep:
43ffcd9a	116	omap2_gpio_resume_after_idle();
8bd22949 KH	117
	118	clk_enable(osc_ck);
	119
	120	/* clear CORE wake-up events */
c4d7e58f PW	121	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
c4d7e58f PW	122	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
8bd22949 KH	123
8bd22949 KH	124	/* wakeup domain events - bit 1: GPT1, bit5 GPIO */
c4d7e58f	125	omap2_prm_clear_mod_reg_bits(0x4 \| 0x1, WKUP_MOD, PM_WKST);
8bd22949 KH	126
8bd22949 KH	127	/* MPU domain wake events */
c4d7e58f	128	l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
8bd22949	129	if (l & 0x01)
c4d7e58f	130	omap2_prm_write_mod_reg(0x01, OCP_MOD,
8bd22949 KH	131	OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
8bd22949 KH	132	if (l & 0x20)
c4d7e58f	133	omap2_prm_write_mod_reg(0x20, OCP_MOD,
8bd22949 KH	134	OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
	135
	136	/* Mask future PRCM-to-MPU interrupts */
c4d7e58f	137	omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
1416408d PW	138
1416408d PW	139	return 0;
8bd22949 KH	140	}
	141
	142	static int omap2_i2c_active(void)
	143	{
	144	u32 l;
	145
c4d7e58f	146	l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
f38ca10a	147	return l & (OMAP2420_EN_I2C2_MASK \| OMAP2420_EN_I2C1_MASK);
8bd22949 KH	148	}
	149
	150	static int sti_console_enabled;
	151
	152	static int omap2_allow_mpu_retention(void)
	153	{
	154	u32 l;
	155
	156	/* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
c4d7e58f	157	l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
2fd0f75c PW	158	if (l & (OMAP2420_EN_MMC_MASK \| OMAP24XX_EN_UART2_MASK \|
	159	OMAP24XX_EN_UART1_MASK \| OMAP24XX_EN_MCSPI2_MASK \|
	160	OMAP24XX_EN_MCSPI1_MASK \| OMAP24XX_EN_DSS1_MASK))
8bd22949 KH	161	return 0;
8bd22949 KH	162	/* Check for UART3. */
c4d7e58f	163	l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2);
2fd0f75c	164	if (l & OMAP24XX_EN_UART3_MASK)
8bd22949 KH	165	return 0;
	166	if (sti_console_enabled)
	167	return 0;
	168
	169	return 1;
	170	}
	171
	172	static void omap2_enter_mpu_retention(void)
	173	{
8bd22949 KH	174	/* Putting MPU into the WFI state while a transfer is active
	175	* seems to cause the I2C block to timeout. Why? Good question. */
	176	if (omap2_i2c_active())
	177	return;
	178
	179	/* The peripherals seem not to be able to wake up the MPU when
	180	* it is in retention mode. */
	181	if (omap2_allow_mpu_retention()) {
	182	/* REVISIT: These write to reserved bits? */
c4d7e58f PW	183	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1);
	184	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2);
	185	omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST);
8bd22949 KH	186
8bd22949 KH	187	/* Try to enter MPU retention */
c4d7e58f	188	omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) \|
2fd0f75c	189	OMAP_LOGICRETSTATE_MASK,
37903009	190	MPU_MOD, OMAP2_PM_PWSTCTRL);
8bd22949 KH	191	} else {
	192	/* Block MPU retention */
	193
c4d7e58f	194	omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD,
37903009	195	OMAP2_PM_PWSTCTRL);
8bd22949 KH	196	}
8bd22949 KH	197
8bd22949	198	omap2_sram_idle();
8bd22949 KH	199	}
	200
	201	static int omap2_can_sleep(void)
	202	{
	203	if (omap2_fclks_active())
	204	return 0;
	205	if (osc_ck->usecount > 1)
	206	return 0;
	207	if (omap_dma_running())
	208	return 0;
	209
	210	return 1;
	211	}
	212
	213	static void omap2_pm_idle(void)
	214	{
8bd22949 KH	215	local_fiq_disable();
	216
	217	if (!omap2_can_sleep()) {
94434535	218	if (omap_irq_pending())
8bd22949 KH	219	goto out;
	220	omap2_enter_mpu_retention();
	221	goto out;
	222	}
	223
94434535	224	if (omap_irq_pending())
8bd22949 KH	225	goto out;
	226
	227	omap2_enter_full_retention();
	228
	229	out:
	230	local_fiq_enable();
8bd22949 KH	231	}
8bd22949 KH	232
8bd22949 KH	233	static void __init prcm_setup_regs(void)
	234	{
	235	int i, num_mem_banks;
	236	struct powerdomain *pwrdm;
	237
4ef70c06 PW	238	/*
	239	* Enable autoidle
	240	* XXX This should be handled by hwmod code or PRCM init code
	241	*/
c4d7e58f	242	omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
8bd22949 KH	243	OMAP2_PRCM_SYSCONFIG_OFFSET);
8bd22949 KH	244
8bd22949 KH	245	/*
	246	* Set CORE powerdomain memory banks to retain their contents
	247	* during RETENTION
	248	*/
	249	num_mem_banks = pwrdm_get_mem_bank_count(core_pwrdm);
	250	for (i = 0; i < num_mem_banks; i++)
	251	pwrdm_set_mem_retst(core_pwrdm, i, PWRDM_POWER_RET);
	252
	253	/* Set CORE powerdomain's next power state to RETENTION */
	254	pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET);
	255
	256	/*
	257	* Set MPU powerdomain's next power state to RETENTION;
	258	* preserve logic state during retention
	259	*/
	260	pwrdm_set_logic_retst(mpu_pwrdm, PWRDM_POWER_RET);
	261	pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET);
	262
	263	/* Force-power down DSP, GFX powerdomains */
	264
	265	pwrdm = clkdm_get_pwrdm(dsp_clkdm);
	266	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
68b921ad	267	clkdm_sleep(dsp_clkdm);
8bd22949 KH	268
	269	pwrdm = clkdm_get_pwrdm(gfx_clkdm);
	270	pwrdm_set_next_pwrst(pwrdm, PWRDM_POWER_OFF);
68b921ad	271	clkdm_sleep(gfx_clkdm);
8bd22949	272
51d070af	273	/* Enable hardware-supervised idle for all clkdms */
92206fd2	274	clkdm_for_each(omap_pm_clkdms_setup, NULL);
369d5614	275	clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
8bd22949	276
1416408d PW	277	#ifdef CONFIG_SUSPEND
	278	omap_pm_suspend = omap2_enter_full_retention;
	279	#endif
	280
8bd22949 KH	281	/* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
8bd22949 KH	282	* stabilisation */
c4d7e58f PW	283	omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
c4d7e58f PW	284	OMAP2_PRCM_CLKSSETUP_OFFSET);
8bd22949 KH	285
8bd22949 KH	286	/* Configure automatic voltage transition */
c4d7e58f PW	287	omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
	288	OMAP2_PRCM_VOLTSETUP_OFFSET);
	289	omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK \|
	290	(0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) \|
	291	OMAP24XX_MEMRETCTRL_MASK \|
	292	(0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) \|
	293	(0x0 << OMAP24XX_VOLT_LEVEL_SHIFT),
	294	OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET);
8bd22949 KH	295
8bd22949 KH	296	/* Enable wake-up events */
c4d7e58f PW	297	omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK \| OMAP24XX_EN_GPT1_MASK,
c4d7e58f PW	298	WKUP_MOD, PM_WKEN);
8bd22949 KH	299	}
8bd22949 KH	300
bbd707ac	301	int __init omap2_pm_init(void)
8bd22949 KH	302	{
	303	u32 l;
	304
8bd22949	305	printk(KERN_INFO "Power Management for OMAP2 initializing\n");
c4d7e58f	306	l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET);
8bd22949 KH	307	printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
8bd22949 KH	308
369d5614	309	/* Look up important powerdomains */
8bd22949 KH	310
	311	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
	312	if (!mpu_pwrdm)
	313	pr_err("PM: mpu_pwrdm not found\n");
	314
	315	core_pwrdm = pwrdm_lookup("core_pwrdm");
	316	if (!core_pwrdm)
	317	pr_err("PM: core_pwrdm not found\n");
	318
369d5614 PW	319	/* Look up important clockdomains */
	320
	321	mpu_clkdm = clkdm_lookup("mpu_clkdm");
	322	if (!mpu_clkdm)
	323	pr_err("PM: mpu_clkdm not found\n");
	324
	325	wkup_clkdm = clkdm_lookup("wkup_clkdm");
	326	if (!wkup_clkdm)
	327	pr_err("PM: wkup_clkdm not found\n");
	328
8bd22949 KH	329	dsp_clkdm = clkdm_lookup("dsp_clkdm");
8bd22949 KH	330	if (!dsp_clkdm)
369d5614	331	pr_err("PM: dsp_clkdm not found\n");
8bd22949 KH	332
	333	gfx_clkdm = clkdm_lookup("gfx_clkdm");
	334	if (!gfx_clkdm)
	335	pr_err("PM: gfx_clkdm not found\n");
	336
	337
	338	osc_ck = clk_get(NULL, "osc_ck");
	339	if (IS_ERR(osc_ck)) {
	340	printk(KERN_ERR "could not get osc_ck\n");
	341	return -ENODEV;
	342	}
	343
	344	if (cpu_is_omap242x()) {
	345	emul_ck = clk_get(NULL, "emul_ck");
	346	if (IS_ERR(emul_ck)) {
	347	printk(KERN_ERR "could not get emul_ck\n");
	348	clk_put(osc_ck);
	349	return -ENODEV;
	350	}
	351	}
	352
	353	prcm_setup_regs();
	354
8bd22949 KH	355	/*
	356	* We copy the assembler sleep/wakeup routines to SRAM.
	357	* These routines need to be in SRAM as that's the only
	358	* memory the MPU can see when it wakes up.
	359	*/
bbd707ac SG	360	omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
bbd707ac SG	361	omap24xx_idle_loop_suspend_sz);
8bd22949	362
bbd707ac SG	363	omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
bbd707ac SG	364	omap24xx_cpu_suspend_sz);
8bd22949	365
0bcd24b0	366	arm_pm_idle = omap2_pm_idle;
8bd22949 KH	367
	368	return 0;
	369	}