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Merge tag 'gpio-for-linus' of git://git.secretlab.ca/git/linux
[deliverable/linux.git] / arch / arm / mach-omap2 / pm34xx.c
CommitLineData
8bd22949
KH		 1/*
2 * OMAP3 Power Management Routines
3 *
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 * Jouni Hogander
7 *
2f5939c3
RN		 8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
10 *
8bd22949
KH		 11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
13 *
14 * Based on pm.c for omap1
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/pm.h>
22#include <linux/suspend.h>
23#include <linux/interrupt.h>
24#include <linux/module.h>
25#include <linux/list.h>
26#include <linux/err.h>
27#include <linux/gpio.h>
c40552bc 28#include <linux/clk.h>
dccaad89 29#include <linux/delay.h>
5a0e3ad6 30#include <linux/slab.h>
45c3eb7d 31#include <linux/omap-dma.h>
4b25408f
TL		 32#include <linux/platform_data/gpio-omap.h>
33
5e7c58dc 34#include <trace/events/power.h>
8bd22949 35
bf027ca1 36#include <asm/fncpy.h>
2c74a0ce 37#include <asm/suspend.h>
9f97da78 38#include <asm/system_misc.h>
2c74a0ce 39
1540f214 40#include "clockdomain.h"
72e06d08 41#include "powerdomain.h"
e4c060db 42#include "soc.h"
4e65331c 43#include "common.h"
ff4ae5d9 44#include "cm3xxx.h"
8bd22949 45#include "cm-regbits-34xx.h"
99f0b8d6 46#include "gpmc.h"
8bd22949 47#include "prm-regbits-34xx.h"
139563ad 48#include "prm3xxx.h"
8bd22949 49#include "pm.h"
13a6fe0f 50#include "sdrc.h"
bf027ca1 51#include "sram.h"
4814ced5 52#include "control.h"
13a6fe0f 53
8cdfd834
NM		 54/* pm34xx errata defined in pm.h */
55u16 pm34xx_errata;
56
8bd22949
KH		 57struct power_state {
58 struct powerdomain *pwrdm;
59 u32 next_state;
10f90ed2 60#ifdef CONFIG_SUSPEND
8bd22949 61 u32 saved_state;
10f90ed2 62#endif
8bd22949
KH		 63 struct list_head node;
64};
65
66static LIST_HEAD(pwrst_list);
67
27d59a4a 68static int (*_omap_save_secure_sram)(u32 *addr);
46e130d2 69void (*omap3_do_wfi_sram)(void);
27d59a4a 70
fa3c2a4f
RN		 71static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
72static struct powerdomain *core_pwrdm, *per_pwrdm;
3a7ec26b 73
2f5939c3
RN		 74static void omap3_core_save_context(void)
75{
596efe47 76 omap3_ctrl_save_padconf();
dccaad89
TK		 77
78 /*
79 * Force write last pad into memory, as this can fail in some
83521291 80 * cases according to errata 1.157, 1.185
dccaad89
TK		 81 */
82 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
83 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
84
2f5939c3
RN		 85 /* Save the Interrupt controller context */
86 omap_intc_save_context();
87 /* Save the GPMC context */
88 omap3_gpmc_save_context();
89 /* Save the system control module context, padconf already save above*/
90 omap3_control_save_context();
f2d11858 91 omap_dma_global_context_save();
2f5939c3
RN		 92}
93
94static void omap3_core_restore_context(void)
95{
96 /* Restore the control module context, padconf restored by h/w */
97 omap3_control_restore_context();
98 /* Restore the GPMC context */
99 omap3_gpmc_restore_context();
100 /* Restore the interrupt controller context */
101 omap_intc_restore_context();
f2d11858 102 omap_dma_global_context_restore();
2f5939c3
RN		 103}
104
9d97140b
TK		 105/*
106 * FIXME: This function should be called before entering off-mode after
107 * OMAP3 secure services have been accessed. Currently it is only called
108 * once during boot sequence, but this works as we are not using secure
109 * services.
110 */
617fcc98 111static void omap3_save_secure_ram_context(void)
27d59a4a
TK		 112{
113 u32 ret;
617fcc98 114 int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
27d59a4a
TK		 115
116 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
27d59a4a
TK		 117 /*
118 * MPU next state must be set to POWER_ON temporarily,
119 * otherwise the WFI executed inside the ROM code
120 * will hang the system.
121 */
122 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
123 ret = _omap_save_secure_sram((u32 *)
124 __pa(omap3_secure_ram_storage));
617fcc98 125 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
27d59a4a
TK		 126 /* Following is for error tracking, it should not happen */
127 if (ret) {
98179856 128 pr_err("save_secure_sram() returns %08x\n", ret);
27d59a4a
TK		 129 while (1)
130 ;
131 }
132 }
133}
134
77da2d91
JH		 135/*
136 * PRCM Interrupt Handler Helper Function
137 *
138 * The purpose of this function is to clear any wake-up events latched
139 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
140 * may occur whilst attempting to clear a PM_WKST_x register and thus
141 * set another bit in this register. A while loop is used to ensure
142 * that any peripheral wake-up events occurring while attempting to
143 * clear the PM_WKST_x are detected and cleared.
144 */
22f51371 145static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
8bd22949 146{
71a80775 147 u32 wkst, fclk, iclk, clken;
77da2d91
JH		 148 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
149 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
150 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
5d805978
PW		 151 u16 grpsel_off = (regs == 3) ?
152 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
8cb0ac99 153 int c = 0;
8bd22949 154
c4d7e58f
PW		 155 wkst = omap2_prm_read_mod_reg(module, wkst_off);
156 wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
22f51371 157 wkst &= ~ignore_bits;
8bd22949 158 if (wkst) {
c4d7e58f
PW		 159 iclk = omap2_cm_read_mod_reg(module, iclk_off);
160 fclk = omap2_cm_read_mod_reg(module, fclk_off);
77da2d91 161 while (wkst) {
71a80775 162 clken = wkst;
c4d7e58f 163 omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
71a80775
VP		 164 /*
165 * For USBHOST, we don't know whether HOST1 or
166 * HOST2 woke us up, so enable both f-clocks
167 */
168 if (module == OMAP3430ES2_USBHOST_MOD)
169 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
c4d7e58f
PW		 170 omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
171 omap2_prm_write_mod_reg(wkst, module, wkst_off);
172 wkst = omap2_prm_read_mod_reg(module, wkst_off);
22f51371 173 wkst &= ~ignore_bits;
8cb0ac99 174 c++;
77da2d91 175 }
c4d7e58f
PW		 176 omap2_cm_write_mod_reg(iclk, module, iclk_off);
177 omap2_cm_write_mod_reg(fclk, module, fclk_off);
8bd22949 178 }
8cb0ac99
PW		 179
180 return c;
181}
182
22f51371 183static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
8cb0ac99
PW		 184{
185 int c;
186
22f51371
TK		 187 c = prcm_clear_mod_irqs(WKUP_MOD, 1,
188 ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
8cb0ac99 189
22f51371 190 return c ? IRQ_HANDLED : IRQ_NONE;
77da2d91 191}
8bd22949 192
22f51371 193static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
77da2d91 194{
22f51371 195 int c;
d6290a3e 196
22f51371
TK		 197 /*
198 * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
199 * these are handled in a separate handler to avoid acking
200 * IO events before parsing in mux code
201 */
202 c = prcm_clear_mod_irqs(WKUP_MOD, 1,
203 OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
204 c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
205 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
206 if (omap_rev() > OMAP3430_REV_ES1_0) {
207 c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
208 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
209 }
8bd22949 210
22f51371 211 return c ? IRQ_HANDLED : IRQ_NONE;
8bd22949
KH		 212}
213
cbe26349
RK		 214static void omap34xx_save_context(u32 *save)
215{
216 u32 val;
217
218 /* Read Auxiliary Control Register */
219 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
220 *save++ = 1;
221 *save++ = val;
222
223 /* Read L2 AUX ctrl register */
224 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
225 *save++ = 1;
226 *save++ = val;
227}
228
29cb3cd2 229static int omap34xx_do_sram_idle(unsigned long save_state)
57f277b0 230{
cbe26349 231 omap34xx_cpu_suspend(save_state);
29cb3cd2 232 return 0;
57f277b0
RN		 233}
234
99e6a4d2 235void omap_sram_idle(void)
8bd22949
KH		 236{
237 /* Variable to tell what needs to be saved and restored
238 * in omap_sram_idle*/
239 /* save_state = 0 => Nothing to save and restored */
240 /* save_state = 1 => Only L1 and logic lost */
241 /* save_state = 2 => Only L2 lost */
242 /* save_state = 3 => L1, L2 and logic lost */
fa3c2a4f
RN		 243 int save_state = 0;
244 int mpu_next_state = PWRDM_POWER_ON;
245 int per_next_state = PWRDM_POWER_ON;
246 int core_next_state = PWRDM_POWER_ON;
72e06d08 247 int per_going_off;
eeb3711b 248 int core_prev_state;
13a6fe0f 249 u32 sdrc_pwr = 0;
8bd22949 250
8bd22949
KH		 251 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
252 switch (mpu_next_state) {
fa3c2a4f 253 case PWRDM_POWER_ON:
8bd22949
KH		 254 case PWRDM_POWER_RET:
255 /* No need to save context */
256 save_state = 0;
257 break;
61255ab9
RN		 258 case PWRDM_POWER_OFF:
259 save_state = 3;
260 break;
8bd22949
KH		 261 default:
262 /* Invalid state */
98179856 263 pr_err("Invalid mpu state in sram_idle\n");
8bd22949
KH		 264 return;
265 }
fe617af7 266
fa3c2a4f
RN		 267 /* NEON control */
268 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
7139178e 269 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
fa3c2a4f 270
40742fa8 271 /* Enable IO-PAD and IO-CHAIN wakeups */
658ce97e 272 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
ecf157d0 273 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
40742fa8 274
e0e29fd7 275 pwrdm_pre_transition(NULL);
ff2f8e5f 276
40742fa8 277 /* PER */
658ce97e 278 if (per_next_state < PWRDM_POWER_ON) {
72e06d08 279 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
72e06d08 280 omap2_gpio_prepare_for_idle(per_going_off);
658ce97e
KH		 281 }
282
283 /* CORE */
fa3c2a4f 284 if (core_next_state < PWRDM_POWER_ON) {
2f5939c3
RN		 285 if (core_next_state == PWRDM_POWER_OFF) {
286 omap3_core_save_context();
f0611a5c 287 omap3_cm_save_context();
2f5939c3 288 }
fa3c2a4f 289 }
40742fa8 290
f18cc2ff 291 omap3_intc_prepare_idle();
8bd22949 292
13a6fe0f 293 /*
30474544
PW		 294 * On EMU/HS devices ROM code restores a SRDC value
295 * from scratchpad which has automatic self refresh on timeout
296 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
297 * Hence store/restore the SDRC_POWER register here.
298 */
299 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
300 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
301 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
f265dc4c 302 core_next_state == PWRDM_POWER_OFF)
13a6fe0f 303 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
13a6fe0f 304
61255ab9 305 /*
076f2cc4
RK		 306 * omap3_arm_context is the location where some ARM context
307 * get saved. The rest is placed on the stack, and restored
308 * from there before resuming.
61255ab9 309 */
cbe26349
RK		 310 if (save_state)
311 omap34xx_save_context(omap3_arm_context);
076f2cc4 312 if (save_state == 1 || save_state == 3)
2c74a0ce 313 cpu_suspend(save_state, omap34xx_do_sram_idle);
076f2cc4
RK		 314 else
315 omap34xx_do_sram_idle(save_state);
8bd22949 316
f265dc4c 317 /* Restore normal SDRC POWER settings */
30474544
PW		 318 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
319 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
320 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
13a6fe0f
TK		 321 core_next_state == PWRDM_POWER_OFF)
322 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
323
658ce97e 324 /* CORE */
fa3c2a4f 325 if (core_next_state < PWRDM_POWER_ON) {
2f5939c3
RN		 326 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
327 if (core_prev_state == PWRDM_POWER_OFF) {
328 omap3_core_restore_context();
f0611a5c 329 omap3_cm_restore_context();
2f5939c3 330 omap3_sram_restore_context();
8a917d2f 331 omap2_sms_restore_context();
2f5939c3 332 }
658ce97e 333 if (core_next_state == PWRDM_POWER_OFF)
c4d7e58f 334 omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
658ce97e
KH		 335 OMAP3430_GR_MOD,
336 OMAP3_PRM_VOLTCTRL_OFFSET);
337 }
f18cc2ff 338 omap3_intc_resume_idle();
658ce97e 339
e0e29fd7
KH		 340 pwrdm_post_transition(NULL);
341
658ce97e 342 /* PER */
e0e29fd7 343 if (per_next_state < PWRDM_POWER_ON)
43ffcd9a 344 omap2_gpio_resume_after_idle();
8bd22949
KH		 345}
346
8bd22949
KH		 347static void omap3_pm_idle(void)
348{
0bcd24b0 349 if (omap_irq_pending())
6b85638b 350 return;
8bd22949 351
5e7c58dc
JP		 352 trace_cpu_idle(1, smp_processor_id());
353
8bd22949
KH		 354 omap_sram_idle();
355
5e7c58dc 356 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
8bd22949
KH		 357}
358
10f90ed2 359#ifdef CONFIG_SUSPEND
8bd22949
KH		 360static int omap3_pm_suspend(void)
361{
362 struct power_state *pwrst;
363 int state, ret = 0;
364
365 /* Read current next_pwrsts */
366 list_for_each_entry(pwrst, &pwrst_list, node)
367 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
368 /* Set ones wanted by suspend */
369 list_for_each_entry(pwrst, &pwrst_list, node) {
eb6a2c75 370 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
8bd22949
KH		 371 goto restore;
372 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
373 goto restore;
374 }
375
2bbe3af3
TK		 376 omap3_intc_suspend();
377
8bd22949
KH		 378 omap_sram_idle();
379
380restore:
381 /* Restore next_pwrsts */
382 list_for_each_entry(pwrst, &pwrst_list, node) {
8bd22949
KH		 383 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
384 if (state > pwrst->next_state) {
7852ec05
PW		 385 pr_info("Powerdomain (%s) didn't enter target state %d\n",
386 pwrst->pwrdm->name, pwrst->next_state);
8bd22949
KH		 387 ret = -1;
388 }
eb6a2c75 389 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
8bd22949
KH		 390 }
391 if (ret)
98179856 392 pr_err("Could not enter target state in pm_suspend\n");
8bd22949 393 else
98179856 394 pr_info("Successfully put all powerdomains to target state\n");
8bd22949
KH		 395
396 return ret;
397}
398
10f90ed2 399#endif /* CONFIG_SUSPEND */
8bd22949 400
1155e426
KH		 401
402/**
403 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
404 * retention
405 *
406 * In cases where IVA2 is activated by bootcode, it may prevent
407 * full-chip retention or off-mode because it is not idle. This
408 * function forces the IVA2 into idle state so it can go
409 * into retention/off and thus allow full-chip retention/off.
410 *
411 **/
412static void __init omap3_iva_idle(void)
413{
414 /* ensure IVA2 clock is disabled */
c4d7e58f 415 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
1155e426
KH		 416
417 /* if no clock activity, nothing else to do */
c4d7e58f 418 if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
1155e426
KH		 419 OMAP3430_CLKACTIVITY_IVA2_MASK))
420 return;
421
422 /* Reset IVA2 */
c4d7e58f 423 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
2bc4ef71
PW		 424 OMAP3430_RST2_IVA2_MASK |
425 OMAP3430_RST3_IVA2_MASK,
37903009 426 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
1155e426
KH		 427
428 /* Enable IVA2 clock */
c4d7e58f 429 omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
1155e426
KH		 430 OMAP3430_IVA2_MOD, CM_FCLKEN);
431
432 /* Set IVA2 boot mode to 'idle' */
433 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
434 OMAP343X_CONTROL_IVA2_BOOTMOD);
435
436 /* Un-reset IVA2 */
c4d7e58f 437 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
1155e426
KH		 438
439 /* Disable IVA2 clock */
c4d7e58f 440 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
1155e426
KH		 441
442 /* Reset IVA2 */
c4d7e58f 443 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
2bc4ef71
PW		 444 OMAP3430_RST2_IVA2_MASK |
445 OMAP3430_RST3_IVA2_MASK,
37903009 446 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
1155e426
KH		 447}
448
8111b221 449static void __init omap3_d2d_idle(void)
8bd22949 450{
8111b221
KH		 451 u16 mask, padconf;
452
453 /* In a stand alone OMAP3430 where there is not a stacked
454 * modem for the D2D Idle Ack and D2D MStandby must be pulled
455 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
456 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
457 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
458 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
459 padconf |= mask;
460 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
461
462 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
463 padconf |= mask;
464 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
465
8bd22949 466 /* reset modem */
c4d7e58f 467 omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
2bc4ef71 468 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
37903009 469 CORE_MOD, OMAP2_RM_RSTCTRL);
c4d7e58f 470 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
8111b221 471}
8bd22949 472
8111b221
KH		 473static void __init prcm_setup_regs(void)
474{
e5863689
G		 475 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
476 OMAP3630_EN_UART4_MASK : 0;
477 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
478 OMAP3630_GRPSEL_UART4_MASK : 0;
479
4ef70c06 480 /* XXX This should be handled by hwmod code or SCM init code */
2fd0f75c 481 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
b296c811 482
8bd22949
KH		 483 /*
484 * Enable control of expternal oscillator through
485 * sys_clkreq. In the long run clock framework should
486 * take care of this.
487 */
c4d7e58f 488 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
8bd22949
KH		 489 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
490 OMAP3430_GR_MOD,
491 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
492
493 /* setup wakup source */
c4d7e58f 494 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
2fd0f75c 495 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
8bd22949
KH		 496 WKUP_MOD, PM_WKEN);
497 /* No need to write EN_IO, that is always enabled */
c4d7e58f 498 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
275f675c
PW		 499 OMAP3430_GRPSEL_GPT1_MASK |
500 OMAP3430_GRPSEL_GPT12_MASK,
8bd22949 501 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
1155e426 502
b92c5721 503 /* Enable PM_WKEN to support DSS LPR */
c4d7e58f 504 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
b92c5721
SV		 505 OMAP3430_DSS_MOD, PM_WKEN);
506
b427f92f 507 /* Enable wakeups in PER */
c4d7e58f 508 omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
e5863689 509 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
2fd0f75c
PW		 510 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
511 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
512 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
513 OMAP3430_EN_MCBSP4_MASK,
b427f92f 514 OMAP3430_PER_MOD, PM_WKEN);
eb350f74 515 /* and allow them to wake up MPU */
c4d7e58f 516 omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
e5863689 517 OMAP3430_GRPSEL_GPIO2_MASK |
275f675c
PW		 518 OMAP3430_GRPSEL_GPIO3_MASK |
519 OMAP3430_GRPSEL_GPIO4_MASK |
520 OMAP3430_GRPSEL_GPIO5_MASK |
521 OMAP3430_GRPSEL_GPIO6_MASK |
522 OMAP3430_GRPSEL_UART3_MASK |
523 OMAP3430_GRPSEL_MCBSP2_MASK |
524 OMAP3430_GRPSEL_MCBSP3_MASK |
525 OMAP3430_GRPSEL_MCBSP4_MASK,
eb350f74
KH		 526 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
527
d3fd3290 528 /* Don't attach IVA interrupts */
a819c4f1
MG		 529 if (omap3_has_iva()) {
530 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
531 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
532 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
533 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
534 OMAP3430_PM_IVAGRPSEL);
535 }
d3fd3290 536
b1340d17 537 /* Clear any pending 'reset' flags */
c4d7e58f
PW		 538 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
539 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
540 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
541 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
542 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
543 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
544 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
b1340d17 545
014c46db 546 /* Clear any pending PRCM interrupts */
c4d7e58f 547 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
014c46db 548
a819c4f1
MG		 549 if (omap3_has_iva())
550 omap3_iva_idle();
551
8111b221 552 omap3_d2d_idle();
8bd22949
KH		 553}
554
c40552bc
KH		 555void omap3_pm_off_mode_enable(int enable)
556{
557 struct power_state *pwrst;
558 u32 state;
559
560 if (enable)
561 state = PWRDM_POWER_OFF;
562 else
563 state = PWRDM_POWER_RET;
564
565 list_for_each_entry(pwrst, &pwrst_list, node) {
cc1b6028
EV		 566 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
567 pwrst->pwrdm == core_pwrdm &&
568 state == PWRDM_POWER_OFF) {
569 pwrst->next_state = PWRDM_POWER_RET;
e16b41bf 570 pr_warn("%s: Core OFF disabled due to errata i583\n",
cc1b6028
EV		 571 __func__);
572 } else {
573 pwrst->next_state = state;
574 }
575 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
c40552bc
KH		 576 }
577}
578
68d4778c
TK		 579int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
580{
581 struct power_state *pwrst;
582
583 list_for_each_entry(pwrst, &pwrst_list, node) {
584 if (pwrst->pwrdm == pwrdm)
585 return pwrst->next_state;
586 }
587 return -EINVAL;
588}
589
590int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
591{
592 struct power_state *pwrst;
593
594 list_for_each_entry(pwrst, &pwrst_list, node) {
595 if (pwrst->pwrdm == pwrdm) {
596 pwrst->next_state = state;
597 return 0;
598 }
599 }
600 return -EINVAL;
601}
602
a23456e9 603static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
8bd22949
KH		 604{
605 struct power_state *pwrst;
606
607 if (!pwrdm->pwrsts)
608 return 0;
609
d3d381c6 610 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
8bd22949
KH		 611 if (!pwrst)
612 return -ENOMEM;
613 pwrst->pwrdm = pwrdm;
614 pwrst->next_state = PWRDM_POWER_RET;
615 list_add(&pwrst->node, &pwrst_list);
616
617 if (pwrdm_has_hdwr_sar(pwrdm))
618 pwrdm_enable_hdwr_sar(pwrdm);
619
eb6a2c75 620 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
8bd22949
KH		 621}
622
46e130d2
JP		 623/*
624 * Push functions to SRAM
625 *
626 * The minimum set of functions is pushed to SRAM for execution:
627 * - omap3_do_wfi for erratum i581 WA,
628 * - save_secure_ram_context for security extensions.
629 */
3231fc88
RN		 630void omap_push_sram_idle(void)
631{
46e130d2
JP		 632 omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
633
27d59a4a
TK		 634 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
635 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
636 save_secure_ram_context_sz);
3231fc88
RN		 637}
638
8cdfd834
NM		 639static void __init pm_errata_configure(void)
640{
c4236d2e 641 if (cpu_is_omap3630()) {
458e999e 642 pm34xx_errata |= PM_RTA_ERRATUM_i608;
c4236d2e
PDS		 643 /* Enable the l2 cache toggling in sleep logic */
644 enable_omap3630_toggle_l2_on_restore();
cc1b6028 645 if (omap_rev() < OMAP3630_REV_ES1_2)
856c3c5b
PW		 646 pm34xx_errata |= (PM_SDRC_WAKEUP_ERRATUM_i583 |
647 PM_PER_MEMORIES_ERRATUM_i582);
648 } else if (cpu_is_omap34xx()) {
649 pm34xx_errata |= PM_PER_MEMORIES_ERRATUM_i582;
c4236d2e 650 }
8cdfd834
NM		 651}
652
bbd707ac 653int __init omap3_pm_init(void)
8bd22949
KH		 654{
655 struct power_state *pwrst, *tmp;
856c3c5b 656 struct clockdomain *neon_clkdm, *mpu_clkdm, *per_clkdm, *wkup_clkdm;
8bd22949
KH		 657 int ret;
658
b02b9172
PW		 659 if (!omap3_has_io_chain_ctrl())
660 pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
661
8cdfd834
NM		 662 pm_errata_configure();
663
8bd22949
KH		 664 /* XXX prcm_setup_regs needs to be before enabling hw
665 * supervised mode for powerdomains */
666 prcm_setup_regs();
667
22f51371
TK		 668 ret = request_irq(omap_prcm_event_to_irq("wkup"),
669 _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
670
671 if (ret) {
672 pr_err("pm: Failed to request pm_wkup irq\n");
673 goto err1;
674 }
675
676 /* IO interrupt is shared with mux code */
677 ret = request_irq(omap_prcm_event_to_irq("io"),
678 _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
679 omap3_pm_init);
99b59df0 680 enable_irq(omap_prcm_event_to_irq("io"));
22f51371 681
8bd22949 682 if (ret) {
22f51371 683 pr_err("pm: Failed to request pm_io irq\n");
ce229c5d 684 goto err2;
8bd22949
KH		 685 }
686
a23456e9 687 ret = pwrdm_for_each(pwrdms_setup, NULL);
8bd22949 688 if (ret) {
98179856 689 pr_err("Failed to setup powerdomains\n");
ce229c5d 690 goto err3;
8bd22949
KH		 691 }
692
92206fd2 693 (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
8bd22949
KH		 694
695 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
696 if (mpu_pwrdm == NULL) {
98179856 697 pr_err("Failed to get mpu_pwrdm\n");
ce229c5d
MG		 698 ret = -EINVAL;
699 goto err3;
8bd22949
KH		 700 }
701
fa3c2a4f
RN		 702 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
703 per_pwrdm = pwrdm_lookup("per_pwrdm");
704 core_pwrdm = pwrdm_lookup("core_pwrdm");
705
55ed9694
PW		 706 neon_clkdm = clkdm_lookup("neon_clkdm");
707 mpu_clkdm = clkdm_lookup("mpu_clkdm");
856c3c5b
PW		 708 per_clkdm = clkdm_lookup("per_clkdm");
709 wkup_clkdm = clkdm_lookup("wkup_clkdm");
55ed9694 710
10f90ed2 711#ifdef CONFIG_SUSPEND
1416408d
PW		 712 omap_pm_suspend = omap3_pm_suspend;
713#endif
8bd22949 714
0bcd24b0 715 arm_pm_idle = omap3_pm_idle;
0343371e 716 omap3_idle_init();
8bd22949 717
458e999e
NM		 718 /*
719 * RTA is disabled during initialization as per erratum i608
720 * it is safer to disable RTA by the bootloader, but we would like
721 * to be doubly sure here and prevent any mishaps.
722 */
723 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
724 omap3630_ctrl_disable_rta();
725
856c3c5b
PW		 726 /*
727 * The UART3/4 FIFO and the sidetone memory in McBSP2/3 are
728 * not correctly reset when the PER powerdomain comes back
729 * from OFF or OSWR when the CORE powerdomain is kept active.
730 * See OMAP36xx Erratum i582 "PER Domain reset issue after
731 * Domain-OFF/OSWR Wakeup". This wakeup dependency is not a
732 * complete workaround. The kernel must also prevent the PER
733 * powerdomain from going to OSWR/OFF while the CORE
734 * powerdomain is not going to OSWR/OFF. And if PER last
735 * power state was off while CORE last power state was ON, the
736 * UART3/4 and McBSP2/3 SIDETONE devices need to run a
737 * self-test using their loopback tests; if that fails, those
738 * devices are unusable until the PER/CORE can complete a transition
739 * from ON to OSWR/OFF and then back to ON.
740 *
741 * XXX Technically this workaround is only needed if off-mode
742 * or OSWR is enabled.
743 */
744 if (IS_PM34XX_ERRATUM(PM_PER_MEMORIES_ERRATUM_i582))
745 clkdm_add_wkdep(per_clkdm, wkup_clkdm);
746
55ed9694 747 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
27d59a4a
TK		 748 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
749 omap3_secure_ram_storage =
750 kmalloc(0x803F, GFP_KERNEL);
751 if (!omap3_secure_ram_storage)
7852ec05 752 pr_err("Memory allocation failed when allocating for secure sram context\n");
9d97140b
TK		 753
754 local_irq_disable();
9d97140b
TK		 755
756 omap_dma_global_context_save();
617fcc98 757 omap3_save_secure_ram_context();
9d97140b
TK		 758 omap_dma_global_context_restore();
759
760 local_irq_enable();
27d59a4a 761 }
27d59a4a 762
9d97140b 763 omap3_save_scratchpad_contents();
8bd22949 764 return ret;
ce229c5d
MG		 765
766err3:
8bd22949
KH		 767 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
768 list_del(&pwrst->node);
769 kfree(pwrst);
770 }
ce229c5d
MG		 771 free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
772err2:
773 free_irq(omap_prcm_event_to_irq("wkup"), NULL);
774err1:
8bd22949
KH		 775 return ret;
776}
Linux kernel - Deliverables
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