projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'timer' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[deliverable/linux.git] / arch / arm / mach-omap2 / pm34xx.c
CommitLineData
8bd22949
KH		 1/*
2 * OMAP3 Power Management Routines
3 *
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 * Jouni Hogander
7 *
2f5939c3
RN		 8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
10 *
8bd22949
KH		 11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
13 *
14 * Based on pm.c for omap1
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/pm.h>
22#include <linux/suspend.h>
23#include <linux/interrupt.h>
24#include <linux/module.h>
25#include <linux/list.h>
26#include <linux/err.h>
27#include <linux/gpio.h>
c40552bc 28#include <linux/clk.h>
dccaad89 29#include <linux/delay.h>
5a0e3ad6 30#include <linux/slab.h>
5e7c58dc 31#include <trace/events/power.h>
8bd22949 32
2c74a0ce 33#include <asm/suspend.h>
9f97da78 34#include <asm/system_misc.h>
2c74a0ce 35
ce491cf8 36#include <plat/sram.h>
1540f214 37#include "clockdomain.h"
72e06d08 38#include "powerdomain.h"
61255ab9 39#include <plat/sdrc.h>
2f5939c3
RN		 40#include <plat/prcm.h>
41#include <plat/gpmc.h>
f2d11858 42#include <plat/dma.h>
8bd22949 43
4e65331c 44#include "common.h"
59fb659b 45#include "cm2xxx_3xxx.h"
8bd22949
KH		 46#include "cm-regbits-34xx.h"
47#include "prm-regbits-34xx.h"
48
59fb659b 49#include "prm2xxx_3xxx.h"
8bd22949 50#include "pm.h"
13a6fe0f 51#include "sdrc.h"
4814ced5 52#include "control.h"
13a6fe0f 53
8cdfd834
NM		 54/* pm34xx errata defined in pm.h */
55u16 pm34xx_errata;
56
8bd22949
KH		 57struct power_state {
58 struct powerdomain *pwrdm;
59 u32 next_state;
10f90ed2 60#ifdef CONFIG_SUSPEND
8bd22949 61 u32 saved_state;
10f90ed2 62#endif
8bd22949
KH		 63 struct list_head node;
64};
65
66static LIST_HEAD(pwrst_list);
67
27d59a4a 68static int (*_omap_save_secure_sram)(u32 *addr);
46e130d2 69void (*omap3_do_wfi_sram)(void);
27d59a4a 70
fa3c2a4f
RN		 71static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
72static struct powerdomain *core_pwrdm, *per_pwrdm;
c16c3f67 73static struct powerdomain *cam_pwrdm;
fa3c2a4f 74
3a7ec26b
KJ		 75static void omap3_enable_io_chain(void)
76{
77 int timeout = 0;
78
b02b9172
PW		 79 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
80 PM_WKEN);
81 /* Do a readback to assure write has been done */
82 omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
83
84 while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
85 OMAP3430_ST_IO_CHAIN_MASK)) {
86 timeout++;
87 if (timeout > 1000) {
88 pr_err("Wake up daisy chain activation failed.\n");
89 return;
3a7ec26b 90 }
b02b9172
PW		 91 omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
92 WKUP_MOD, PM_WKEN);
3a7ec26b
KJ		 93 }
94}
95
96static void omap3_disable_io_chain(void)
97{
b02b9172
PW		 98 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
99 PM_WKEN);
3a7ec26b
KJ		 100}
101
2f5939c3
RN		 102static void omap3_core_save_context(void)
103{
596efe47 104 omap3_ctrl_save_padconf();
dccaad89
TK		 105
106 /*
107 * Force write last pad into memory, as this can fail in some
83521291 108 * cases according to errata 1.157, 1.185
dccaad89
TK		 109 */
110 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
111 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
112
2f5939c3
RN		 113 /* Save the Interrupt controller context */
114 omap_intc_save_context();
115 /* Save the GPMC context */
116 omap3_gpmc_save_context();
117 /* Save the system control module context, padconf already save above*/
118 omap3_control_save_context();
f2d11858 119 omap_dma_global_context_save();
2f5939c3
RN		 120}
121
122static void omap3_core_restore_context(void)
123{
124 /* Restore the control module context, padconf restored by h/w */
125 omap3_control_restore_context();
126 /* Restore the GPMC context */
127 omap3_gpmc_restore_context();
128 /* Restore the interrupt controller context */
129 omap_intc_restore_context();
f2d11858 130 omap_dma_global_context_restore();
2f5939c3
RN		 131}
132
9d97140b
TK		 133/*
134 * FIXME: This function should be called before entering off-mode after
135 * OMAP3 secure services have been accessed. Currently it is only called
136 * once during boot sequence, but this works as we are not using secure
137 * services.
138 */
617fcc98 139static void omap3_save_secure_ram_context(void)
27d59a4a
TK		 140{
141 u32 ret;
617fcc98 142 int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
27d59a4a
TK		 143
144 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
27d59a4a
TK		 145 /*
146 * MPU next state must be set to POWER_ON temporarily,
147 * otherwise the WFI executed inside the ROM code
148 * will hang the system.
149 */
150 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
151 ret = _omap_save_secure_sram((u32 *)
152 __pa(omap3_secure_ram_storage));
617fcc98 153 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
27d59a4a
TK		 154 /* Following is for error tracking, it should not happen */
155 if (ret) {
98179856 156 pr_err("save_secure_sram() returns %08x\n", ret);
27d59a4a
TK		 157 while (1)
158 ;
159 }
160 }
161}
162
77da2d91
JH		 163/*
164 * PRCM Interrupt Handler Helper Function
165 *
166 * The purpose of this function is to clear any wake-up events latched
167 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
168 * may occur whilst attempting to clear a PM_WKST_x register and thus
169 * set another bit in this register. A while loop is used to ensure
170 * that any peripheral wake-up events occurring while attempting to
171 * clear the PM_WKST_x are detected and cleared.
172 */
22f51371 173static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
8bd22949 174{
71a80775 175 u32 wkst, fclk, iclk, clken;
77da2d91
JH		 176 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
177 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
178 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
5d805978
PW		 179 u16 grpsel_off = (regs == 3) ?
180 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
8cb0ac99 181 int c = 0;
8bd22949 182
c4d7e58f
PW		 183 wkst = omap2_prm_read_mod_reg(module, wkst_off);
184 wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
22f51371 185 wkst &= ~ignore_bits;
8bd22949 186 if (wkst) {
c4d7e58f
PW		 187 iclk = omap2_cm_read_mod_reg(module, iclk_off);
188 fclk = omap2_cm_read_mod_reg(module, fclk_off);
77da2d91 189 while (wkst) {
71a80775 190 clken = wkst;
c4d7e58f 191 omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
71a80775
VP		 192 /*
193 * For USBHOST, we don't know whether HOST1 or
194 * HOST2 woke us up, so enable both f-clocks
195 */
196 if (module == OMAP3430ES2_USBHOST_MOD)
197 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
c4d7e58f
PW		 198 omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
199 omap2_prm_write_mod_reg(wkst, module, wkst_off);
200 wkst = omap2_prm_read_mod_reg(module, wkst_off);
22f51371 201 wkst &= ~ignore_bits;
8cb0ac99 202 c++;
77da2d91 203 }
c4d7e58f
PW		 204 omap2_cm_write_mod_reg(iclk, module, iclk_off);
205 omap2_cm_write_mod_reg(fclk, module, fclk_off);
8bd22949 206 }
8cb0ac99
PW		 207
208 return c;
209}
210
22f51371 211static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
8cb0ac99
PW		 212{
213 int c;
214
22f51371
TK		 215 c = prcm_clear_mod_irqs(WKUP_MOD, 1,
216 ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
8cb0ac99 217
22f51371 218 return c ? IRQ_HANDLED : IRQ_NONE;
77da2d91 219}
8bd22949 220
22f51371 221static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
77da2d91 222{
22f51371 223 int c;
d6290a3e 224
22f51371
TK		 225 /*
226 * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
227 * these are handled in a separate handler to avoid acking
228 * IO events before parsing in mux code
229 */
230 c = prcm_clear_mod_irqs(WKUP_MOD, 1,
231 OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
232 c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
233 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
234 if (omap_rev() > OMAP3430_REV_ES1_0) {
235 c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
236 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
237 }
8bd22949 238
22f51371 239 return c ? IRQ_HANDLED : IRQ_NONE;
8bd22949
KH		 240}
241
cbe26349
RK		 242static void omap34xx_save_context(u32 *save)
243{
244 u32 val;
245
246 /* Read Auxiliary Control Register */
247 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
248 *save++ = 1;
249 *save++ = val;
250
251 /* Read L2 AUX ctrl register */
252 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
253 *save++ = 1;
254 *save++ = val;
255}
256
29cb3cd2 257static int omap34xx_do_sram_idle(unsigned long save_state)
57f277b0 258{
cbe26349 259 omap34xx_cpu_suspend(save_state);
29cb3cd2 260 return 0;
57f277b0
RN		 261}
262
99e6a4d2 263void omap_sram_idle(void)
8bd22949
KH		 264{
265 /* Variable to tell what needs to be saved and restored
266 * in omap_sram_idle*/
267 /* save_state = 0 => Nothing to save and restored */
268 /* save_state = 1 => Only L1 and logic lost */
269 /* save_state = 2 => Only L2 lost */
270 /* save_state = 3 => L1, L2 and logic lost */
fa3c2a4f
RN		 271 int save_state = 0;
272 int mpu_next_state = PWRDM_POWER_ON;
273 int per_next_state = PWRDM_POWER_ON;
274 int core_next_state = PWRDM_POWER_ON;
72e06d08 275 int per_going_off;
eeb3711b 276 int core_prev_state;
13a6fe0f 277 u32 sdrc_pwr = 0;
8bd22949 278
8bd22949
KH		 279 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
280 switch (mpu_next_state) {
fa3c2a4f 281 case PWRDM_POWER_ON:
8bd22949
KH		 282 case PWRDM_POWER_RET:
283 /* No need to save context */
284 save_state = 0;
285 break;
61255ab9
RN		 286 case PWRDM_POWER_OFF:
287 save_state = 3;
288 break;
8bd22949
KH		 289 default:
290 /* Invalid state */
98179856 291 pr_err("Invalid mpu state in sram_idle\n");
8bd22949
KH		 292 return;
293 }
fe617af7 294
fa3c2a4f
RN		 295 /* NEON control */
296 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
7139178e 297 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
fa3c2a4f 298
40742fa8 299 /* Enable IO-PAD and IO-CHAIN wakeups */
658ce97e 300 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
ecf157d0 301 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
d5c47d7e
KH		 302 if (omap3_has_io_wakeup() &&
303 (per_next_state < PWRDM_POWER_ON ||
304 core_next_state < PWRDM_POWER_ON)) {
c4d7e58f 305 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
b02b9172
PW		 306 if (omap3_has_io_chain_ctrl())
307 omap3_enable_io_chain();
40742fa8
MC		 308 }
309
ff2f8e5f
C		 310 pwrdm_pre_transition();
311
40742fa8 312 /* PER */
658ce97e 313 if (per_next_state < PWRDM_POWER_ON) {
72e06d08 314 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
72e06d08 315 omap2_gpio_prepare_for_idle(per_going_off);
658ce97e
KH		 316 }
317
318 /* CORE */
fa3c2a4f 319 if (core_next_state < PWRDM_POWER_ON) {
2f5939c3
RN		 320 if (core_next_state == PWRDM_POWER_OFF) {
321 omap3_core_save_context();
f0611a5c 322 omap3_cm_save_context();
2f5939c3 323 }
fa3c2a4f 324 }
40742fa8 325
f18cc2ff 326 omap3_intc_prepare_idle();
8bd22949 327
13a6fe0f 328 /*
30474544
PW		 329 * On EMU/HS devices ROM code restores a SRDC value
330 * from scratchpad which has automatic self refresh on timeout
331 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
332 * Hence store/restore the SDRC_POWER register here.
333 */
334 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
335 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
336 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
f265dc4c 337 core_next_state == PWRDM_POWER_OFF)
13a6fe0f 338 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
13a6fe0f 339
61255ab9 340 /*
076f2cc4
RK		 341 * omap3_arm_context is the location where some ARM context
342 * get saved. The rest is placed on the stack, and restored
343 * from there before resuming.
61255ab9 344 */
cbe26349
RK		 345 if (save_state)
346 omap34xx_save_context(omap3_arm_context);
076f2cc4 347 if (save_state == 1 || save_state == 3)
2c74a0ce 348 cpu_suspend(save_state, omap34xx_do_sram_idle);
076f2cc4
RK		 349 else
350 omap34xx_do_sram_idle(save_state);
8bd22949 351
f265dc4c 352 /* Restore normal SDRC POWER settings */
30474544
PW		 353 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
354 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
355 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
13a6fe0f
TK		 356 core_next_state == PWRDM_POWER_OFF)
357 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
358
658ce97e 359 /* CORE */
fa3c2a4f 360 if (core_next_state < PWRDM_POWER_ON) {
2f5939c3
RN		 361 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
362 if (core_prev_state == PWRDM_POWER_OFF) {
363 omap3_core_restore_context();
f0611a5c 364 omap3_cm_restore_context();
2f5939c3 365 omap3_sram_restore_context();
8a917d2f 366 omap2_sms_restore_context();
2f5939c3 367 }
658ce97e 368 if (core_next_state == PWRDM_POWER_OFF)
c4d7e58f 369 omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
658ce97e
KH		 370 OMAP3430_GR_MOD,
371 OMAP3_PRM_VOLTCTRL_OFFSET);
372 }
f18cc2ff 373 omap3_intc_resume_idle();
658ce97e 374
ff2f8e5f
C		 375 pwrdm_post_transition();
376
658ce97e 377 /* PER */
eeb3711b 378 if (per_next_state < PWRDM_POWER_ON)
43ffcd9a 379 omap2_gpio_resume_after_idle();
fe617af7 380
3a7ec26b 381 /* Disable IO-PAD and IO-CHAIN wakeup */
58a5559e
KH		 382 if (omap3_has_io_wakeup() &&
383 (per_next_state < PWRDM_POWER_ON ||
384 core_next_state < PWRDM_POWER_ON)) {
c4d7e58f
PW		 385 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
386 PM_WKEN);
b02b9172
PW		 387 if (omap3_has_io_chain_ctrl())
388 omap3_disable_io_chain();
3a7ec26b 389 }
658ce97e 390
5cd1937b 391 clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
8bd22949
KH		 392}
393
8bd22949
KH		 394static void omap3_pm_idle(void)
395{
8bd22949
KH		 396 local_fiq_disable();
397
0bcd24b0 398 if (omap_irq_pending())
8bd22949
KH		 399 goto out;
400
5e7c58dc
JP		 401 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
402 trace_cpu_idle(1, smp_processor_id());
403
8bd22949
KH		 404 omap_sram_idle();
405
5e7c58dc
JP		 406 trace_power_end(smp_processor_id());
407 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
408
8bd22949
KH		 409out:
410 local_fiq_enable();
8bd22949
KH		 411}
412
10f90ed2 413#ifdef CONFIG_SUSPEND
8bd22949
KH		 414static int omap3_pm_suspend(void)
415{
416 struct power_state *pwrst;
417 int state, ret = 0;
418
419 /* Read current next_pwrsts */
420 list_for_each_entry(pwrst, &pwrst_list, node)
421 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
422 /* Set ones wanted by suspend */
423 list_for_each_entry(pwrst, &pwrst_list, node) {
eb6a2c75 424 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
8bd22949
KH		 425 goto restore;
426 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
427 goto restore;
428 }
429
2bbe3af3
TK		 430 omap3_intc_suspend();
431
8bd22949
KH		 432 omap_sram_idle();
433
434restore:
435 /* Restore next_pwrsts */
436 list_for_each_entry(pwrst, &pwrst_list, node) {
8bd22949
KH		 437 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
438 if (state > pwrst->next_state) {
98179856
MG		 439 pr_info("Powerdomain (%s) didn't enter "
440 "target state %d\n",
8bd22949
KH		 441 pwrst->pwrdm->name, pwrst->next_state);
442 ret = -1;
443 }
eb6a2c75 444 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
8bd22949
KH		 445 }
446 if (ret)
98179856 447 pr_err("Could not enter target state in pm_suspend\n");
8bd22949 448 else
98179856 449 pr_info("Successfully put all powerdomains to target state\n");
8bd22949
KH		 450
451 return ret;
452}
453
10f90ed2 454#endif /* CONFIG_SUSPEND */
8bd22949 455
1155e426
KH		 456
457/**
458 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
459 * retention
460 *
461 * In cases where IVA2 is activated by bootcode, it may prevent
462 * full-chip retention or off-mode because it is not idle. This
463 * function forces the IVA2 into idle state so it can go
464 * into retention/off and thus allow full-chip retention/off.
465 *
466 **/
467static void __init omap3_iva_idle(void)
468{
469 /* ensure IVA2 clock is disabled */
c4d7e58f 470 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
1155e426
KH		 471
472 /* if no clock activity, nothing else to do */
c4d7e58f 473 if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
1155e426
KH		 474 OMAP3430_CLKACTIVITY_IVA2_MASK))
475 return;
476
477 /* Reset IVA2 */
c4d7e58f 478 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
2bc4ef71
PW		 479 OMAP3430_RST2_IVA2_MASK |
480 OMAP3430_RST3_IVA2_MASK,
37903009 481 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
1155e426
KH		 482
483 /* Enable IVA2 clock */
c4d7e58f 484 omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
1155e426
KH		 485 OMAP3430_IVA2_MOD, CM_FCLKEN);
486
487 /* Set IVA2 boot mode to 'idle' */
488 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
489 OMAP343X_CONTROL_IVA2_BOOTMOD);
490
491 /* Un-reset IVA2 */
c4d7e58f 492 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
1155e426
KH		 493
494 /* Disable IVA2 clock */
c4d7e58f 495 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
1155e426
KH		 496
497 /* Reset IVA2 */
c4d7e58f 498 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
2bc4ef71
PW		 499 OMAP3430_RST2_IVA2_MASK |
500 OMAP3430_RST3_IVA2_MASK,
37903009 501 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
1155e426
KH		 502}
503
8111b221 504static void __init omap3_d2d_idle(void)
8bd22949 505{
8111b221
KH		 506 u16 mask, padconf;
507
508 /* In a stand alone OMAP3430 where there is not a stacked
509 * modem for the D2D Idle Ack and D2D MStandby must be pulled
510 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
511 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
512 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
513 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
514 padconf |= mask;
515 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
516
517 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
518 padconf |= mask;
519 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
520
8bd22949 521 /* reset modem */
c4d7e58f 522 omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
2bc4ef71 523 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
37903009 524 CORE_MOD, OMAP2_RM_RSTCTRL);
c4d7e58f 525 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
8111b221 526}
8bd22949 527
8111b221
KH		 528static void __init prcm_setup_regs(void)
529{
e5863689
G		 530 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
531 OMAP3630_EN_UART4_MASK : 0;
532 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
533 OMAP3630_GRPSEL_UART4_MASK : 0;
534
4ef70c06 535 /* XXX This should be handled by hwmod code or SCM init code */
2fd0f75c 536 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
b296c811 537
8bd22949
KH		 538 /*
539 * Enable control of expternal oscillator through
540 * sys_clkreq. In the long run clock framework should
541 * take care of this.
542 */
c4d7e58f 543 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
8bd22949
KH		 544 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
545 OMAP3430_GR_MOD,
546 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
547
548 /* setup wakup source */
c4d7e58f 549 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
2fd0f75c 550 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
8bd22949
KH		 551 WKUP_MOD, PM_WKEN);
552 /* No need to write EN_IO, that is always enabled */
c4d7e58f 553 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
275f675c
PW		 554 OMAP3430_GRPSEL_GPT1_MASK |
555 OMAP3430_GRPSEL_GPT12_MASK,
8bd22949 556 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
1155e426 557
b92c5721 558 /* Enable PM_WKEN to support DSS LPR */
c4d7e58f 559 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
b92c5721
SV		 560 OMAP3430_DSS_MOD, PM_WKEN);
561
b427f92f 562 /* Enable wakeups in PER */
c4d7e58f 563 omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
e5863689 564 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
2fd0f75c
PW		 565 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
566 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
567 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
568 OMAP3430_EN_MCBSP4_MASK,
b427f92f 569 OMAP3430_PER_MOD, PM_WKEN);
eb350f74 570 /* and allow them to wake up MPU */
c4d7e58f 571 omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
e5863689 572 OMAP3430_GRPSEL_GPIO2_MASK |
275f675c
PW		 573 OMAP3430_GRPSEL_GPIO3_MASK |
574 OMAP3430_GRPSEL_GPIO4_MASK |
575 OMAP3430_GRPSEL_GPIO5_MASK |
576 OMAP3430_GRPSEL_GPIO6_MASK |
577 OMAP3430_GRPSEL_UART3_MASK |
578 OMAP3430_GRPSEL_MCBSP2_MASK |
579 OMAP3430_GRPSEL_MCBSP3_MASK |
580 OMAP3430_GRPSEL_MCBSP4_MASK,
eb350f74
KH		 581 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
582
d3fd3290 583 /* Don't attach IVA interrupts */
a819c4f1
MG		 584 if (omap3_has_iva()) {
585 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
586 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
587 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
588 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
589 OMAP3430_PM_IVAGRPSEL);
590 }
d3fd3290 591
b1340d17 592 /* Clear any pending 'reset' flags */
c4d7e58f
PW		 593 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
594 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
595 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
596 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
597 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
598 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
599 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
b1340d17 600
014c46db 601 /* Clear any pending PRCM interrupts */
c4d7e58f 602 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
014c46db 603
a819c4f1
MG		 604 if (omap3_has_iva())
605 omap3_iva_idle();
606
8111b221 607 omap3_d2d_idle();
8bd22949
KH		 608}
609
c40552bc
KH		 610void omap3_pm_off_mode_enable(int enable)
611{
612 struct power_state *pwrst;
613 u32 state;
614
615 if (enable)
616 state = PWRDM_POWER_OFF;
617 else
618 state = PWRDM_POWER_RET;
619
620 list_for_each_entry(pwrst, &pwrst_list, node) {
cc1b6028
EV		 621 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
622 pwrst->pwrdm == core_pwrdm &&
623 state == PWRDM_POWER_OFF) {
624 pwrst->next_state = PWRDM_POWER_RET;
e16b41bf 625 pr_warn("%s: Core OFF disabled due to errata i583\n",
cc1b6028
EV		 626 __func__);
627 } else {
628 pwrst->next_state = state;
629 }
630 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
c40552bc
KH		 631 }
632}
633
68d4778c
TK		 634int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
635{
636 struct power_state *pwrst;
637
638 list_for_each_entry(pwrst, &pwrst_list, node) {
639 if (pwrst->pwrdm == pwrdm)
640 return pwrst->next_state;
641 }
642 return -EINVAL;
643}
644
645int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
646{
647 struct power_state *pwrst;
648
649 list_for_each_entry(pwrst, &pwrst_list, node) {
650 if (pwrst->pwrdm == pwrdm) {
651 pwrst->next_state = state;
652 return 0;
653 }
654 }
655 return -EINVAL;
656}
657
a23456e9 658static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
8bd22949
KH		 659{
660 struct power_state *pwrst;
661
662 if (!pwrdm->pwrsts)
663 return 0;
664
d3d381c6 665 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
8bd22949
KH		 666 if (!pwrst)
667 return -ENOMEM;
668 pwrst->pwrdm = pwrdm;
669 pwrst->next_state = PWRDM_POWER_RET;
670 list_add(&pwrst->node, &pwrst_list);
671
672 if (pwrdm_has_hdwr_sar(pwrdm))
673 pwrdm_enable_hdwr_sar(pwrdm);
674
eb6a2c75 675 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
8bd22949
KH		 676}
677
46e130d2
JP		 678/*
679 * Push functions to SRAM
680 *
681 * The minimum set of functions is pushed to SRAM for execution:
682 * - omap3_do_wfi for erratum i581 WA,
683 * - save_secure_ram_context for security extensions.
684 */
3231fc88
RN		 685void omap_push_sram_idle(void)
686{
46e130d2
JP		 687 omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
688
27d59a4a
TK		 689 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
690 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
691 save_secure_ram_context_sz);
3231fc88
RN		 692}
693
8cdfd834
NM		 694static void __init pm_errata_configure(void)
695{
c4236d2e 696 if (cpu_is_omap3630()) {
458e999e 697 pm34xx_errata |= PM_RTA_ERRATUM_i608;
c4236d2e
PDS		 698 /* Enable the l2 cache toggling in sleep logic */
699 enable_omap3630_toggle_l2_on_restore();
cc1b6028
EV		 700 if (omap_rev() < OMAP3630_REV_ES1_2)
701 pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
c4236d2e 702 }
8cdfd834
NM		 703}
704
bbd707ac 705int __init omap3_pm_init(void)
8bd22949
KH		 706{
707 struct power_state *pwrst, *tmp;
eeb3711b 708 struct clockdomain *neon_clkdm, *mpu_clkdm;
8bd22949
KH		 709 int ret;
710
b02b9172
PW		 711 if (!omap3_has_io_chain_ctrl())
712 pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
713
8cdfd834
NM		 714 pm_errata_configure();
715
8bd22949
KH		 716 /* XXX prcm_setup_regs needs to be before enabling hw
717 * supervised mode for powerdomains */
718 prcm_setup_regs();
719
22f51371
TK		 720 ret = request_irq(omap_prcm_event_to_irq("wkup"),
721 _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
722
723 if (ret) {
724 pr_err("pm: Failed to request pm_wkup irq\n");
725 goto err1;
726 }
727
728 /* IO interrupt is shared with mux code */
729 ret = request_irq(omap_prcm_event_to_irq("io"),
730 _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
731 omap3_pm_init);
99b59df0 732 enable_irq(omap_prcm_event_to_irq("io"));
22f51371 733
8bd22949 734 if (ret) {
22f51371 735 pr_err("pm: Failed to request pm_io irq\n");
ce229c5d 736 goto err2;
8bd22949
KH		 737 }
738
a23456e9 739 ret = pwrdm_for_each(pwrdms_setup, NULL);
8bd22949 740 if (ret) {
98179856 741 pr_err("Failed to setup powerdomains\n");
ce229c5d 742 goto err3;
8bd22949
KH		 743 }
744
92206fd2 745 (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
8bd22949
KH		 746
747 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
748 if (mpu_pwrdm == NULL) {
98179856 749 pr_err("Failed to get mpu_pwrdm\n");
ce229c5d
MG		 750 ret = -EINVAL;
751 goto err3;
8bd22949
KH		 752 }
753
fa3c2a4f
RN		 754 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
755 per_pwrdm = pwrdm_lookup("per_pwrdm");
756 core_pwrdm = pwrdm_lookup("core_pwrdm");
c16c3f67 757 cam_pwrdm = pwrdm_lookup("cam_pwrdm");
fa3c2a4f 758
55ed9694
PW		 759 neon_clkdm = clkdm_lookup("neon_clkdm");
760 mpu_clkdm = clkdm_lookup("mpu_clkdm");
55ed9694 761
10f90ed2 762#ifdef CONFIG_SUSPEND
1416408d
PW		 763 omap_pm_suspend = omap3_pm_suspend;
764#endif
8bd22949 765
0bcd24b0 766 arm_pm_idle = omap3_pm_idle;
0343371e 767 omap3_idle_init();
8bd22949 768
458e999e
NM		 769 /*
770 * RTA is disabled during initialization as per erratum i608
771 * it is safer to disable RTA by the bootloader, but we would like
772 * to be doubly sure here and prevent any mishaps.
773 */
774 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
775 omap3630_ctrl_disable_rta();
776
55ed9694 777 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
27d59a4a
TK		 778 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
779 omap3_secure_ram_storage =
780 kmalloc(0x803F, GFP_KERNEL);
781 if (!omap3_secure_ram_storage)
98179856
MG		 782 pr_err("Memory allocation failed when "
783 "allocating for secure sram context\n");
9d97140b
TK		 784
785 local_irq_disable();
786 local_fiq_disable();
787
788 omap_dma_global_context_save();
617fcc98 789 omap3_save_secure_ram_context();
9d97140b
TK		 790 omap_dma_global_context_restore();
791
792 local_irq_enable();
793 local_fiq_enable();
27d59a4a 794 }
27d59a4a 795
9d97140b 796 omap3_save_scratchpad_contents();
8bd22949 797 return ret;
ce229c5d
MG		 798
799err3:
8bd22949
KH		 800 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
801 list_del(&pwrst->node);
802 kfree(pwrst);
803 }
ce229c5d
MG		 804 free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
805err2:
806 free_irq(omap_prcm_event_to_irq("wkup"), NULL);
807err1:
8bd22949
KH		 808 return ret;
809}
Linux kernel - Deliverables
This page took 0.240813 seconds and 5 git commands to generate.