Commit | Line | Data |
---|---|---|
8bd22949 KH |
1 | /* |
2 | * OMAP3 Power Management Routines | |
3 | * | |
4 | * Copyright (C) 2006-2008 Nokia Corporation | |
5 | * Tony Lindgren <tony@atomide.com> | |
6 | * Jouni Hogander | |
7 | * | |
2f5939c3 RN |
8 | * Copyright (C) 2007 Texas Instruments, Inc. |
9 | * Rajendra Nayak <rnayak@ti.com> | |
10 | * | |
8bd22949 KH |
11 | * Copyright (C) 2005 Texas Instruments, Inc. |
12 | * Richard Woodruff <r-woodruff2@ti.com> | |
13 | * | |
14 | * Based on pm.c for omap1 | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/pm.h> | |
22 | #include <linux/suspend.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/gpio.h> | |
c40552bc | 28 | #include <linux/clk.h> |
dccaad89 | 29 | #include <linux/delay.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
5e7c58dc | 31 | #include <trace/events/power.h> |
8bd22949 | 32 | |
2c74a0ce | 33 | #include <asm/suspend.h> |
9f97da78 | 34 | #include <asm/system_misc.h> |
2c74a0ce | 35 | |
ce491cf8 | 36 | #include <plat/sram.h> |
1540f214 | 37 | #include "clockdomain.h" |
72e06d08 | 38 | #include "powerdomain.h" |
61255ab9 | 39 | #include <plat/sdrc.h> |
2f5939c3 RN |
40 | #include <plat/prcm.h> |
41 | #include <plat/gpmc.h> | |
f2d11858 | 42 | #include <plat/dma.h> |
8bd22949 | 43 | |
4e65331c | 44 | #include "common.h" |
59fb659b | 45 | #include "cm2xxx_3xxx.h" |
8bd22949 KH |
46 | #include "cm-regbits-34xx.h" |
47 | #include "prm-regbits-34xx.h" | |
48 | ||
59fb659b | 49 | #include "prm2xxx_3xxx.h" |
8bd22949 | 50 | #include "pm.h" |
13a6fe0f | 51 | #include "sdrc.h" |
4814ced5 | 52 | #include "control.h" |
13a6fe0f | 53 | |
e83df17f KH |
54 | #ifdef CONFIG_SUSPEND |
55 | static suspend_state_t suspend_state = PM_SUSPEND_ON; | |
e83df17f KH |
56 | #endif |
57 | ||
8cdfd834 NM |
58 | /* pm34xx errata defined in pm.h */ |
59 | u16 pm34xx_errata; | |
60 | ||
8bd22949 KH |
61 | struct power_state { |
62 | struct powerdomain *pwrdm; | |
63 | u32 next_state; | |
10f90ed2 | 64 | #ifdef CONFIG_SUSPEND |
8bd22949 | 65 | u32 saved_state; |
10f90ed2 | 66 | #endif |
8bd22949 KH |
67 | struct list_head node; |
68 | }; | |
69 | ||
70 | static LIST_HEAD(pwrst_list); | |
71 | ||
27d59a4a | 72 | static int (*_omap_save_secure_sram)(u32 *addr); |
46e130d2 | 73 | void (*omap3_do_wfi_sram)(void); |
27d59a4a | 74 | |
fa3c2a4f RN |
75 | static struct powerdomain *mpu_pwrdm, *neon_pwrdm; |
76 | static struct powerdomain *core_pwrdm, *per_pwrdm; | |
c16c3f67 | 77 | static struct powerdomain *cam_pwrdm; |
fa3c2a4f | 78 | |
2f5939c3 RN |
79 | static inline void omap3_per_save_context(void) |
80 | { | |
81 | omap_gpio_save_context(); | |
82 | } | |
83 | ||
84 | static inline void omap3_per_restore_context(void) | |
85 | { | |
86 | omap_gpio_restore_context(); | |
87 | } | |
88 | ||
3a7ec26b KJ |
89 | static void omap3_enable_io_chain(void) |
90 | { | |
91 | int timeout = 0; | |
92 | ||
b02b9172 PW |
93 | omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, |
94 | PM_WKEN); | |
95 | /* Do a readback to assure write has been done */ | |
96 | omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN); | |
97 | ||
98 | while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) & | |
99 | OMAP3430_ST_IO_CHAIN_MASK)) { | |
100 | timeout++; | |
101 | if (timeout > 1000) { | |
102 | pr_err("Wake up daisy chain activation failed.\n"); | |
103 | return; | |
3a7ec26b | 104 | } |
b02b9172 PW |
105 | omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, |
106 | WKUP_MOD, PM_WKEN); | |
3a7ec26b KJ |
107 | } |
108 | } | |
109 | ||
110 | static void omap3_disable_io_chain(void) | |
111 | { | |
b02b9172 PW |
112 | omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, |
113 | PM_WKEN); | |
3a7ec26b KJ |
114 | } |
115 | ||
2f5939c3 RN |
116 | static void omap3_core_save_context(void) |
117 | { | |
596efe47 | 118 | omap3_ctrl_save_padconf(); |
dccaad89 TK |
119 | |
120 | /* | |
121 | * Force write last pad into memory, as this can fail in some | |
83521291 | 122 | * cases according to errata 1.157, 1.185 |
dccaad89 TK |
123 | */ |
124 | omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14), | |
125 | OMAP343X_CONTROL_MEM_WKUP + 0x2a0); | |
126 | ||
2f5939c3 RN |
127 | /* Save the Interrupt controller context */ |
128 | omap_intc_save_context(); | |
129 | /* Save the GPMC context */ | |
130 | omap3_gpmc_save_context(); | |
131 | /* Save the system control module context, padconf already save above*/ | |
132 | omap3_control_save_context(); | |
f2d11858 | 133 | omap_dma_global_context_save(); |
2f5939c3 RN |
134 | } |
135 | ||
136 | static void omap3_core_restore_context(void) | |
137 | { | |
138 | /* Restore the control module context, padconf restored by h/w */ | |
139 | omap3_control_restore_context(); | |
140 | /* Restore the GPMC context */ | |
141 | omap3_gpmc_restore_context(); | |
142 | /* Restore the interrupt controller context */ | |
143 | omap_intc_restore_context(); | |
f2d11858 | 144 | omap_dma_global_context_restore(); |
2f5939c3 RN |
145 | } |
146 | ||
9d97140b TK |
147 | /* |
148 | * FIXME: This function should be called before entering off-mode after | |
149 | * OMAP3 secure services have been accessed. Currently it is only called | |
150 | * once during boot sequence, but this works as we are not using secure | |
151 | * services. | |
152 | */ | |
617fcc98 | 153 | static void omap3_save_secure_ram_context(void) |
27d59a4a TK |
154 | { |
155 | u32 ret; | |
617fcc98 | 156 | int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); |
27d59a4a TK |
157 | |
158 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { | |
27d59a4a TK |
159 | /* |
160 | * MPU next state must be set to POWER_ON temporarily, | |
161 | * otherwise the WFI executed inside the ROM code | |
162 | * will hang the system. | |
163 | */ | |
164 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); | |
165 | ret = _omap_save_secure_sram((u32 *) | |
166 | __pa(omap3_secure_ram_storage)); | |
617fcc98 | 167 | pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state); |
27d59a4a TK |
168 | /* Following is for error tracking, it should not happen */ |
169 | if (ret) { | |
170 | printk(KERN_ERR "save_secure_sram() returns %08x\n", | |
171 | ret); | |
172 | while (1) | |
173 | ; | |
174 | } | |
175 | } | |
176 | } | |
177 | ||
77da2d91 JH |
178 | /* |
179 | * PRCM Interrupt Handler Helper Function | |
180 | * | |
181 | * The purpose of this function is to clear any wake-up events latched | |
182 | * in the PRCM PM_WKST_x registers. It is possible that a wake-up event | |
183 | * may occur whilst attempting to clear a PM_WKST_x register and thus | |
184 | * set another bit in this register. A while loop is used to ensure | |
185 | * that any peripheral wake-up events occurring while attempting to | |
186 | * clear the PM_WKST_x are detected and cleared. | |
187 | */ | |
22f51371 | 188 | static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits) |
8bd22949 | 189 | { |
71a80775 | 190 | u32 wkst, fclk, iclk, clken; |
77da2d91 JH |
191 | u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; |
192 | u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; | |
193 | u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; | |
5d805978 PW |
194 | u16 grpsel_off = (regs == 3) ? |
195 | OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; | |
8cb0ac99 | 196 | int c = 0; |
8bd22949 | 197 | |
c4d7e58f PW |
198 | wkst = omap2_prm_read_mod_reg(module, wkst_off); |
199 | wkst &= omap2_prm_read_mod_reg(module, grpsel_off); | |
22f51371 | 200 | wkst &= ~ignore_bits; |
8bd22949 | 201 | if (wkst) { |
c4d7e58f PW |
202 | iclk = omap2_cm_read_mod_reg(module, iclk_off); |
203 | fclk = omap2_cm_read_mod_reg(module, fclk_off); | |
77da2d91 | 204 | while (wkst) { |
71a80775 | 205 | clken = wkst; |
c4d7e58f | 206 | omap2_cm_set_mod_reg_bits(clken, module, iclk_off); |
71a80775 VP |
207 | /* |
208 | * For USBHOST, we don't know whether HOST1 or | |
209 | * HOST2 woke us up, so enable both f-clocks | |
210 | */ | |
211 | if (module == OMAP3430ES2_USBHOST_MOD) | |
212 | clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; | |
c4d7e58f PW |
213 | omap2_cm_set_mod_reg_bits(clken, module, fclk_off); |
214 | omap2_prm_write_mod_reg(wkst, module, wkst_off); | |
215 | wkst = omap2_prm_read_mod_reg(module, wkst_off); | |
22f51371 | 216 | wkst &= ~ignore_bits; |
8cb0ac99 | 217 | c++; |
77da2d91 | 218 | } |
c4d7e58f PW |
219 | omap2_cm_write_mod_reg(iclk, module, iclk_off); |
220 | omap2_cm_write_mod_reg(fclk, module, fclk_off); | |
8bd22949 | 221 | } |
8cb0ac99 PW |
222 | |
223 | return c; | |
224 | } | |
225 | ||
22f51371 | 226 | static irqreturn_t _prcm_int_handle_io(int irq, void *unused) |
8cb0ac99 PW |
227 | { |
228 | int c; | |
229 | ||
22f51371 TK |
230 | c = prcm_clear_mod_irqs(WKUP_MOD, 1, |
231 | ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK)); | |
8cb0ac99 | 232 | |
22f51371 | 233 | return c ? IRQ_HANDLED : IRQ_NONE; |
77da2d91 | 234 | } |
8bd22949 | 235 | |
22f51371 | 236 | static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused) |
77da2d91 | 237 | { |
22f51371 | 238 | int c; |
d6290a3e | 239 | |
22f51371 TK |
240 | /* |
241 | * Clear all except ST_IO and ST_IO_CHAIN for wkup module, | |
242 | * these are handled in a separate handler to avoid acking | |
243 | * IO events before parsing in mux code | |
244 | */ | |
245 | c = prcm_clear_mod_irqs(WKUP_MOD, 1, | |
246 | OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK); | |
247 | c += prcm_clear_mod_irqs(CORE_MOD, 1, 0); | |
248 | c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0); | |
249 | if (omap_rev() > OMAP3430_REV_ES1_0) { | |
250 | c += prcm_clear_mod_irqs(CORE_MOD, 3, 0); | |
251 | c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0); | |
252 | } | |
8bd22949 | 253 | |
22f51371 | 254 | return c ? IRQ_HANDLED : IRQ_NONE; |
8bd22949 KH |
255 | } |
256 | ||
cbe26349 RK |
257 | static void omap34xx_save_context(u32 *save) |
258 | { | |
259 | u32 val; | |
260 | ||
261 | /* Read Auxiliary Control Register */ | |
262 | asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val)); | |
263 | *save++ = 1; | |
264 | *save++ = val; | |
265 | ||
266 | /* Read L2 AUX ctrl register */ | |
267 | asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); | |
268 | *save++ = 1; | |
269 | *save++ = val; | |
270 | } | |
271 | ||
29cb3cd2 | 272 | static int omap34xx_do_sram_idle(unsigned long save_state) |
57f277b0 | 273 | { |
cbe26349 | 274 | omap34xx_cpu_suspend(save_state); |
29cb3cd2 | 275 | return 0; |
57f277b0 RN |
276 | } |
277 | ||
99e6a4d2 | 278 | void omap_sram_idle(void) |
8bd22949 KH |
279 | { |
280 | /* Variable to tell what needs to be saved and restored | |
281 | * in omap_sram_idle*/ | |
282 | /* save_state = 0 => Nothing to save and restored */ | |
283 | /* save_state = 1 => Only L1 and logic lost */ | |
284 | /* save_state = 2 => Only L2 lost */ | |
285 | /* save_state = 3 => L1, L2 and logic lost */ | |
fa3c2a4f RN |
286 | int save_state = 0; |
287 | int mpu_next_state = PWRDM_POWER_ON; | |
288 | int per_next_state = PWRDM_POWER_ON; | |
289 | int core_next_state = PWRDM_POWER_ON; | |
72e06d08 | 290 | int per_going_off; |
2f5939c3 | 291 | int core_prev_state, per_prev_state; |
13a6fe0f | 292 | u32 sdrc_pwr = 0; |
8bd22949 | 293 | |
fa3c2a4f RN |
294 | pwrdm_clear_all_prev_pwrst(mpu_pwrdm); |
295 | pwrdm_clear_all_prev_pwrst(neon_pwrdm); | |
296 | pwrdm_clear_all_prev_pwrst(core_pwrdm); | |
297 | pwrdm_clear_all_prev_pwrst(per_pwrdm); | |
298 | ||
8bd22949 KH |
299 | mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); |
300 | switch (mpu_next_state) { | |
fa3c2a4f | 301 | case PWRDM_POWER_ON: |
8bd22949 KH |
302 | case PWRDM_POWER_RET: |
303 | /* No need to save context */ | |
304 | save_state = 0; | |
305 | break; | |
61255ab9 RN |
306 | case PWRDM_POWER_OFF: |
307 | save_state = 3; | |
308 | break; | |
8bd22949 KH |
309 | default: |
310 | /* Invalid state */ | |
311 | printk(KERN_ERR "Invalid mpu state in sram_idle\n"); | |
312 | return; | |
313 | } | |
fe617af7 | 314 | |
fa3c2a4f RN |
315 | /* NEON control */ |
316 | if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) | |
7139178e | 317 | pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state); |
fa3c2a4f | 318 | |
40742fa8 | 319 | /* Enable IO-PAD and IO-CHAIN wakeups */ |
658ce97e | 320 | per_next_state = pwrdm_read_next_pwrst(per_pwrdm); |
ecf157d0 | 321 | core_next_state = pwrdm_read_next_pwrst(core_pwrdm); |
d5c47d7e KH |
322 | if (omap3_has_io_wakeup() && |
323 | (per_next_state < PWRDM_POWER_ON || | |
324 | core_next_state < PWRDM_POWER_ON)) { | |
c4d7e58f | 325 | omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); |
b02b9172 PW |
326 | if (omap3_has_io_chain_ctrl()) |
327 | omap3_enable_io_chain(); | |
40742fa8 MC |
328 | } |
329 | ||
ff2f8e5f C |
330 | pwrdm_pre_transition(); |
331 | ||
40742fa8 | 332 | /* PER */ |
658ce97e | 333 | if (per_next_state < PWRDM_POWER_ON) { |
72e06d08 | 334 | per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; |
72e06d08 | 335 | omap2_gpio_prepare_for_idle(per_going_off); |
e7410cf7 | 336 | if (per_next_state == PWRDM_POWER_OFF) |
ecf157d0 | 337 | omap3_per_save_context(); |
658ce97e KH |
338 | } |
339 | ||
340 | /* CORE */ | |
fa3c2a4f | 341 | if (core_next_state < PWRDM_POWER_ON) { |
2f5939c3 RN |
342 | if (core_next_state == PWRDM_POWER_OFF) { |
343 | omap3_core_save_context(); | |
f0611a5c | 344 | omap3_cm_save_context(); |
2f5939c3 | 345 | } |
fa3c2a4f | 346 | } |
40742fa8 | 347 | |
f18cc2ff | 348 | omap3_intc_prepare_idle(); |
8bd22949 | 349 | |
13a6fe0f | 350 | /* |
30474544 PW |
351 | * On EMU/HS devices ROM code restores a SRDC value |
352 | * from scratchpad which has automatic self refresh on timeout | |
353 | * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443. | |
354 | * Hence store/restore the SDRC_POWER register here. | |
355 | */ | |
356 | if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && | |
357 | (omap_type() == OMAP2_DEVICE_TYPE_EMU || | |
358 | omap_type() == OMAP2_DEVICE_TYPE_SEC) && | |
f265dc4c | 359 | core_next_state == PWRDM_POWER_OFF) |
13a6fe0f | 360 | sdrc_pwr = sdrc_read_reg(SDRC_POWER); |
13a6fe0f | 361 | |
61255ab9 | 362 | /* |
076f2cc4 RK |
363 | * omap3_arm_context is the location where some ARM context |
364 | * get saved. The rest is placed on the stack, and restored | |
365 | * from there before resuming. | |
61255ab9 | 366 | */ |
cbe26349 RK |
367 | if (save_state) |
368 | omap34xx_save_context(omap3_arm_context); | |
076f2cc4 | 369 | if (save_state == 1 || save_state == 3) |
2c74a0ce | 370 | cpu_suspend(save_state, omap34xx_do_sram_idle); |
076f2cc4 RK |
371 | else |
372 | omap34xx_do_sram_idle(save_state); | |
8bd22949 | 373 | |
f265dc4c | 374 | /* Restore normal SDRC POWER settings */ |
30474544 PW |
375 | if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 && |
376 | (omap_type() == OMAP2_DEVICE_TYPE_EMU || | |
377 | omap_type() == OMAP2_DEVICE_TYPE_SEC) && | |
13a6fe0f TK |
378 | core_next_state == PWRDM_POWER_OFF) |
379 | sdrc_write_reg(sdrc_pwr, SDRC_POWER); | |
380 | ||
658ce97e | 381 | /* CORE */ |
fa3c2a4f | 382 | if (core_next_state < PWRDM_POWER_ON) { |
2f5939c3 RN |
383 | core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); |
384 | if (core_prev_state == PWRDM_POWER_OFF) { | |
385 | omap3_core_restore_context(); | |
f0611a5c | 386 | omap3_cm_restore_context(); |
2f5939c3 | 387 | omap3_sram_restore_context(); |
8a917d2f | 388 | omap2_sms_restore_context(); |
2f5939c3 | 389 | } |
658ce97e | 390 | if (core_next_state == PWRDM_POWER_OFF) |
c4d7e58f | 391 | omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, |
658ce97e KH |
392 | OMAP3430_GR_MOD, |
393 | OMAP3_PRM_VOLTCTRL_OFFSET); | |
394 | } | |
f18cc2ff | 395 | omap3_intc_resume_idle(); |
658ce97e | 396 | |
ff2f8e5f C |
397 | pwrdm_post_transition(); |
398 | ||
658ce97e KH |
399 | /* PER */ |
400 | if (per_next_state < PWRDM_POWER_ON) { | |
401 | per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); | |
43ffcd9a KH |
402 | omap2_gpio_resume_after_idle(); |
403 | if (per_prev_state == PWRDM_POWER_OFF) | |
658ce97e | 404 | omap3_per_restore_context(); |
fa3c2a4f | 405 | } |
fe617af7 | 406 | |
3a7ec26b | 407 | /* Disable IO-PAD and IO-CHAIN wakeup */ |
58a5559e KH |
408 | if (omap3_has_io_wakeup() && |
409 | (per_next_state < PWRDM_POWER_ON || | |
410 | core_next_state < PWRDM_POWER_ON)) { | |
c4d7e58f PW |
411 | omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, |
412 | PM_WKEN); | |
b02b9172 PW |
413 | if (omap3_has_io_chain_ctrl()) |
414 | omap3_disable_io_chain(); | |
3a7ec26b | 415 | } |
658ce97e | 416 | |
5cd1937b | 417 | clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); |
8bd22949 KH |
418 | } |
419 | ||
8bd22949 KH |
420 | static void omap3_pm_idle(void) |
421 | { | |
422 | local_irq_disable(); | |
423 | local_fiq_disable(); | |
424 | ||
cf22854c | 425 | if (omap_irq_pending() || need_resched()) |
8bd22949 KH |
426 | goto out; |
427 | ||
5e7c58dc JP |
428 | trace_power_start(POWER_CSTATE, 1, smp_processor_id()); |
429 | trace_cpu_idle(1, smp_processor_id()); | |
430 | ||
8bd22949 KH |
431 | omap_sram_idle(); |
432 | ||
5e7c58dc JP |
433 | trace_power_end(smp_processor_id()); |
434 | trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id()); | |
435 | ||
8bd22949 KH |
436 | out: |
437 | local_fiq_enable(); | |
438 | local_irq_enable(); | |
439 | } | |
440 | ||
10f90ed2 | 441 | #ifdef CONFIG_SUSPEND |
8bd22949 KH |
442 | static int omap3_pm_suspend(void) |
443 | { | |
444 | struct power_state *pwrst; | |
445 | int state, ret = 0; | |
446 | ||
447 | /* Read current next_pwrsts */ | |
448 | list_for_each_entry(pwrst, &pwrst_list, node) | |
449 | pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); | |
450 | /* Set ones wanted by suspend */ | |
451 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
eb6a2c75 | 452 | if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) |
8bd22949 KH |
453 | goto restore; |
454 | if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) | |
455 | goto restore; | |
456 | } | |
457 | ||
2bbe3af3 TK |
458 | omap3_intc_suspend(); |
459 | ||
8bd22949 KH |
460 | omap_sram_idle(); |
461 | ||
462 | restore: | |
463 | /* Restore next_pwrsts */ | |
464 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
8bd22949 KH |
465 | state = pwrdm_read_prev_pwrst(pwrst->pwrdm); |
466 | if (state > pwrst->next_state) { | |
467 | printk(KERN_INFO "Powerdomain (%s) didn't enter " | |
468 | "target state %d\n", | |
469 | pwrst->pwrdm->name, pwrst->next_state); | |
470 | ret = -1; | |
471 | } | |
eb6a2c75 | 472 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); |
8bd22949 KH |
473 | } |
474 | if (ret) | |
475 | printk(KERN_ERR "Could not enter target state in pm_suspend\n"); | |
476 | else | |
477 | printk(KERN_INFO "Successfully put all powerdomains " | |
478 | "to target state\n"); | |
479 | ||
480 | return ret; | |
481 | } | |
482 | ||
2466211e | 483 | static int omap3_pm_enter(suspend_state_t unused) |
8bd22949 KH |
484 | { |
485 | int ret = 0; | |
486 | ||
2466211e | 487 | switch (suspend_state) { |
8bd22949 KH |
488 | case PM_SUSPEND_STANDBY: |
489 | case PM_SUSPEND_MEM: | |
490 | ret = omap3_pm_suspend(); | |
491 | break; | |
492 | default: | |
493 | ret = -EINVAL; | |
494 | } | |
495 | ||
496 | return ret; | |
497 | } | |
498 | ||
2466211e TK |
499 | /* Hooks to enable / disable UART interrupts during suspend */ |
500 | static int omap3_pm_begin(suspend_state_t state) | |
501 | { | |
c166381d | 502 | disable_hlt(); |
2466211e | 503 | suspend_state = state; |
22f51371 | 504 | omap_prcm_irq_prepare(); |
2466211e TK |
505 | return 0; |
506 | } | |
507 | ||
508 | static void omap3_pm_end(void) | |
509 | { | |
510 | suspend_state = PM_SUSPEND_ON; | |
c166381d | 511 | enable_hlt(); |
2466211e TK |
512 | return; |
513 | } | |
514 | ||
22f51371 TK |
515 | static void omap3_pm_finish(void) |
516 | { | |
517 | omap_prcm_irq_complete(); | |
518 | } | |
519 | ||
2f55ac07 | 520 | static const struct platform_suspend_ops omap_pm_ops = { |
2466211e TK |
521 | .begin = omap3_pm_begin, |
522 | .end = omap3_pm_end, | |
8bd22949 | 523 | .enter = omap3_pm_enter, |
22f51371 | 524 | .finish = omap3_pm_finish, |
8bd22949 KH |
525 | .valid = suspend_valid_only_mem, |
526 | }; | |
10f90ed2 | 527 | #endif /* CONFIG_SUSPEND */ |
8bd22949 | 528 | |
1155e426 KH |
529 | |
530 | /** | |
531 | * omap3_iva_idle(): ensure IVA is in idle so it can be put into | |
532 | * retention | |
533 | * | |
534 | * In cases where IVA2 is activated by bootcode, it may prevent | |
535 | * full-chip retention or off-mode because it is not idle. This | |
536 | * function forces the IVA2 into idle state so it can go | |
537 | * into retention/off and thus allow full-chip retention/off. | |
538 | * | |
539 | **/ | |
540 | static void __init omap3_iva_idle(void) | |
541 | { | |
542 | /* ensure IVA2 clock is disabled */ | |
c4d7e58f | 543 | omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); |
1155e426 KH |
544 | |
545 | /* if no clock activity, nothing else to do */ | |
c4d7e58f | 546 | if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & |
1155e426 KH |
547 | OMAP3430_CLKACTIVITY_IVA2_MASK)) |
548 | return; | |
549 | ||
550 | /* Reset IVA2 */ | |
c4d7e58f | 551 | omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | |
2bc4ef71 PW |
552 | OMAP3430_RST2_IVA2_MASK | |
553 | OMAP3430_RST3_IVA2_MASK, | |
37903009 | 554 | OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
1155e426 KH |
555 | |
556 | /* Enable IVA2 clock */ | |
c4d7e58f | 557 | omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, |
1155e426 KH |
558 | OMAP3430_IVA2_MOD, CM_FCLKEN); |
559 | ||
560 | /* Set IVA2 boot mode to 'idle' */ | |
561 | omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, | |
562 | OMAP343X_CONTROL_IVA2_BOOTMOD); | |
563 | ||
564 | /* Un-reset IVA2 */ | |
c4d7e58f | 565 | omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
1155e426 KH |
566 | |
567 | /* Disable IVA2 clock */ | |
c4d7e58f | 568 | omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); |
1155e426 KH |
569 | |
570 | /* Reset IVA2 */ | |
c4d7e58f | 571 | omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | |
2bc4ef71 PW |
572 | OMAP3430_RST2_IVA2_MASK | |
573 | OMAP3430_RST3_IVA2_MASK, | |
37903009 | 574 | OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); |
1155e426 KH |
575 | } |
576 | ||
8111b221 | 577 | static void __init omap3_d2d_idle(void) |
8bd22949 | 578 | { |
8111b221 KH |
579 | u16 mask, padconf; |
580 | ||
581 | /* In a stand alone OMAP3430 where there is not a stacked | |
582 | * modem for the D2D Idle Ack and D2D MStandby must be pulled | |
583 | * high. S CONTROL_PADCONF_SAD2D_IDLEACK and | |
584 | * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ | |
585 | mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ | |
586 | padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); | |
587 | padconf |= mask; | |
588 | omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); | |
589 | ||
590 | padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); | |
591 | padconf |= mask; | |
592 | omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); | |
593 | ||
8bd22949 | 594 | /* reset modem */ |
c4d7e58f | 595 | omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | |
2bc4ef71 | 596 | OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, |
37903009 | 597 | CORE_MOD, OMAP2_RM_RSTCTRL); |
c4d7e58f | 598 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); |
8111b221 | 599 | } |
8bd22949 | 600 | |
8111b221 KH |
601 | static void __init prcm_setup_regs(void) |
602 | { | |
e5863689 G |
603 | u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? |
604 | OMAP3630_EN_UART4_MASK : 0; | |
605 | u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? | |
606 | OMAP3630_GRPSEL_UART4_MASK : 0; | |
607 | ||
4ef70c06 | 608 | /* XXX This should be handled by hwmod code or SCM init code */ |
2fd0f75c | 609 | omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); |
b296c811 | 610 | |
8bd22949 KH |
611 | /* |
612 | * Enable control of expternal oscillator through | |
613 | * sys_clkreq. In the long run clock framework should | |
614 | * take care of this. | |
615 | */ | |
c4d7e58f | 616 | omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, |
8bd22949 KH |
617 | 1 << OMAP_AUTOEXTCLKMODE_SHIFT, |
618 | OMAP3430_GR_MOD, | |
619 | OMAP3_PRM_CLKSRC_CTRL_OFFSET); | |
620 | ||
621 | /* setup wakup source */ | |
c4d7e58f | 622 | omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | |
2fd0f75c | 623 | OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, |
8bd22949 KH |
624 | WKUP_MOD, PM_WKEN); |
625 | /* No need to write EN_IO, that is always enabled */ | |
c4d7e58f | 626 | omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | |
275f675c PW |
627 | OMAP3430_GRPSEL_GPT1_MASK | |
628 | OMAP3430_GRPSEL_GPT12_MASK, | |
8bd22949 | 629 | WKUP_MOD, OMAP3430_PM_MPUGRPSEL); |
1155e426 | 630 | |
b92c5721 | 631 | /* Enable PM_WKEN to support DSS LPR */ |
c4d7e58f | 632 | omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, |
b92c5721 SV |
633 | OMAP3430_DSS_MOD, PM_WKEN); |
634 | ||
b427f92f | 635 | /* Enable wakeups in PER */ |
c4d7e58f | 636 | omap2_prm_write_mod_reg(omap3630_en_uart4_mask | |
e5863689 | 637 | OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | |
2fd0f75c PW |
638 | OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | |
639 | OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | | |
640 | OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK | | |
641 | OMAP3430_EN_MCBSP4_MASK, | |
b427f92f | 642 | OMAP3430_PER_MOD, PM_WKEN); |
eb350f74 | 643 | /* and allow them to wake up MPU */ |
c4d7e58f | 644 | omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask | |
e5863689 | 645 | OMAP3430_GRPSEL_GPIO2_MASK | |
275f675c PW |
646 | OMAP3430_GRPSEL_GPIO3_MASK | |
647 | OMAP3430_GRPSEL_GPIO4_MASK | | |
648 | OMAP3430_GRPSEL_GPIO5_MASK | | |
649 | OMAP3430_GRPSEL_GPIO6_MASK | | |
650 | OMAP3430_GRPSEL_UART3_MASK | | |
651 | OMAP3430_GRPSEL_MCBSP2_MASK | | |
652 | OMAP3430_GRPSEL_MCBSP3_MASK | | |
653 | OMAP3430_GRPSEL_MCBSP4_MASK, | |
eb350f74 KH |
654 | OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); |
655 | ||
d3fd3290 | 656 | /* Don't attach IVA interrupts */ |
c4d7e58f PW |
657 | omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); |
658 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); | |
659 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); | |
660 | omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); | |
d3fd3290 | 661 | |
b1340d17 | 662 | /* Clear any pending 'reset' flags */ |
c4d7e58f PW |
663 | omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); |
664 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); | |
665 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); | |
666 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); | |
667 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); | |
668 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); | |
669 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); | |
b1340d17 | 670 | |
014c46db | 671 | /* Clear any pending PRCM interrupts */ |
c4d7e58f | 672 | omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); |
014c46db | 673 | |
1155e426 | 674 | omap3_iva_idle(); |
8111b221 | 675 | omap3_d2d_idle(); |
8bd22949 KH |
676 | } |
677 | ||
c40552bc KH |
678 | void omap3_pm_off_mode_enable(int enable) |
679 | { | |
680 | struct power_state *pwrst; | |
681 | u32 state; | |
682 | ||
683 | if (enable) | |
684 | state = PWRDM_POWER_OFF; | |
685 | else | |
686 | state = PWRDM_POWER_RET; | |
687 | ||
688 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
cc1b6028 EV |
689 | if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) && |
690 | pwrst->pwrdm == core_pwrdm && | |
691 | state == PWRDM_POWER_OFF) { | |
692 | pwrst->next_state = PWRDM_POWER_RET; | |
e16b41bf | 693 | pr_warn("%s: Core OFF disabled due to errata i583\n", |
cc1b6028 EV |
694 | __func__); |
695 | } else { | |
696 | pwrst->next_state = state; | |
697 | } | |
698 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); | |
c40552bc KH |
699 | } |
700 | } | |
701 | ||
68d4778c TK |
702 | int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) |
703 | { | |
704 | struct power_state *pwrst; | |
705 | ||
706 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
707 | if (pwrst->pwrdm == pwrdm) | |
708 | return pwrst->next_state; | |
709 | } | |
710 | return -EINVAL; | |
711 | } | |
712 | ||
713 | int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) | |
714 | { | |
715 | struct power_state *pwrst; | |
716 | ||
717 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
718 | if (pwrst->pwrdm == pwrdm) { | |
719 | pwrst->next_state = state; | |
720 | return 0; | |
721 | } | |
722 | } | |
723 | return -EINVAL; | |
724 | } | |
725 | ||
a23456e9 | 726 | static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) |
8bd22949 KH |
727 | { |
728 | struct power_state *pwrst; | |
729 | ||
730 | if (!pwrdm->pwrsts) | |
731 | return 0; | |
732 | ||
d3d381c6 | 733 | pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); |
8bd22949 KH |
734 | if (!pwrst) |
735 | return -ENOMEM; | |
736 | pwrst->pwrdm = pwrdm; | |
737 | pwrst->next_state = PWRDM_POWER_RET; | |
738 | list_add(&pwrst->node, &pwrst_list); | |
739 | ||
740 | if (pwrdm_has_hdwr_sar(pwrdm)) | |
741 | pwrdm_enable_hdwr_sar(pwrdm); | |
742 | ||
eb6a2c75 | 743 | return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); |
8bd22949 KH |
744 | } |
745 | ||
746 | /* | |
747 | * Enable hw supervised mode for all clockdomains if it's | |
748 | * supported. Initiate sleep transition for other clockdomains, if | |
749 | * they are not used | |
750 | */ | |
a23456e9 | 751 | static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) |
8bd22949 KH |
752 | { |
753 | if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) | |
5cd1937b | 754 | clkdm_allow_idle(clkdm); |
8bd22949 KH |
755 | else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && |
756 | atomic_read(&clkdm->usecount) == 0) | |
68b921ad | 757 | clkdm_sleep(clkdm); |
8bd22949 KH |
758 | return 0; |
759 | } | |
760 | ||
46e130d2 JP |
761 | /* |
762 | * Push functions to SRAM | |
763 | * | |
764 | * The minimum set of functions is pushed to SRAM for execution: | |
765 | * - omap3_do_wfi for erratum i581 WA, | |
766 | * - save_secure_ram_context for security extensions. | |
767 | */ | |
3231fc88 RN |
768 | void omap_push_sram_idle(void) |
769 | { | |
46e130d2 JP |
770 | omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz); |
771 | ||
27d59a4a TK |
772 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) |
773 | _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, | |
774 | save_secure_ram_context_sz); | |
3231fc88 RN |
775 | } |
776 | ||
8cdfd834 NM |
777 | static void __init pm_errata_configure(void) |
778 | { | |
c4236d2e | 779 | if (cpu_is_omap3630()) { |
458e999e | 780 | pm34xx_errata |= PM_RTA_ERRATUM_i608; |
c4236d2e PDS |
781 | /* Enable the l2 cache toggling in sleep logic */ |
782 | enable_omap3630_toggle_l2_on_restore(); | |
cc1b6028 EV |
783 | if (omap_rev() < OMAP3630_REV_ES1_2) |
784 | pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583; | |
c4236d2e | 785 | } |
8cdfd834 NM |
786 | } |
787 | ||
7cc515f7 | 788 | static int __init omap3_pm_init(void) |
8bd22949 KH |
789 | { |
790 | struct power_state *pwrst, *tmp; | |
55ed9694 | 791 | struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm; |
8bd22949 KH |
792 | int ret; |
793 | ||
794 | if (!cpu_is_omap34xx()) | |
795 | return -ENODEV; | |
796 | ||
b02b9172 PW |
797 | if (!omap3_has_io_chain_ctrl()) |
798 | pr_warning("PM: no software I/O chain control; some wakeups may be lost\n"); | |
799 | ||
8cdfd834 NM |
800 | pm_errata_configure(); |
801 | ||
8bd22949 KH |
802 | /* XXX prcm_setup_regs needs to be before enabling hw |
803 | * supervised mode for powerdomains */ | |
804 | prcm_setup_regs(); | |
805 | ||
22f51371 TK |
806 | ret = request_irq(omap_prcm_event_to_irq("wkup"), |
807 | _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL); | |
808 | ||
809 | if (ret) { | |
810 | pr_err("pm: Failed to request pm_wkup irq\n"); | |
811 | goto err1; | |
812 | } | |
813 | ||
814 | /* IO interrupt is shared with mux code */ | |
815 | ret = request_irq(omap_prcm_event_to_irq("io"), | |
816 | _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io", | |
817 | omap3_pm_init); | |
818 | ||
8bd22949 | 819 | if (ret) { |
22f51371 | 820 | pr_err("pm: Failed to request pm_io irq\n"); |
8bd22949 KH |
821 | goto err1; |
822 | } | |
823 | ||
a23456e9 | 824 | ret = pwrdm_for_each(pwrdms_setup, NULL); |
8bd22949 KH |
825 | if (ret) { |
826 | printk(KERN_ERR "Failed to setup powerdomains\n"); | |
827 | goto err2; | |
828 | } | |
829 | ||
a23456e9 | 830 | (void) clkdm_for_each(clkdms_setup, NULL); |
8bd22949 KH |
831 | |
832 | mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); | |
833 | if (mpu_pwrdm == NULL) { | |
834 | printk(KERN_ERR "Failed to get mpu_pwrdm\n"); | |
835 | goto err2; | |
836 | } | |
837 | ||
fa3c2a4f RN |
838 | neon_pwrdm = pwrdm_lookup("neon_pwrdm"); |
839 | per_pwrdm = pwrdm_lookup("per_pwrdm"); | |
840 | core_pwrdm = pwrdm_lookup("core_pwrdm"); | |
c16c3f67 | 841 | cam_pwrdm = pwrdm_lookup("cam_pwrdm"); |
fa3c2a4f | 842 | |
55ed9694 PW |
843 | neon_clkdm = clkdm_lookup("neon_clkdm"); |
844 | mpu_clkdm = clkdm_lookup("mpu_clkdm"); | |
845 | per_clkdm = clkdm_lookup("per_clkdm"); | |
846 | core_clkdm = clkdm_lookup("core_clkdm"); | |
847 | ||
10f90ed2 | 848 | #ifdef CONFIG_SUSPEND |
8bd22949 | 849 | suspend_set_ops(&omap_pm_ops); |
10f90ed2 | 850 | #endif /* CONFIG_SUSPEND */ |
8bd22949 KH |
851 | |
852 | pm_idle = omap3_pm_idle; | |
0343371e | 853 | omap3_idle_init(); |
8bd22949 | 854 | |
458e999e NM |
855 | /* |
856 | * RTA is disabled during initialization as per erratum i608 | |
857 | * it is safer to disable RTA by the bootloader, but we would like | |
858 | * to be doubly sure here and prevent any mishaps. | |
859 | */ | |
860 | if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608)) | |
861 | omap3630_ctrl_disable_rta(); | |
862 | ||
55ed9694 | 863 | clkdm_add_wkdep(neon_clkdm, mpu_clkdm); |
27d59a4a TK |
864 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { |
865 | omap3_secure_ram_storage = | |
866 | kmalloc(0x803F, GFP_KERNEL); | |
867 | if (!omap3_secure_ram_storage) | |
868 | printk(KERN_ERR "Memory allocation failed when" | |
869 | "allocating for secure sram context\n"); | |
9d97140b TK |
870 | |
871 | local_irq_disable(); | |
872 | local_fiq_disable(); | |
873 | ||
874 | omap_dma_global_context_save(); | |
617fcc98 | 875 | omap3_save_secure_ram_context(); |
9d97140b TK |
876 | omap_dma_global_context_restore(); |
877 | ||
878 | local_irq_enable(); | |
879 | local_fiq_enable(); | |
27d59a4a | 880 | } |
27d59a4a | 881 | |
9d97140b | 882 | omap3_save_scratchpad_contents(); |
8bd22949 KH |
883 | err1: |
884 | return ret; | |
885 | err2: | |
886 | free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); | |
887 | list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { | |
888 | list_del(&pwrst->node); | |
889 | kfree(pwrst); | |
890 | } | |
891 | return ret; | |
892 | } | |
893 | ||
894 | late_initcall(omap3_pm_init); |