[deliverable/linux.git] / arch / arm / mach-omap2 / pm34xx.c

/*
 * OMAP3 Power Management Routines
 *
 * Copyright (C) 2006-2008 Nokia Corporation
 * Tony Lindgren <tony@atomide.com>
 * Jouni Hogander
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * Based on pm.c for omap1
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/pm.h>
#include <linux/suspend.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/list.h>
#include <linux/err.h>
#include <linux/gpio.h>

#include <mach/sram.h>
#include <mach/clockdomain.h>
#include <mach/powerdomain.h>
#include <mach/control.h>
#include <mach/serial.h>

#include "cm.h"
#include "cm-regbits-34xx.h"
#include "prm-regbits-34xx.h"

#include "prm.h"
#include "pm.h"

struct power_state {
	struct powerdomain *pwrdm;
	u32 next_state;
	u32 saved_state;
	struct list_head node;
};

static LIST_HEAD(pwrst_list);

static void (*_omap_sram_idle)(u32 *addr, int save_state);

static struct powerdomain *mpu_pwrdm;

/* PRCM Interrupt Handler for wakeups */
static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
{
	u32 wkst, irqstatus_mpu;
	u32 fclk, iclk;

	/* WKUP */
	wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST);
	if (wkst) {
		iclk = cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
		fclk = cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
		cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_ICLKEN);
		cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_FCLKEN);
		prm_write_mod_reg(wkst, WKUP_MOD, PM_WKST);
		while (prm_read_mod_reg(WKUP_MOD, PM_WKST))
			cpu_relax();
		cm_write_mod_reg(iclk, WKUP_MOD, CM_ICLKEN);
		cm_write_mod_reg(fclk, WKUP_MOD, CM_FCLKEN);
	}

	/* CORE */
	wkst = prm_read_mod_reg(CORE_MOD, PM_WKST1);
	if (wkst) {
		iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
		fclk = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
		cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN1);
		cm_set_mod_reg_bits(wkst, CORE_MOD, CM_FCLKEN1);
		prm_write_mod_reg(wkst, CORE_MOD, PM_WKST1);
		while (prm_read_mod_reg(CORE_MOD, PM_WKST1))
			cpu_relax();
		cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN1);
		cm_write_mod_reg(fclk, CORE_MOD, CM_FCLKEN1);
	}
	wkst = prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3);
	if (wkst) {
		iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
		fclk = cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
		cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN3);
		cm_set_mod_reg_bits(wkst, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
		prm_write_mod_reg(wkst, CORE_MOD, OMAP3430ES2_PM_WKST3);
		while (prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3))
			cpu_relax();
		cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN3);
		cm_write_mod_reg(fclk, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
	}

	/* PER */
	wkst = prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST);
	if (wkst) {
		iclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
		fclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
		cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_ICLKEN);
		cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_FCLKEN);
		prm_write_mod_reg(wkst, OMAP3430_PER_MOD, PM_WKST);
		while (prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST))
			cpu_relax();
		cm_write_mod_reg(iclk, OMAP3430_PER_MOD, CM_ICLKEN);
		cm_write_mod_reg(fclk, OMAP3430_PER_MOD, CM_FCLKEN);
	}

	if (omap_rev() > OMAP3430_REV_ES1_0) {
		/* USBHOST */
		wkst = prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKST);
		if (wkst) {
			iclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
					       CM_ICLKEN);
			fclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
					       CM_FCLKEN);
			cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
					    CM_ICLKEN);
			cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
					    CM_FCLKEN);
			prm_write_mod_reg(wkst, OMAP3430ES2_USBHOST_MOD,
					  PM_WKST);
			while (prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
						PM_WKST))
				cpu_relax();
			cm_write_mod_reg(iclk, OMAP3430ES2_USBHOST_MOD,
					 CM_ICLKEN);
			cm_write_mod_reg(fclk, OMAP3430ES2_USBHOST_MOD,
					 CM_FCLKEN);
		}
	}

	irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
					 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
	prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
			  OMAP3_PRM_IRQSTATUS_MPU_OFFSET);

	while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET))
		cpu_relax();

	return IRQ_HANDLED;
}

static void omap_sram_idle(void)
{
	/* Variable to tell what needs to be saved and restored
	 * in omap_sram_idle*/
	/* save_state = 0 => Nothing to save and restored */
	/* save_state = 1 => Only L1 and logic lost */
	/* save_state = 2 => Only L2 lost */
	/* save_state = 3 => L1, L2 and logic lost */
	int save_state = 0, mpu_next_state;

	if (!_omap_sram_idle)
		return;

	mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
	switch (mpu_next_state) {
	case PWRDM_POWER_RET:
		/* No need to save context */
		save_state = 0;
		break;
	default:
		/* Invalid state */
		printk(KERN_ERR "Invalid mpu state in sram_idle\n");
		return;
	}
	omap2_gpio_prepare_for_retention();
	omap_uart_prepare_idle(0);
	omap_uart_prepare_idle(1);
	omap_uart_prepare_idle(2);

	_omap_sram_idle(NULL, save_state);
	cpu_init();

	omap_uart_resume_idle(2);
	omap_uart_resume_idle(1);
	omap_uart_resume_idle(0);
	omap2_gpio_resume_after_retention();
}

/*
 * Check if functional clocks are enabled before entering
 * sleep. This function could be behind CONFIG_PM_DEBUG
 * when all drivers are configuring their sysconfig registers
 * properly and using their clocks properly.
 */
static int omap3_fclks_active(void)
{
	u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
		fck_cam = 0, fck_per = 0, fck_usbhost = 0;

	fck_core1 = cm_read_mod_reg(CORE_MOD,
				    CM_FCLKEN1);
	if (omap_rev() > OMAP3430_REV_ES1_0) {
		fck_core3 = cm_read_mod_reg(CORE_MOD,
					    OMAP3430ES2_CM_FCLKEN3);
		fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
					  CM_FCLKEN);
		fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
					      CM_FCLKEN);
	} else
		fck_sgx = cm_read_mod_reg(GFX_MOD,
					  OMAP3430ES2_CM_FCLKEN3);
	fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
				  CM_FCLKEN);
	fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
				  CM_FCLKEN);
	fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
				  CM_FCLKEN);

	/* Ignore UART clocks.  These are handled by UART core (serial.c) */
	fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2);
	fck_per &= ~OMAP3430_EN_UART3;

	if (fck_core1 | fck_core3 | fck_sgx | fck_dss |
	    fck_cam | fck_per | fck_usbhost)
		return 1;
	return 0;
}

static int omap3_can_sleep(void)
{
	if (!omap_uart_can_sleep())
		return 0;
	if (omap3_fclks_active())
		return 0;
	return 1;
}

/* This sets pwrdm state (other than mpu & core. Currently only ON &
 * RET are supported. Function is assuming that clkdm doesn't have
 * hw_sup mode enabled. */
static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
{
	u32 cur_state;
	int sleep_switch = 0;
	int ret = 0;

	if (pwrdm == NULL || IS_ERR(pwrdm))
		return -EINVAL;

	while (!(pwrdm->pwrsts & (1 << state))) {
		if (state == PWRDM_POWER_OFF)
			return ret;
		state--;
	}

	cur_state = pwrdm_read_next_pwrst(pwrdm);
	if (cur_state == state)
		return ret;

	if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
		omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
		sleep_switch = 1;
		pwrdm_wait_transition(pwrdm);
	}

	ret = pwrdm_set_next_pwrst(pwrdm, state);
	if (ret) {
		printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
		       pwrdm->name);
		goto err;
	}

	if (sleep_switch) {
		omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
		pwrdm_wait_transition(pwrdm);
	}

err:
	return ret;
}

static void omap3_pm_idle(void)
{
	local_irq_disable();
	local_fiq_disable();

	if (!omap3_can_sleep())
		goto out;

	if (omap_irq_pending())
		goto out;

	omap_sram_idle();

out:
	local_fiq_enable();
	local_irq_enable();
}

static int omap3_pm_prepare(void)
{
	disable_hlt();
	return 0;
}

static int omap3_pm_suspend(void)
{
	struct power_state *pwrst;
	int state, ret = 0;

	/* Read current next_pwrsts */
	list_for_each_entry(pwrst, &pwrst_list, node)
		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
	/* Set ones wanted by suspend */
	list_for_each_entry(pwrst, &pwrst_list, node) {
		if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
			goto restore;
		if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
			goto restore;
	}

	omap_uart_prepare_suspend();
	omap_sram_idle();

restore:
	/* Restore next_pwrsts */
	list_for_each_entry(pwrst, &pwrst_list, node) {
		set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
		state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
		if (state > pwrst->next_state) {
			printk(KERN_INFO "Powerdomain (%s) didn't enter "
			       "target state %d\n",
			       pwrst->pwrdm->name, pwrst->next_state);
			ret = -1;
		}
	}
	if (ret)
		printk(KERN_ERR "Could not enter target state in pm_suspend\n");
	else
		printk(KERN_INFO "Successfully put all powerdomains "
		       "to target state\n");

	return ret;
}

static int omap3_pm_enter(suspend_state_t state)
{
	int ret = 0;

	switch (state) {
	case PM_SUSPEND_STANDBY:
	case PM_SUSPEND_MEM:
		ret = omap3_pm_suspend();
		break;
	default:
		ret = -EINVAL;
	}

	return ret;
}

static void omap3_pm_finish(void)
{
	enable_hlt();
}

static struct platform_suspend_ops omap_pm_ops = {
	.prepare	= omap3_pm_prepare,
	.enter		= omap3_pm_enter,
	.finish		= omap3_pm_finish,
	.valid		= suspend_valid_only_mem,
};


/**
 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 *                   retention
 *
 * In cases where IVA2 is activated by bootcode, it may prevent
 * full-chip retention or off-mode because it is not idle.  This
 * function forces the IVA2 into idle state so it can go
 * into retention/off and thus allow full-chip retention/off.
 *
 **/
static void __init omap3_iva_idle(void)
{
	/* ensure IVA2 clock is disabled */
	cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);

	/* if no clock activity, nothing else to do */
	if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
	      OMAP3430_CLKACTIVITY_IVA2_MASK))
		return;

	/* Reset IVA2 */
	prm_write_mod_reg(OMAP3430_RST1_IVA2 |
			  OMAP3430_RST2_IVA2 |
			  OMAP3430_RST3_IVA2,
			  OMAP3430_IVA2_MOD, RM_RSTCTRL);

	/* Enable IVA2 clock */
	cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2,
			 OMAP3430_IVA2_MOD, CM_FCLKEN);

	/* Set IVA2 boot mode to 'idle' */
	omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
			 OMAP343X_CONTROL_IVA2_BOOTMOD);

	/* Un-reset IVA2 */
	prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);

	/* Disable IVA2 clock */
	cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);

	/* Reset IVA2 */
	prm_write_mod_reg(OMAP3430_RST1_IVA2 |
			  OMAP3430_RST2_IVA2 |
			  OMAP3430_RST3_IVA2,
			  OMAP3430_IVA2_MOD, RM_RSTCTRL);
}

static void __init omap3_d2d_idle(void)
{
	u16 mask, padconf;

	/* In a stand alone OMAP3430 where there is not a stacked
	 * modem for the D2D Idle Ack and D2D MStandby must be pulled
	 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
	 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
	mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
	padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
	padconf |= mask;
	omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);

	padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
	padconf |= mask;
	omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);

	/* reset modem */
	prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON |
			  OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
			  CORE_MOD, RM_RSTCTRL);
	prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
}

static void __init prcm_setup_regs(void)
{
	/* XXX Reset all wkdeps. This should be done when initializing
	 * powerdomains */
	prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
	prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
	prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
	prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
	prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
	prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
	if (omap_rev() > OMAP3430_REV_ES1_0) {
		prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
		prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
	} else
		prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);

	/*
	 * Enable interface clock autoidle for all modules.
	 * Note that in the long run this should be done by clockfw
	 */
	cm_write_mod_reg(
		OMAP3430_AUTO_MODEM |
		OMAP3430ES2_AUTO_MMC3 |
		OMAP3430ES2_AUTO_ICR |
		OMAP3430_AUTO_AES2 |
		OMAP3430_AUTO_SHA12 |
		OMAP3430_AUTO_DES2 |
		OMAP3430_AUTO_MMC2 |
		OMAP3430_AUTO_MMC1 |
		OMAP3430_AUTO_MSPRO |
		OMAP3430_AUTO_HDQ |
		OMAP3430_AUTO_MCSPI4 |
		OMAP3430_AUTO_MCSPI3 |
		OMAP3430_AUTO_MCSPI2 |
		OMAP3430_AUTO_MCSPI1 |
		OMAP3430_AUTO_I2C3 |
		OMAP3430_AUTO_I2C2 |
		OMAP3430_AUTO_I2C1 |
		OMAP3430_AUTO_UART2 |
		OMAP3430_AUTO_UART1 |
		OMAP3430_AUTO_GPT11 |
		OMAP3430_AUTO_GPT10 |
		OMAP3430_AUTO_MCBSP5 |
		OMAP3430_AUTO_MCBSP1 |
		OMAP3430ES1_AUTO_FAC | /* This is es1 only */
		OMAP3430_AUTO_MAILBOXES |
		OMAP3430_AUTO_OMAPCTRL |
		OMAP3430ES1_AUTO_FSHOSTUSB |
		OMAP3430_AUTO_HSOTGUSB |
		OMAP3430_AUTO_SAD2D |
		OMAP3430_AUTO_SSI,
		CORE_MOD, CM_AUTOIDLE1);

	cm_write_mod_reg(
		OMAP3430_AUTO_PKA |
		OMAP3430_AUTO_AES1 |
		OMAP3430_AUTO_RNG |
		OMAP3430_AUTO_SHA11 |
		OMAP3430_AUTO_DES1,
		CORE_MOD, CM_AUTOIDLE2);

	if (omap_rev() > OMAP3430_REV_ES1_0) {
		cm_write_mod_reg(
			OMAP3430_AUTO_MAD2D |
			OMAP3430ES2_AUTO_USBTLL,
			CORE_MOD, CM_AUTOIDLE3);
	}

	cm_write_mod_reg(
		OMAP3430_AUTO_WDT2 |
		OMAP3430_AUTO_WDT1 |
		OMAP3430_AUTO_GPIO1 |
		OMAP3430_AUTO_32KSYNC |
		OMAP3430_AUTO_GPT12 |
		OMAP3430_AUTO_GPT1 ,
		WKUP_MOD, CM_AUTOIDLE);

	cm_write_mod_reg(
		OMAP3430_AUTO_DSS,
		OMAP3430_DSS_MOD,
		CM_AUTOIDLE);

	cm_write_mod_reg(
		OMAP3430_AUTO_CAM,
		OMAP3430_CAM_MOD,
		CM_AUTOIDLE);

	cm_write_mod_reg(
		OMAP3430_AUTO_GPIO6 |
		OMAP3430_AUTO_GPIO5 |
		OMAP3430_AUTO_GPIO4 |
		OMAP3430_AUTO_GPIO3 |
		OMAP3430_AUTO_GPIO2 |
		OMAP3430_AUTO_WDT3 |
		OMAP3430_AUTO_UART3 |
		OMAP3430_AUTO_GPT9 |
		OMAP3430_AUTO_GPT8 |
		OMAP3430_AUTO_GPT7 |
		OMAP3430_AUTO_GPT6 |
		OMAP3430_AUTO_GPT5 |
		OMAP3430_AUTO_GPT4 |
		OMAP3430_AUTO_GPT3 |
		OMAP3430_AUTO_GPT2 |
		OMAP3430_AUTO_MCBSP4 |
		OMAP3430_AUTO_MCBSP3 |
		OMAP3430_AUTO_MCBSP2,
		OMAP3430_PER_MOD,
		CM_AUTOIDLE);

	if (omap_rev() > OMAP3430_REV_ES1_0) {
		cm_write_mod_reg(
			OMAP3430ES2_AUTO_USBHOST,
			OMAP3430ES2_USBHOST_MOD,
			CM_AUTOIDLE);
	}

	/*
	 * Set all plls to autoidle. This is needed until autoidle is
	 * enabled by clockfw
	 */
	cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
			 OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
	cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
			 MPU_MOD,
			 CM_AUTOIDLE2);
	cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
			 (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
			 PLL_MOD,
			 CM_AUTOIDLE);
	cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
			 PLL_MOD,
			 CM_AUTOIDLE2);

	/*
	 * Enable control of expternal oscillator through
	 * sys_clkreq. In the long run clock framework should
	 * take care of this.
	 */
	prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
			     1 << OMAP_AUTOEXTCLKMODE_SHIFT,
			     OMAP3430_GR_MOD,
			     OMAP3_PRM_CLKSRC_CTRL_OFFSET);

	/* setup wakup source */
	prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 |
			  OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12,
			  WKUP_MOD, PM_WKEN);
	/* No need to write EN_IO, that is always enabled */
	prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 |
			  OMAP3430_EN_GPT12,
			  WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
	/* For some reason IO doesn't generate wakeup event even if
	 * it is selected to mpu wakeup goup */
	prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN,
			  OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);

	/* Clear any pending 'reset' flags */
	prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
	prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
	prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
	prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
	prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
	prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
	prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);

	/* Clear any pending PRCM interrupts */
	prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);

	omap3_iva_idle();
	omap3_d2d_idle();
}

static int __init pwrdms_setup(struct powerdomain *pwrdm)
{
	struct power_state *pwrst;

	if (!pwrdm->pwrsts)
		return 0;

	pwrst = kmalloc(sizeof(struct power_state), GFP_KERNEL);
	if (!pwrst)
		return -ENOMEM;
	pwrst->pwrdm = pwrdm;
	pwrst->next_state = PWRDM_POWER_RET;
	list_add(&pwrst->node, &pwrst_list);

	if (pwrdm_has_hdwr_sar(pwrdm))
		pwrdm_enable_hdwr_sar(pwrdm);

	return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
}

/*
 * Enable hw supervised mode for all clockdomains if it's
 * supported. Initiate sleep transition for other clockdomains, if
 * they are not used
 */
static int __init clkdms_setup(struct clockdomain *clkdm)
{
	if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
		omap2_clkdm_allow_idle(clkdm);
	else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
		 atomic_read(&clkdm->usecount) == 0)
		omap2_clkdm_sleep(clkdm);
	return 0;
}

int __init omap3_pm_init(void)
{
	struct power_state *pwrst, *tmp;
	int ret;

	if (!cpu_is_omap34xx())
		return -ENODEV;

	printk(KERN_ERR "Power Management for TI OMAP3.\n");

	/* XXX prcm_setup_regs needs to be before enabling hw
	 * supervised mode for powerdomains */
	prcm_setup_regs();

	ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
			  (irq_handler_t)prcm_interrupt_handler,
			  IRQF_DISABLED, "prcm", NULL);
	if (ret) {
		printk(KERN_ERR "request_irq failed to register for 0x%x\n",
		       INT_34XX_PRCM_MPU_IRQ);
		goto err1;
	}

	ret = pwrdm_for_each(pwrdms_setup);
	if (ret) {
		printk(KERN_ERR "Failed to setup powerdomains\n");
		goto err2;
	}

	(void) clkdm_for_each(clkdms_setup);

	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
	if (mpu_pwrdm == NULL) {
		printk(KERN_ERR "Failed to get mpu_pwrdm\n");
		goto err2;
	}

	_omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
					 omap34xx_cpu_suspend_sz);

	suspend_set_ops(&omap_pm_ops);

	pm_idle = omap3_pm_idle;

err1:
	return ret;
err2:
	free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
	list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
		list_del(&pwrst->node);
		kfree(pwrst);
	}
	return ret;
}

late_initcall(omap3_pm_init);
Commit	Line	Data
8bd22949 KH	1	/*
	2	* OMAP3 Power Management Routines
	3	*
	4	* Copyright (C) 2006-2008 Nokia Corporation
	5	* Tony Lindgren <tony@atomide.com>
	6	* Jouni Hogander
	7	*
	8	* Copyright (C) 2005 Texas Instruments, Inc.
	9	* Richard Woodruff <r-woodruff2@ti.com>
	10	*
	11	* Based on pm.c for omap1
	12	*
	13	* This program is free software; you can redistribute it and/or modify
	14	* it under the terms of the GNU General Public License version 2 as
	15	* published by the Free Software Foundation.
	16	*/
	17
	18	#include <linux/pm.h>
	19	#include <linux/suspend.h>
	20	#include <linux/interrupt.h>
	21	#include <linux/module.h>
	22	#include <linux/list.h>
	23	#include <linux/err.h>
	24	#include <linux/gpio.h>
	25
	26	#include <mach/sram.h>
	27	#include <mach/clockdomain.h>
	28	#include <mach/powerdomain.h>
	29	#include <mach/control.h>
4af4016c	30	#include <mach/serial.h>
8bd22949 KH	31
	32	#include "cm.h"
	33	#include "cm-regbits-34xx.h"
	34	#include "prm-regbits-34xx.h"
	35
	36	#include "prm.h"
	37	#include "pm.h"
	38
	39	struct power_state {
	40	struct powerdomain *pwrdm;
	41	u32 next_state;
	42	u32 saved_state;
	43	struct list_head node;
	44	};
	45
	46	static LIST_HEAD(pwrst_list);
	47
	48	static void (_omap_sram_idle)(u32 addr, int save_state);
	49
	50	static struct powerdomain *mpu_pwrdm;
	51
	52	/* PRCM Interrupt Handler for wakeups */
	53	static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
	54	{
	55	u32 wkst, irqstatus_mpu;
	56	u32 fclk, iclk;
	57
	58	/* WKUP */
	59	wkst = prm_read_mod_reg(WKUP_MOD, PM_WKST);
	60	if (wkst) {
	61	iclk = cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
	62	fclk = cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
	63	cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_ICLKEN);
	64	cm_set_mod_reg_bits(wkst, WKUP_MOD, CM_FCLKEN);
	65	prm_write_mod_reg(wkst, WKUP_MOD, PM_WKST);
	66	while (prm_read_mod_reg(WKUP_MOD, PM_WKST))
	67	cpu_relax();
	68	cm_write_mod_reg(iclk, WKUP_MOD, CM_ICLKEN);
	69	cm_write_mod_reg(fclk, WKUP_MOD, CM_FCLKEN);
	70	}
	71
	72	/* CORE */
	73	wkst = prm_read_mod_reg(CORE_MOD, PM_WKST1);
	74	if (wkst) {
	75	iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
	76	fclk = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
	77	cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN1);
	78	cm_set_mod_reg_bits(wkst, CORE_MOD, CM_FCLKEN1);
	79	prm_write_mod_reg(wkst, CORE_MOD, PM_WKST1);
	80	while (prm_read_mod_reg(CORE_MOD, PM_WKST1))
	81	cpu_relax();
	82	cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN1);
	83	cm_write_mod_reg(fclk, CORE_MOD, CM_FCLKEN1);
	84	}
	85	wkst = prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3);
	86	if (wkst) {
	87	iclk = cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
	88	fclk = cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
	89	cm_set_mod_reg_bits(wkst, CORE_MOD, CM_ICLKEN3);
	90	cm_set_mod_reg_bits(wkst, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
	91	prm_write_mod_reg(wkst, CORE_MOD, OMAP3430ES2_PM_WKST3);
	92	while (prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_WKST3))
	93	cpu_relax();
	94	cm_write_mod_reg(iclk, CORE_MOD, CM_ICLKEN3);
95	cm_write_mod_reg(fclk, CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
96	}
97
98	/* PER */
99	wkst = prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST);
100	if (wkst) {
101	iclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
102	fclk = cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
103	cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_ICLKEN);
104	cm_set_mod_reg_bits(wkst, OMAP3430_PER_MOD, CM_FCLKEN);
105	prm_write_mod_reg(wkst, OMAP3430_PER_MOD, PM_WKST);
106	while (prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKST))
107	cpu_relax();
108	cm_write_mod_reg(iclk, OMAP3430_PER_MOD, CM_ICLKEN);
109	cm_write_mod_reg(fclk, OMAP3430_PER_MOD, CM_FCLKEN);
110	}
111
112	if (omap_rev() > OMAP3430_REV_ES1_0) {
113	/* USBHOST */
114	wkst = prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKST);
115	if (wkst) {
116	iclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
117	CM_ICLKEN);
118	fclk = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
119	CM_FCLKEN);
120	cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
121	CM_ICLKEN);
122	cm_set_mod_reg_bits(wkst, OMAP3430ES2_USBHOST_MOD,
123	CM_FCLKEN);
124	prm_write_mod_reg(wkst, OMAP3430ES2_USBHOST_MOD,
125	PM_WKST);
126	while (prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
127	PM_WKST))
128	cpu_relax();
129	cm_write_mod_reg(iclk, OMAP3430ES2_USBHOST_MOD,
130	CM_ICLKEN);
131	cm_write_mod_reg(fclk, OMAP3430ES2_USBHOST_MOD,
132	CM_FCLKEN);
133	}
134	}
135
136	irqstatus_mpu = prm_read_mod_reg(OCP_MOD,
137	OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
138	prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
139	OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
140
141	while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET))
142	cpu_relax();
143
144	return IRQ_HANDLED;
145	}
146
147	static void omap_sram_idle(void)
148	{
149	/* Variable to tell what needs to be saved and restored
150	* in omap_sram_idle*/
151	/* save_state = 0 => Nothing to save and restored */
152	/* save_state = 1 => Only L1 and logic lost */
153	/* save_state = 2 => Only L2 lost */
154	/* save_state = 3 => L1, L2 and logic lost */
155	int save_state = 0, mpu_next_state;
156
157	if (!_omap_sram_idle)
158	return;
159
160	mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
161	switch (mpu_next_state) {
162	case PWRDM_POWER_RET:
163	/* No need to save context */
164	save_state = 0;
165	break;
166	default:
167	/* Invalid state */
168	printk(KERN_ERR "Invalid mpu state in sram_idle\n");
169	return;
170	}
171	omap2_gpio_prepare_for_retention();
4af4016c KH	172	omap_uart_prepare_idle(0);
	173	omap_uart_prepare_idle(1);
	174	omap_uart_prepare_idle(2);
8bd22949 KH	175
	176	_omap_sram_idle(NULL, save_state);
	177	cpu_init();
	178
4af4016c KH	179	omap_uart_resume_idle(2);
	180	omap_uart_resume_idle(1);
	181	omap_uart_resume_idle(0);
8bd22949 KH	182	omap2_gpio_resume_after_retention();
	183	}
	184
	185	/*
	186	* Check if functional clocks are enabled before entering
	187	* sleep. This function could be behind CONFIG_PM_DEBUG
	188	* when all drivers are configuring their sysconfig registers
	189	* properly and using their clocks properly.
	190	*/
	191	static int omap3_fclks_active(void)
	192	{
	193	u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0,
	194	fck_cam = 0, fck_per = 0, fck_usbhost = 0;
	195
	196	fck_core1 = cm_read_mod_reg(CORE_MOD,
	197	CM_FCLKEN1);
	198	if (omap_rev() > OMAP3430_REV_ES1_0) {
	199	fck_core3 = cm_read_mod_reg(CORE_MOD,
	200	OMAP3430ES2_CM_FCLKEN3);
	201	fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
	202	CM_FCLKEN);
	203	fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
	204	CM_FCLKEN);
	205	} else
	206	fck_sgx = cm_read_mod_reg(GFX_MOD,
	207	OMAP3430ES2_CM_FCLKEN3);
	208	fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD,
	209	CM_FCLKEN);
	210	fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD,
	211	CM_FCLKEN);
	212	fck_per = cm_read_mod_reg(OMAP3430_PER_MOD,
	213	CM_FCLKEN);
4af4016c KH	214
	215	/* Ignore UART clocks. These are handled by UART core (serial.c) */
	216	fck_core1 &= ~(OMAP3430_EN_UART1 \| OMAP3430_EN_UART2);
	217	fck_per &= ~OMAP3430_EN_UART3;
	218
8bd22949 KH	219	if (fck_core1 \| fck_core3 \| fck_sgx \| fck_dss \|
	220	fck_cam \| fck_per \| fck_usbhost)
	221	return 1;
	222	return 0;
	223	}
	224
	225	static int omap3_can_sleep(void)
	226	{
4af4016c KH	227	if (!omap_uart_can_sleep())
4af4016c KH	228	return 0;
8bd22949 KH	229	if (omap3_fclks_active())
	230	return 0;
	231	return 1;
	232	}
	233
	234	/* This sets pwrdm state (other than mpu & core. Currently only ON &
	235	* RET are supported. Function is assuming that clkdm doesn't have
	236	* hw_sup mode enabled. */
	237	static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
	238	{
	239	u32 cur_state;
	240	int sleep_switch = 0;
	241	int ret = 0;
	242
	243	if (pwrdm == NULL \|\| IS_ERR(pwrdm))
	244	return -EINVAL;
	245
	246	while (!(pwrdm->pwrsts & (1 << state))) {
	247	if (state == PWRDM_POWER_OFF)
	248	return ret;
	249	state--;
	250	}
	251
	252	cur_state = pwrdm_read_next_pwrst(pwrdm);
	253	if (cur_state == state)
	254	return ret;
	255
	256	if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) {
	257	omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
	258	sleep_switch = 1;
	259	pwrdm_wait_transition(pwrdm);
	260	}
	261
	262	ret = pwrdm_set_next_pwrst(pwrdm, state);
	263	if (ret) {
	264	printk(KERN_ERR "Unable to set state of powerdomain: %s\n",
	265	pwrdm->name);
	266	goto err;
	267	}
	268
	269	if (sleep_switch) {
	270	omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
	271	pwrdm_wait_transition(pwrdm);
	272	}
	273
	274	err:
	275	return ret;
	276	}
	277
	278	static void omap3_pm_idle(void)
	279	{
	280	local_irq_disable();
	281	local_fiq_disable();
	282
	283	if (!omap3_can_sleep())
	284	goto out;
	285
	286	if (omap_irq_pending())
	287	goto out;
	288
	289	omap_sram_idle();
	290
	291	out:
	292	local_fiq_enable();
293	local_irq_enable();
294	}
295
296	static int omap3_pm_prepare(void)
297	{
298	disable_hlt();
299	return 0;
300	}
301
302	static int omap3_pm_suspend(void)
303	{
304	struct power_state *pwrst;
305	int state, ret = 0;
306
307	/* Read current next_pwrsts */
308	list_for_each_entry(pwrst, &pwrst_list, node)
309	pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
310	/* Set ones wanted by suspend */
311	list_for_each_entry(pwrst, &pwrst_list, node) {
312	if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
313	goto restore;
314	if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
315	goto restore;
316	}
317
4af4016c	318	omap_uart_prepare_suspend();
8bd22949 KH	319	omap_sram_idle();
	320
	321	restore:
	322	/* Restore next_pwrsts */
	323	list_for_each_entry(pwrst, &pwrst_list, node) {
	324	set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
	325	state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
	326	if (state > pwrst->next_state) {
	327	printk(KERN_INFO "Powerdomain (%s) didn't enter "
	328	"target state %d\n",
	329	pwrst->pwrdm->name, pwrst->next_state);
	330	ret = -1;
	331	}
	332	}
	333	if (ret)
	334	printk(KERN_ERR "Could not enter target state in pm_suspend\n");
	335	else
	336	printk(KERN_INFO "Successfully put all powerdomains "
	337	"to target state\n");
	338
	339	return ret;
	340	}
	341
	342	static int omap3_pm_enter(suspend_state_t state)
	343	{
	344	int ret = 0;
	345
	346	switch (state) {
	347	case PM_SUSPEND_STANDBY:
	348	case PM_SUSPEND_MEM:
	349	ret = omap3_pm_suspend();
	350	break;
	351	default:
	352	ret = -EINVAL;
	353	}
	354
	355	return ret;
	356	}
	357
	358	static void omap3_pm_finish(void)
	359	{
	360	enable_hlt();
	361	}
	362
	363	static struct platform_suspend_ops omap_pm_ops = {
	364	.prepare = omap3_pm_prepare,
	365	.enter = omap3_pm_enter,
	366	.finish = omap3_pm_finish,
	367	.valid = suspend_valid_only_mem,
	368	};
	369
1155e426 KH	370
	371	/**
	372	* omap3_iva_idle(): ensure IVA is in idle so it can be put into
	373	* retention
	374	*
	375	* In cases where IVA2 is activated by bootcode, it may prevent
	376	* full-chip retention or off-mode because it is not idle. This
	377	* function forces the IVA2 into idle state so it can go
	378	* into retention/off and thus allow full-chip retention/off.
	379	*
	380	**/
	381	static void __init omap3_iva_idle(void)
	382	{
	383	/* ensure IVA2 clock is disabled */
	384	cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
	385
	386	/* if no clock activity, nothing else to do */
	387	if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
	388	OMAP3430_CLKACTIVITY_IVA2_MASK))
	389	return;
	390
	391	/* Reset IVA2 */
	392	prm_write_mod_reg(OMAP3430_RST1_IVA2 \|
	393	OMAP3430_RST2_IVA2 \|
	394	OMAP3430_RST3_IVA2,
	395	OMAP3430_IVA2_MOD, RM_RSTCTRL);
	396
	397	/* Enable IVA2 clock */
	398	cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2,
	399	OMAP3430_IVA2_MOD, CM_FCLKEN);
	400
	401	/* Set IVA2 boot mode to 'idle' */
	402	omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
	403	OMAP343X_CONTROL_IVA2_BOOTMOD);
	404
	405	/* Un-reset IVA2 */
	406	prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL);
	407
	408	/* Disable IVA2 clock */
	409	cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
	410
	411	/* Reset IVA2 */
	412	prm_write_mod_reg(OMAP3430_RST1_IVA2 \|
	413	OMAP3430_RST2_IVA2 \|
	414	OMAP3430_RST3_IVA2,
	415	OMAP3430_IVA2_MOD, RM_RSTCTRL);
	416	}
	417
8111b221	418	static void __init omap3_d2d_idle(void)
8bd22949	419	{
8111b221 KH	420	u16 mask, padconf;
	421
	422	/* In a stand alone OMAP3430 where there is not a stacked
	423	* modem for the D2D Idle Ack and D2D MStandby must be pulled
	424	* high. S CONTROL_PADCONF_SAD2D_IDLEACK and
	425	* CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
	426	mask = (1 << 4) \| (1 << 3); /* pull-up, enabled */
	427	padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
	428	padconf \|= mask;
	429	omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
	430
	431	padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
	432	padconf \|= mask;
	433	omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
	434
8bd22949 KH	435	/* reset modem */
	436	prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON \|
	437	OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST,
	438	CORE_MOD, RM_RSTCTRL);
	439	prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL);
8111b221	440	}
8bd22949	441
8111b221 KH	442	static void __init prcm_setup_regs(void)
8111b221 KH	443	{
8bd22949 KH	444	/* XXX Reset all wkdeps. This should be done when initializing
	445	* powerdomains */
	446	prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
	447	prm_write_mod_reg(0, MPU_MOD, PM_WKDEP);
	448	prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP);
	449	prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP);
	450	prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP);
	451	prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP);
	452	if (omap_rev() > OMAP3430_REV_ES1_0) {
	453	prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP);
	454	prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
	455	} else
	456	prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
	457
	458	/*
	459	* Enable interface clock autoidle for all modules.
	460	* Note that in the long run this should be done by clockfw
	461	*/
	462	cm_write_mod_reg(
8111b221	463	OMAP3430_AUTO_MODEM \|
8bd22949 KH	464	OMAP3430ES2_AUTO_MMC3 \|
	465	OMAP3430ES2_AUTO_ICR \|
	466	OMAP3430_AUTO_AES2 \|
	467	OMAP3430_AUTO_SHA12 \|
	468	OMAP3430_AUTO_DES2 \|
	469	OMAP3430_AUTO_MMC2 \|
	470	OMAP3430_AUTO_MMC1 \|
	471	OMAP3430_AUTO_MSPRO \|
	472	OMAP3430_AUTO_HDQ \|
	473	OMAP3430_AUTO_MCSPI4 \|
	474	OMAP3430_AUTO_MCSPI3 \|
	475	OMAP3430_AUTO_MCSPI2 \|
	476	OMAP3430_AUTO_MCSPI1 \|
	477	OMAP3430_AUTO_I2C3 \|
	478	OMAP3430_AUTO_I2C2 \|
	479	OMAP3430_AUTO_I2C1 \|
	480	OMAP3430_AUTO_UART2 \|
	481	OMAP3430_AUTO_UART1 \|
	482	OMAP3430_AUTO_GPT11 \|
	483	OMAP3430_AUTO_GPT10 \|
	484	OMAP3430_AUTO_MCBSP5 \|
	485	OMAP3430_AUTO_MCBSP1 \|
	486	OMAP3430ES1_AUTO_FAC \| /* This is es1 only */
	487	OMAP3430_AUTO_MAILBOXES \|
	488	OMAP3430_AUTO_OMAPCTRL \|
	489	OMAP3430ES1_AUTO_FSHOSTUSB \|
	490	OMAP3430_AUTO_HSOTGUSB \|
8111b221	491	OMAP3430_AUTO_SAD2D \|
8bd22949 KH	492	OMAP3430_AUTO_SSI,
	493	CORE_MOD, CM_AUTOIDLE1);
	494
	495	cm_write_mod_reg(
	496	OMAP3430_AUTO_PKA \|
	497	OMAP3430_AUTO_AES1 \|
	498	OMAP3430_AUTO_RNG \|
	499	OMAP3430_AUTO_SHA11 \|
	500	OMAP3430_AUTO_DES1,
	501	CORE_MOD, CM_AUTOIDLE2);
	502
	503	if (omap_rev() > OMAP3430_REV_ES1_0) {
	504	cm_write_mod_reg(
8111b221	505	OMAP3430_AUTO_MAD2D \|
8bd22949 KH	506	OMAP3430ES2_AUTO_USBTLL,
	507	CORE_MOD, CM_AUTOIDLE3);
	508	}
	509
	510	cm_write_mod_reg(
	511	OMAP3430_AUTO_WDT2 \|
	512	OMAP3430_AUTO_WDT1 \|
	513	OMAP3430_AUTO_GPIO1 \|
	514	OMAP3430_AUTO_32KSYNC \|
	515	OMAP3430_AUTO_GPT12 \|
	516	OMAP3430_AUTO_GPT1 ,
	517	WKUP_MOD, CM_AUTOIDLE);
	518
	519	cm_write_mod_reg(
	520	OMAP3430_AUTO_DSS,
	521	OMAP3430_DSS_MOD,
	522	CM_AUTOIDLE);
	523
	524	cm_write_mod_reg(
	525	OMAP3430_AUTO_CAM,
	526	OMAP3430_CAM_MOD,
	527	CM_AUTOIDLE);
	528
	529	cm_write_mod_reg(
	530	OMAP3430_AUTO_GPIO6 \|
	531	OMAP3430_AUTO_GPIO5 \|
	532	OMAP3430_AUTO_GPIO4 \|
	533	OMAP3430_AUTO_GPIO3 \|
	534	OMAP3430_AUTO_GPIO2 \|
	535	OMAP3430_AUTO_WDT3 \|
	536	OMAP3430_AUTO_UART3 \|
	537	OMAP3430_AUTO_GPT9 \|
	538	OMAP3430_AUTO_GPT8 \|
	539	OMAP3430_AUTO_GPT7 \|
	540	OMAP3430_AUTO_GPT6 \|
	541	OMAP3430_AUTO_GPT5 \|
	542	OMAP3430_AUTO_GPT4 \|
	543	OMAP3430_AUTO_GPT3 \|
	544	OMAP3430_AUTO_GPT2 \|
	545	OMAP3430_AUTO_MCBSP4 \|
	546	OMAP3430_AUTO_MCBSP3 \|
	547	OMAP3430_AUTO_MCBSP2,
	548	OMAP3430_PER_MOD,
	549	CM_AUTOIDLE);
	550
	551	if (omap_rev() > OMAP3430_REV_ES1_0) {
	552	cm_write_mod_reg(
	553	OMAP3430ES2_AUTO_USBHOST,
	554	OMAP3430ES2_USBHOST_MOD,
	555	CM_AUTOIDLE);
	556	}
	557
	558	/*
	559	* Set all plls to autoidle. This is needed until autoidle is
	560	* enabled by clockfw
	561	*/
	562	cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
	563	OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
	564	cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
	565	MPU_MOD,
	566	CM_AUTOIDLE2);
	567	cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) \|
	568	(1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
	569	PLL_MOD,
570	CM_AUTOIDLE);
571	cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
572	PLL_MOD,
573	CM_AUTOIDLE2);
574
575	/*
576	* Enable control of expternal oscillator through
577	* sys_clkreq. In the long run clock framework should
578	* take care of this.
579	*/
580	prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
581	1 << OMAP_AUTOEXTCLKMODE_SHIFT,
582	OMAP3430_GR_MOD,
583	OMAP3_PRM_CLKSRC_CTRL_OFFSET);
584
585	/* setup wakup source */
586	prm_write_mod_reg(OMAP3430_EN_IO \| OMAP3430_EN_GPIO1 \|
587	OMAP3430_EN_GPT1 \| OMAP3430_EN_GPT12,
588	WKUP_MOD, PM_WKEN);
589	/* No need to write EN_IO, that is always enabled */
590	prm_write_mod_reg(OMAP3430_EN_GPIO1 \| OMAP3430_EN_GPT1 \|
591	OMAP3430_EN_GPT12,
592	WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
593	/* For some reason IO doesn't generate wakeup event even if
594	* it is selected to mpu wakeup goup */
595	prm_write_mod_reg(OMAP3430_IO_EN \| OMAP3430_WKUP_EN,
596	OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
1155e426	597
b1340d17 KH	598	/* Clear any pending 'reset' flags */
	599	prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST);
	600	prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST);
	601	prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST);
	602	prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST);
	603	prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST);
	604	prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST);
	605	prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST);
	606
014c46db KH	607	/* Clear any pending PRCM interrupts */
	608	prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
	609
1155e426	610	omap3_iva_idle();
8111b221	611	omap3_d2d_idle();
8bd22949 KH	612	}
	613
	614	static int __init pwrdms_setup(struct powerdomain *pwrdm)
	615	{
	616	struct power_state *pwrst;
	617
	618	if (!pwrdm->pwrsts)
	619	return 0;
	620
	621	pwrst = kmalloc(sizeof(struct power_state), GFP_KERNEL);
	622	if (!pwrst)
	623	return -ENOMEM;
	624	pwrst->pwrdm = pwrdm;
	625	pwrst->next_state = PWRDM_POWER_RET;
	626	list_add(&pwrst->node, &pwrst_list);
	627
	628	if (pwrdm_has_hdwr_sar(pwrdm))
	629	pwrdm_enable_hdwr_sar(pwrdm);
	630
	631	return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
	632	}
	633
	634	/*
	635	* Enable hw supervised mode for all clockdomains if it's
	636	* supported. Initiate sleep transition for other clockdomains, if
	637	* they are not used
	638	*/
	639	static int __init clkdms_setup(struct clockdomain *clkdm)
	640	{
	641	if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
	642	omap2_clkdm_allow_idle(clkdm);
	643	else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
	644	atomic_read(&clkdm->usecount) == 0)
	645	omap2_clkdm_sleep(clkdm);
	646	return 0;
	647	}
	648
	649	int __init omap3_pm_init(void)
	650	{
	651	struct power_state pwrst, tmp;
	652	int ret;
	653
	654	if (!cpu_is_omap34xx())
	655	return -ENODEV;
	656
	657	printk(KERN_ERR "Power Management for TI OMAP3.\n");
	658
	659	/* XXX prcm_setup_regs needs to be before enabling hw
	660	* supervised mode for powerdomains */
	661	prcm_setup_regs();
	662
	663	ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
	664	(irq_handler_t)prcm_interrupt_handler,
	665	IRQF_DISABLED, "prcm", NULL);
	666	if (ret) {
	667	printk(KERN_ERR "request_irq failed to register for 0x%x\n",
	668	INT_34XX_PRCM_MPU_IRQ);
	669	goto err1;
	670	}
	671
	672	ret = pwrdm_for_each(pwrdms_setup);
	673	if (ret) {
	674	printk(KERN_ERR "Failed to setup powerdomains\n");
	675	goto err2;
676	}
677
678	(void) clkdm_for_each(clkdms_setup);
679
680	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
681	if (mpu_pwrdm == NULL) {
682	printk(KERN_ERR "Failed to get mpu_pwrdm\n");
683	goto err2;
684	}
685
686	_omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
687	omap34xx_cpu_suspend_sz);
688
689	suspend_set_ops(&omap_pm_ops);
690
691	pm_idle = omap3_pm_idle;
692
693	err1:
694	return ret;
695	err2:
696	free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
697	list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
698	list_del(&pwrst->node);
699	kfree(pwrst);
700	}
701	return ret;
702	}
703
704	late_initcall(omap3_pm_init);