Commit | Line | Data |
---|---|---|
8bd22949 KH |
1 | /* |
2 | * OMAP3 Power Management Routines | |
3 | * | |
4 | * Copyright (C) 2006-2008 Nokia Corporation | |
5 | * Tony Lindgren <tony@atomide.com> | |
6 | * Jouni Hogander | |
7 | * | |
2f5939c3 RN |
8 | * Copyright (C) 2007 Texas Instruments, Inc. |
9 | * Rajendra Nayak <rnayak@ti.com> | |
10 | * | |
8bd22949 KH |
11 | * Copyright (C) 2005 Texas Instruments, Inc. |
12 | * Richard Woodruff <r-woodruff2@ti.com> | |
13 | * | |
14 | * Based on pm.c for omap1 | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/pm.h> | |
22 | #include <linux/suspend.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/module.h> | |
25 | #include <linux/list.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/gpio.h> | |
c40552bc | 28 | #include <linux/clk.h> |
8bd22949 | 29 | |
ce491cf8 TL |
30 | #include <plat/sram.h> |
31 | #include <plat/clockdomain.h> | |
32 | #include <plat/powerdomain.h> | |
33 | #include <plat/control.h> | |
34 | #include <plat/serial.h> | |
61255ab9 | 35 | #include <plat/sdrc.h> |
2f5939c3 RN |
36 | #include <plat/prcm.h> |
37 | #include <plat/gpmc.h> | |
f2d11858 | 38 | #include <plat/dma.h> |
d7814e4d | 39 | #include <plat/dmtimer.h> |
8bd22949 | 40 | |
57f277b0 RN |
41 | #include <asm/tlbflush.h> |
42 | ||
8bd22949 KH |
43 | #include "cm.h" |
44 | #include "cm-regbits-34xx.h" | |
45 | #include "prm-regbits-34xx.h" | |
46 | ||
47 | #include "prm.h" | |
48 | #include "pm.h" | |
13a6fe0f TK |
49 | #include "sdrc.h" |
50 | ||
51 | #define SDRC_POWER_AUTOCOUNT_SHIFT 8 | |
52 | #define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT) | |
53 | #define SDRC_POWER_CLKCTRL_SHIFT 4 | |
54 | #define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT) | |
55 | #define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT) | |
8bd22949 | 56 | |
2f5939c3 RN |
57 | /* Scratchpad offsets */ |
58 | #define OMAP343X_TABLE_ADDRESS_OFFSET 0x31 | |
59 | #define OMAP343X_TABLE_VALUE_OFFSET 0x30 | |
60 | #define OMAP343X_CONTROL_REG_VALUE_OFFSET 0x32 | |
61 | ||
c40552bc KH |
62 | u32 enable_off_mode; |
63 | u32 sleep_while_idle; | |
d7814e4d | 64 | u32 wakeup_timer_seconds; |
c40552bc | 65 | |
8bd22949 KH |
66 | struct power_state { |
67 | struct powerdomain *pwrdm; | |
68 | u32 next_state; | |
10f90ed2 | 69 | #ifdef CONFIG_SUSPEND |
8bd22949 | 70 | u32 saved_state; |
10f90ed2 | 71 | #endif |
8bd22949 KH |
72 | struct list_head node; |
73 | }; | |
74 | ||
75 | static LIST_HEAD(pwrst_list); | |
76 | ||
77 | static void (*_omap_sram_idle)(u32 *addr, int save_state); | |
78 | ||
27d59a4a TK |
79 | static int (*_omap_save_secure_sram)(u32 *addr); |
80 | ||
fa3c2a4f RN |
81 | static struct powerdomain *mpu_pwrdm, *neon_pwrdm; |
82 | static struct powerdomain *core_pwrdm, *per_pwrdm; | |
c16c3f67 | 83 | static struct powerdomain *cam_pwrdm; |
fa3c2a4f RN |
84 | |
85 | static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state); | |
8bd22949 | 86 | |
2f5939c3 RN |
87 | static inline void omap3_per_save_context(void) |
88 | { | |
89 | omap_gpio_save_context(); | |
90 | } | |
91 | ||
92 | static inline void omap3_per_restore_context(void) | |
93 | { | |
94 | omap_gpio_restore_context(); | |
95 | } | |
96 | ||
97 | static void omap3_core_save_context(void) | |
98 | { | |
99 | u32 control_padconf_off; | |
100 | ||
101 | /* Save the padconf registers */ | |
102 | control_padconf_off = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_OFF); | |
103 | control_padconf_off |= START_PADCONF_SAVE; | |
104 | omap_ctrl_writel(control_padconf_off, OMAP343X_CONTROL_PADCONF_OFF); | |
105 | /* wait for the save to complete */ | |
106 | while (!omap_ctrl_readl(OMAP343X_CONTROL_GENERAL_PURPOSE_STATUS) | |
107 | & PADCONF_SAVE_DONE) | |
108 | ; | |
109 | /* Save the Interrupt controller context */ | |
110 | omap_intc_save_context(); | |
111 | /* Save the GPMC context */ | |
112 | omap3_gpmc_save_context(); | |
113 | /* Save the system control module context, padconf already save above*/ | |
114 | omap3_control_save_context(); | |
f2d11858 | 115 | omap_dma_global_context_save(); |
2f5939c3 RN |
116 | } |
117 | ||
118 | static void omap3_core_restore_context(void) | |
119 | { | |
120 | /* Restore the control module context, padconf restored by h/w */ | |
121 | omap3_control_restore_context(); | |
122 | /* Restore the GPMC context */ | |
123 | omap3_gpmc_restore_context(); | |
124 | /* Restore the interrupt controller context */ | |
125 | omap_intc_restore_context(); | |
f2d11858 | 126 | omap_dma_global_context_restore(); |
2f5939c3 RN |
127 | } |
128 | ||
9d97140b TK |
129 | /* |
130 | * FIXME: This function should be called before entering off-mode after | |
131 | * OMAP3 secure services have been accessed. Currently it is only called | |
132 | * once during boot sequence, but this works as we are not using secure | |
133 | * services. | |
134 | */ | |
27d59a4a TK |
135 | static void omap3_save_secure_ram_context(u32 target_mpu_state) |
136 | { | |
137 | u32 ret; | |
138 | ||
139 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { | |
27d59a4a TK |
140 | /* |
141 | * MPU next state must be set to POWER_ON temporarily, | |
142 | * otherwise the WFI executed inside the ROM code | |
143 | * will hang the system. | |
144 | */ | |
145 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); | |
146 | ret = _omap_save_secure_sram((u32 *) | |
147 | __pa(omap3_secure_ram_storage)); | |
148 | pwrdm_set_next_pwrst(mpu_pwrdm, target_mpu_state); | |
149 | /* Following is for error tracking, it should not happen */ | |
150 | if (ret) { | |
151 | printk(KERN_ERR "save_secure_sram() returns %08x\n", | |
152 | ret); | |
153 | while (1) | |
154 | ; | |
155 | } | |
156 | } | |
157 | } | |
158 | ||
77da2d91 JH |
159 | /* |
160 | * PRCM Interrupt Handler Helper Function | |
161 | * | |
162 | * The purpose of this function is to clear any wake-up events latched | |
163 | * in the PRCM PM_WKST_x registers. It is possible that a wake-up event | |
164 | * may occur whilst attempting to clear a PM_WKST_x register and thus | |
165 | * set another bit in this register. A while loop is used to ensure | |
166 | * that any peripheral wake-up events occurring while attempting to | |
167 | * clear the PM_WKST_x are detected and cleared. | |
168 | */ | |
8cb0ac99 | 169 | static int prcm_clear_mod_irqs(s16 module, u8 regs) |
8bd22949 | 170 | { |
71a80775 | 171 | u32 wkst, fclk, iclk, clken; |
77da2d91 JH |
172 | u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; |
173 | u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; | |
174 | u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; | |
5d805978 PW |
175 | u16 grpsel_off = (regs == 3) ? |
176 | OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; | |
8cb0ac99 | 177 | int c = 0; |
8bd22949 | 178 | |
77da2d91 | 179 | wkst = prm_read_mod_reg(module, wkst_off); |
5d805978 | 180 | wkst &= prm_read_mod_reg(module, grpsel_off); |
8bd22949 | 181 | if (wkst) { |
77da2d91 JH |
182 | iclk = cm_read_mod_reg(module, iclk_off); |
183 | fclk = cm_read_mod_reg(module, fclk_off); | |
184 | while (wkst) { | |
71a80775 VP |
185 | clken = wkst; |
186 | cm_set_mod_reg_bits(clken, module, iclk_off); | |
187 | /* | |
188 | * For USBHOST, we don't know whether HOST1 or | |
189 | * HOST2 woke us up, so enable both f-clocks | |
190 | */ | |
191 | if (module == OMAP3430ES2_USBHOST_MOD) | |
192 | clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; | |
193 | cm_set_mod_reg_bits(clken, module, fclk_off); | |
77da2d91 JH |
194 | prm_write_mod_reg(wkst, module, wkst_off); |
195 | wkst = prm_read_mod_reg(module, wkst_off); | |
8cb0ac99 | 196 | c++; |
77da2d91 JH |
197 | } |
198 | cm_write_mod_reg(iclk, module, iclk_off); | |
199 | cm_write_mod_reg(fclk, module, fclk_off); | |
8bd22949 | 200 | } |
8cb0ac99 PW |
201 | |
202 | return c; | |
203 | } | |
204 | ||
205 | static int _prcm_int_handle_wakeup(void) | |
206 | { | |
207 | int c; | |
208 | ||
209 | c = prcm_clear_mod_irqs(WKUP_MOD, 1); | |
210 | c += prcm_clear_mod_irqs(CORE_MOD, 1); | |
211 | c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1); | |
212 | if (omap_rev() > OMAP3430_REV_ES1_0) { | |
213 | c += prcm_clear_mod_irqs(CORE_MOD, 3); | |
214 | c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1); | |
215 | } | |
216 | ||
217 | return c; | |
77da2d91 | 218 | } |
8bd22949 | 219 | |
77da2d91 JH |
220 | /* |
221 | * PRCM Interrupt Handler | |
222 | * | |
223 | * The PRM_IRQSTATUS_MPU register indicates if there are any pending | |
224 | * interrupts from the PRCM for the MPU. These bits must be cleared in | |
225 | * order to clear the PRCM interrupt. The PRCM interrupt handler is | |
226 | * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear | |
227 | * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU | |
228 | * register indicates that a wake-up event is pending for the MPU and | |
229 | * this bit can only be cleared if the all the wake-up events latched | |
230 | * in the various PM_WKST_x registers have been cleared. The interrupt | |
231 | * handler is implemented using a do-while loop so that if a wake-up | |
232 | * event occurred during the processing of the prcm interrupt handler | |
233 | * (setting a bit in the corresponding PM_WKST_x register and thus | |
234 | * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register) | |
235 | * this would be handled. | |
236 | */ | |
237 | static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) | |
238 | { | |
239 | u32 irqstatus_mpu; | |
8cb0ac99 | 240 | int c = 0; |
77da2d91 JH |
241 | |
242 | do { | |
77da2d91 JH |
243 | irqstatus_mpu = prm_read_mod_reg(OCP_MOD, |
244 | OMAP3_PRM_IRQSTATUS_MPU_OFFSET); | |
8cb0ac99 PW |
245 | |
246 | if (irqstatus_mpu & (OMAP3430_WKUP_ST | OMAP3430_IO_ST)) { | |
247 | c = _prcm_int_handle_wakeup(); | |
248 | ||
249 | /* | |
250 | * Is the MPU PRCM interrupt handler racing with the | |
251 | * IVA2 PRCM interrupt handler ? | |
252 | */ | |
253 | WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup " | |
254 | "but no wakeup sources are marked\n"); | |
255 | } else { | |
256 | /* XXX we need to expand our PRCM interrupt handler */ | |
257 | WARN(1, "prcm: WARNING: PRCM interrupt received, but " | |
258 | "no code to handle it (%08x)\n", irqstatus_mpu); | |
259 | } | |
260 | ||
77da2d91 JH |
261 | prm_write_mod_reg(irqstatus_mpu, OCP_MOD, |
262 | OMAP3_PRM_IRQSTATUS_MPU_OFFSET); | |
8bd22949 | 263 | |
77da2d91 | 264 | } while (prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET)); |
8bd22949 KH |
265 | |
266 | return IRQ_HANDLED; | |
267 | } | |
268 | ||
57f277b0 RN |
269 | static void restore_control_register(u32 val) |
270 | { | |
271 | __asm__ __volatile__ ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val)); | |
272 | } | |
273 | ||
274 | /* Function to restore the table entry that was modified for enabling MMU */ | |
275 | static void restore_table_entry(void) | |
276 | { | |
277 | u32 *scratchpad_address; | |
278 | u32 previous_value, control_reg_value; | |
279 | u32 *address; | |
280 | ||
281 | scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); | |
282 | ||
283 | /* Get address of entry that was modified */ | |
284 | address = (u32 *)__raw_readl(scratchpad_address + | |
285 | OMAP343X_TABLE_ADDRESS_OFFSET); | |
286 | /* Get the previous value which needs to be restored */ | |
287 | previous_value = __raw_readl(scratchpad_address + | |
288 | OMAP343X_TABLE_VALUE_OFFSET); | |
289 | address = __va(address); | |
290 | *address = previous_value; | |
291 | flush_tlb_all(); | |
292 | control_reg_value = __raw_readl(scratchpad_address | |
293 | + OMAP343X_CONTROL_REG_VALUE_OFFSET); | |
294 | /* This will enable caches and prediction */ | |
295 | restore_control_register(control_reg_value); | |
296 | } | |
297 | ||
8bd22949 KH |
298 | static void omap_sram_idle(void) |
299 | { | |
300 | /* Variable to tell what needs to be saved and restored | |
301 | * in omap_sram_idle*/ | |
302 | /* save_state = 0 => Nothing to save and restored */ | |
303 | /* save_state = 1 => Only L1 and logic lost */ | |
304 | /* save_state = 2 => Only L2 lost */ | |
305 | /* save_state = 3 => L1, L2 and logic lost */ | |
fa3c2a4f RN |
306 | int save_state = 0; |
307 | int mpu_next_state = PWRDM_POWER_ON; | |
308 | int per_next_state = PWRDM_POWER_ON; | |
309 | int core_next_state = PWRDM_POWER_ON; | |
2f5939c3 | 310 | int core_prev_state, per_prev_state; |
13a6fe0f | 311 | u32 sdrc_pwr = 0; |
ecf157d0 | 312 | int per_state_modified = 0; |
8bd22949 KH |
313 | |
314 | if (!_omap_sram_idle) | |
315 | return; | |
316 | ||
fa3c2a4f RN |
317 | pwrdm_clear_all_prev_pwrst(mpu_pwrdm); |
318 | pwrdm_clear_all_prev_pwrst(neon_pwrdm); | |
319 | pwrdm_clear_all_prev_pwrst(core_pwrdm); | |
320 | pwrdm_clear_all_prev_pwrst(per_pwrdm); | |
321 | ||
8bd22949 KH |
322 | mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm); |
323 | switch (mpu_next_state) { | |
fa3c2a4f | 324 | case PWRDM_POWER_ON: |
8bd22949 KH |
325 | case PWRDM_POWER_RET: |
326 | /* No need to save context */ | |
327 | save_state = 0; | |
328 | break; | |
61255ab9 RN |
329 | case PWRDM_POWER_OFF: |
330 | save_state = 3; | |
331 | break; | |
8bd22949 KH |
332 | default: |
333 | /* Invalid state */ | |
334 | printk(KERN_ERR "Invalid mpu state in sram_idle\n"); | |
335 | return; | |
336 | } | |
fe617af7 PDS |
337 | pwrdm_pre_transition(); |
338 | ||
fa3c2a4f RN |
339 | /* NEON control */ |
340 | if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON) | |
341 | set_pwrdm_state(neon_pwrdm, mpu_next_state); | |
342 | ||
658ce97e KH |
343 | /* PER */ |
344 | per_next_state = pwrdm_read_next_pwrst(per_pwrdm); | |
ecf157d0 | 345 | core_next_state = pwrdm_read_next_pwrst(core_pwrdm); |
658ce97e | 346 | if (per_next_state < PWRDM_POWER_ON) { |
658ce97e | 347 | omap_uart_prepare_idle(2); |
ecf157d0 TK |
348 | omap2_gpio_prepare_for_retention(); |
349 | if (per_next_state == PWRDM_POWER_OFF) { | |
350 | if (core_next_state == PWRDM_POWER_ON) { | |
351 | per_next_state = PWRDM_POWER_RET; | |
352 | pwrdm_set_next_pwrst(per_pwrdm, per_next_state); | |
353 | per_state_modified = 1; | |
354 | } else | |
355 | omap3_per_save_context(); | |
356 | } | |
658ce97e KH |
357 | } |
358 | ||
c16c3f67 TK |
359 | if (pwrdm_read_pwrst(cam_pwrdm) == PWRDM_POWER_ON) |
360 | omap2_clkdm_deny_idle(mpu_pwrdm->pwrdm_clkdms[0]); | |
361 | ||
658ce97e | 362 | /* CORE */ |
fa3c2a4f | 363 | if (core_next_state < PWRDM_POWER_ON) { |
fa3c2a4f RN |
364 | omap_uart_prepare_idle(0); |
365 | omap_uart_prepare_idle(1); | |
2f5939c3 RN |
366 | if (core_next_state == PWRDM_POWER_OFF) { |
367 | omap3_core_save_context(); | |
368 | omap3_prcm_save_context(); | |
369 | } | |
fa3c2a4f RN |
370 | /* Enable IO-PAD wakeup */ |
371 | prm_set_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN); | |
372 | } | |
8bd22949 | 373 | |
13a6fe0f TK |
374 | /* |
375 | * Force SDRAM controller to self-refresh mode after timeout on | |
376 | * autocount. This is needed on ES3.0 to avoid SDRAM controller | |
377 | * hang-ups. | |
378 | */ | |
379 | if (omap_rev() >= OMAP3430_REV_ES3_0 && | |
380 | omap_type() != OMAP2_DEVICE_TYPE_GP && | |
381 | core_next_state == PWRDM_POWER_OFF) { | |
382 | sdrc_pwr = sdrc_read_reg(SDRC_POWER); | |
383 | sdrc_write_reg((sdrc_pwr & | |
384 | ~(SDRC_POWER_AUTOCOUNT_MASK|SDRC_POWER_CLKCTRL_MASK)) | | |
385 | (1 << SDRC_POWER_AUTOCOUNT_SHIFT) | | |
386 | SDRC_SELF_REFRESH_ON_AUTOCOUNT, SDRC_POWER); | |
387 | } | |
388 | ||
61255ab9 RN |
389 | /* |
390 | * omap3_arm_context is the location where ARM registers | |
391 | * get saved. The restore path then reads from this | |
392 | * location and restores them back. | |
393 | */ | |
394 | _omap_sram_idle(omap3_arm_context, save_state); | |
8bd22949 KH |
395 | cpu_init(); |
396 | ||
13a6fe0f TK |
397 | /* Restore normal SDRAM settings */ |
398 | if (omap_rev() >= OMAP3430_REV_ES3_0 && | |
399 | omap_type() != OMAP2_DEVICE_TYPE_GP && | |
400 | core_next_state == PWRDM_POWER_OFF) | |
401 | sdrc_write_reg(sdrc_pwr, SDRC_POWER); | |
402 | ||
57f277b0 RN |
403 | /* Restore table entry modified during MMU restoration */ |
404 | if (pwrdm_read_prev_pwrst(mpu_pwrdm) == PWRDM_POWER_OFF) | |
405 | restore_table_entry(); | |
406 | ||
658ce97e | 407 | /* CORE */ |
fa3c2a4f | 408 | if (core_next_state < PWRDM_POWER_ON) { |
2f5939c3 RN |
409 | core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm); |
410 | if (core_prev_state == PWRDM_POWER_OFF) { | |
411 | omap3_core_restore_context(); | |
412 | omap3_prcm_restore_context(); | |
413 | omap3_sram_restore_context(); | |
8a917d2f | 414 | omap2_sms_restore_context(); |
2f5939c3 | 415 | } |
658ce97e KH |
416 | omap_uart_resume_idle(0); |
417 | omap_uart_resume_idle(1); | |
418 | if (core_next_state == PWRDM_POWER_OFF) | |
419 | prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF, | |
420 | OMAP3430_GR_MOD, | |
421 | OMAP3_PRM_VOLTCTRL_OFFSET); | |
422 | } | |
423 | ||
424 | /* PER */ | |
425 | if (per_next_state < PWRDM_POWER_ON) { | |
426 | per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm); | |
658ce97e KH |
427 | if (per_prev_state == PWRDM_POWER_OFF) |
428 | omap3_per_restore_context(); | |
fa3c2a4f | 429 | omap2_gpio_resume_after_retention(); |
ecf157d0 TK |
430 | omap_uart_resume_idle(2); |
431 | if (per_state_modified) | |
432 | pwrdm_set_next_pwrst(per_pwrdm, PWRDM_POWER_OFF); | |
fa3c2a4f | 433 | } |
fe617af7 | 434 | |
658ce97e KH |
435 | /* Disable IO-PAD wakeup */ |
436 | if (core_next_state < PWRDM_POWER_ON) | |
437 | prm_clear_mod_reg_bits(OMAP3430_EN_IO, WKUP_MOD, PM_WKEN); | |
438 | ||
fe617af7 PDS |
439 | pwrdm_post_transition(); |
440 | ||
c16c3f67 | 441 | omap2_clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]); |
8bd22949 KH |
442 | } |
443 | ||
444 | /* | |
445 | * Check if functional clocks are enabled before entering | |
446 | * sleep. This function could be behind CONFIG_PM_DEBUG | |
447 | * when all drivers are configuring their sysconfig registers | |
448 | * properly and using their clocks properly. | |
449 | */ | |
450 | static int omap3_fclks_active(void) | |
451 | { | |
452 | u32 fck_core1 = 0, fck_core3 = 0, fck_sgx = 0, fck_dss = 0, | |
453 | fck_cam = 0, fck_per = 0, fck_usbhost = 0; | |
454 | ||
455 | fck_core1 = cm_read_mod_reg(CORE_MOD, | |
456 | CM_FCLKEN1); | |
457 | if (omap_rev() > OMAP3430_REV_ES1_0) { | |
458 | fck_core3 = cm_read_mod_reg(CORE_MOD, | |
459 | OMAP3430ES2_CM_FCLKEN3); | |
460 | fck_sgx = cm_read_mod_reg(OMAP3430ES2_SGX_MOD, | |
461 | CM_FCLKEN); | |
462 | fck_usbhost = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, | |
463 | CM_FCLKEN); | |
464 | } else | |
465 | fck_sgx = cm_read_mod_reg(GFX_MOD, | |
466 | OMAP3430ES2_CM_FCLKEN3); | |
467 | fck_dss = cm_read_mod_reg(OMAP3430_DSS_MOD, | |
468 | CM_FCLKEN); | |
469 | fck_cam = cm_read_mod_reg(OMAP3430_CAM_MOD, | |
470 | CM_FCLKEN); | |
471 | fck_per = cm_read_mod_reg(OMAP3430_PER_MOD, | |
472 | CM_FCLKEN); | |
4af4016c KH |
473 | |
474 | /* Ignore UART clocks. These are handled by UART core (serial.c) */ | |
475 | fck_core1 &= ~(OMAP3430_EN_UART1 | OMAP3430_EN_UART2); | |
476 | fck_per &= ~OMAP3430_EN_UART3; | |
477 | ||
8bd22949 KH |
478 | if (fck_core1 | fck_core3 | fck_sgx | fck_dss | |
479 | fck_cam | fck_per | fck_usbhost) | |
480 | return 1; | |
481 | return 0; | |
482 | } | |
483 | ||
484 | static int omap3_can_sleep(void) | |
485 | { | |
c40552bc KH |
486 | if (!sleep_while_idle) |
487 | return 0; | |
4af4016c KH |
488 | if (!omap_uart_can_sleep()) |
489 | return 0; | |
8bd22949 KH |
490 | if (omap3_fclks_active()) |
491 | return 0; | |
492 | return 1; | |
493 | } | |
494 | ||
495 | /* This sets pwrdm state (other than mpu & core. Currently only ON & | |
496 | * RET are supported. Function is assuming that clkdm doesn't have | |
497 | * hw_sup mode enabled. */ | |
498 | static int set_pwrdm_state(struct powerdomain *pwrdm, u32 state) | |
499 | { | |
500 | u32 cur_state; | |
501 | int sleep_switch = 0; | |
502 | int ret = 0; | |
503 | ||
504 | if (pwrdm == NULL || IS_ERR(pwrdm)) | |
505 | return -EINVAL; | |
506 | ||
507 | while (!(pwrdm->pwrsts & (1 << state))) { | |
508 | if (state == PWRDM_POWER_OFF) | |
509 | return ret; | |
510 | state--; | |
511 | } | |
512 | ||
513 | cur_state = pwrdm_read_next_pwrst(pwrdm); | |
514 | if (cur_state == state) | |
515 | return ret; | |
516 | ||
517 | if (pwrdm_read_pwrst(pwrdm) < PWRDM_POWER_ON) { | |
518 | omap2_clkdm_wakeup(pwrdm->pwrdm_clkdms[0]); | |
519 | sleep_switch = 1; | |
520 | pwrdm_wait_transition(pwrdm); | |
521 | } | |
522 | ||
523 | ret = pwrdm_set_next_pwrst(pwrdm, state); | |
524 | if (ret) { | |
525 | printk(KERN_ERR "Unable to set state of powerdomain: %s\n", | |
526 | pwrdm->name); | |
527 | goto err; | |
528 | } | |
529 | ||
530 | if (sleep_switch) { | |
531 | omap2_clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]); | |
532 | pwrdm_wait_transition(pwrdm); | |
fe617af7 | 533 | pwrdm_state_switch(pwrdm); |
8bd22949 KH |
534 | } |
535 | ||
536 | err: | |
537 | return ret; | |
538 | } | |
539 | ||
540 | static void omap3_pm_idle(void) | |
541 | { | |
542 | local_irq_disable(); | |
543 | local_fiq_disable(); | |
544 | ||
545 | if (!omap3_can_sleep()) | |
546 | goto out; | |
547 | ||
548 | if (omap_irq_pending()) | |
549 | goto out; | |
550 | ||
551 | omap_sram_idle(); | |
552 | ||
553 | out: | |
554 | local_fiq_enable(); | |
555 | local_irq_enable(); | |
556 | } | |
557 | ||
10f90ed2 | 558 | #ifdef CONFIG_SUSPEND |
2466211e TK |
559 | static suspend_state_t suspend_state; |
560 | ||
d7814e4d KH |
561 | static void omap2_pm_wakeup_on_timer(u32 seconds) |
562 | { | |
563 | u32 tick_rate, cycles; | |
564 | ||
565 | if (!seconds) | |
566 | return; | |
567 | ||
568 | tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup)); | |
569 | cycles = tick_rate * seconds; | |
570 | omap_dm_timer_stop(gptimer_wakeup); | |
571 | omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles); | |
572 | ||
573 | pr_info("PM: Resume timer in %d secs (%d ticks at %d ticks/sec.)\n", | |
574 | seconds, cycles, tick_rate); | |
575 | } | |
576 | ||
8bd22949 KH |
577 | static int omap3_pm_prepare(void) |
578 | { | |
579 | disable_hlt(); | |
580 | return 0; | |
581 | } | |
582 | ||
583 | static int omap3_pm_suspend(void) | |
584 | { | |
585 | struct power_state *pwrst; | |
586 | int state, ret = 0; | |
587 | ||
d7814e4d KH |
588 | if (wakeup_timer_seconds) |
589 | omap2_pm_wakeup_on_timer(wakeup_timer_seconds); | |
590 | ||
8bd22949 KH |
591 | /* Read current next_pwrsts */ |
592 | list_for_each_entry(pwrst, &pwrst_list, node) | |
593 | pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); | |
594 | /* Set ones wanted by suspend */ | |
595 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
596 | if (set_pwrdm_state(pwrst->pwrdm, pwrst->next_state)) | |
597 | goto restore; | |
598 | if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm)) | |
599 | goto restore; | |
600 | } | |
601 | ||
4af4016c | 602 | omap_uart_prepare_suspend(); |
8bd22949 KH |
603 | omap_sram_idle(); |
604 | ||
605 | restore: | |
606 | /* Restore next_pwrsts */ | |
607 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
8bd22949 KH |
608 | state = pwrdm_read_prev_pwrst(pwrst->pwrdm); |
609 | if (state > pwrst->next_state) { | |
610 | printk(KERN_INFO "Powerdomain (%s) didn't enter " | |
611 | "target state %d\n", | |
612 | pwrst->pwrdm->name, pwrst->next_state); | |
613 | ret = -1; | |
614 | } | |
6c5f8039 | 615 | set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); |
8bd22949 KH |
616 | } |
617 | if (ret) | |
618 | printk(KERN_ERR "Could not enter target state in pm_suspend\n"); | |
619 | else | |
620 | printk(KERN_INFO "Successfully put all powerdomains " | |
621 | "to target state\n"); | |
622 | ||
623 | return ret; | |
624 | } | |
625 | ||
2466211e | 626 | static int omap3_pm_enter(suspend_state_t unused) |
8bd22949 KH |
627 | { |
628 | int ret = 0; | |
629 | ||
2466211e | 630 | switch (suspend_state) { |
8bd22949 KH |
631 | case PM_SUSPEND_STANDBY: |
632 | case PM_SUSPEND_MEM: | |
633 | ret = omap3_pm_suspend(); | |
634 | break; | |
635 | default: | |
636 | ret = -EINVAL; | |
637 | } | |
638 | ||
639 | return ret; | |
640 | } | |
641 | ||
642 | static void omap3_pm_finish(void) | |
643 | { | |
644 | enable_hlt(); | |
645 | } | |
646 | ||
2466211e TK |
647 | /* Hooks to enable / disable UART interrupts during suspend */ |
648 | static int omap3_pm_begin(suspend_state_t state) | |
649 | { | |
650 | suspend_state = state; | |
651 | omap_uart_enable_irqs(0); | |
652 | return 0; | |
653 | } | |
654 | ||
655 | static void omap3_pm_end(void) | |
656 | { | |
657 | suspend_state = PM_SUSPEND_ON; | |
658 | omap_uart_enable_irqs(1); | |
659 | return; | |
660 | } | |
661 | ||
8bd22949 | 662 | static struct platform_suspend_ops omap_pm_ops = { |
2466211e TK |
663 | .begin = omap3_pm_begin, |
664 | .end = omap3_pm_end, | |
8bd22949 KH |
665 | .prepare = omap3_pm_prepare, |
666 | .enter = omap3_pm_enter, | |
667 | .finish = omap3_pm_finish, | |
668 | .valid = suspend_valid_only_mem, | |
669 | }; | |
10f90ed2 | 670 | #endif /* CONFIG_SUSPEND */ |
8bd22949 | 671 | |
1155e426 KH |
672 | |
673 | /** | |
674 | * omap3_iva_idle(): ensure IVA is in idle so it can be put into | |
675 | * retention | |
676 | * | |
677 | * In cases where IVA2 is activated by bootcode, it may prevent | |
678 | * full-chip retention or off-mode because it is not idle. This | |
679 | * function forces the IVA2 into idle state so it can go | |
680 | * into retention/off and thus allow full-chip retention/off. | |
681 | * | |
682 | **/ | |
683 | static void __init omap3_iva_idle(void) | |
684 | { | |
685 | /* ensure IVA2 clock is disabled */ | |
686 | cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); | |
687 | ||
688 | /* if no clock activity, nothing else to do */ | |
689 | if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & | |
690 | OMAP3430_CLKACTIVITY_IVA2_MASK)) | |
691 | return; | |
692 | ||
693 | /* Reset IVA2 */ | |
694 | prm_write_mod_reg(OMAP3430_RST1_IVA2 | | |
695 | OMAP3430_RST2_IVA2 | | |
696 | OMAP3430_RST3_IVA2, | |
697 | OMAP3430_IVA2_MOD, RM_RSTCTRL); | |
698 | ||
699 | /* Enable IVA2 clock */ | |
700 | cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2, | |
701 | OMAP3430_IVA2_MOD, CM_FCLKEN); | |
702 | ||
703 | /* Set IVA2 boot mode to 'idle' */ | |
704 | omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, | |
705 | OMAP343X_CONTROL_IVA2_BOOTMOD); | |
706 | ||
707 | /* Un-reset IVA2 */ | |
708 | prm_write_mod_reg(0, OMAP3430_IVA2_MOD, RM_RSTCTRL); | |
709 | ||
710 | /* Disable IVA2 clock */ | |
711 | cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); | |
712 | ||
713 | /* Reset IVA2 */ | |
714 | prm_write_mod_reg(OMAP3430_RST1_IVA2 | | |
715 | OMAP3430_RST2_IVA2 | | |
716 | OMAP3430_RST3_IVA2, | |
717 | OMAP3430_IVA2_MOD, RM_RSTCTRL); | |
718 | } | |
719 | ||
8111b221 | 720 | static void __init omap3_d2d_idle(void) |
8bd22949 | 721 | { |
8111b221 KH |
722 | u16 mask, padconf; |
723 | ||
724 | /* In a stand alone OMAP3430 where there is not a stacked | |
725 | * modem for the D2D Idle Ack and D2D MStandby must be pulled | |
726 | * high. S CONTROL_PADCONF_SAD2D_IDLEACK and | |
727 | * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ | |
728 | mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ | |
729 | padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); | |
730 | padconf |= mask; | |
731 | omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); | |
732 | ||
733 | padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); | |
734 | padconf |= mask; | |
735 | omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); | |
736 | ||
8bd22949 KH |
737 | /* reset modem */ |
738 | prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON | | |
739 | OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST, | |
740 | CORE_MOD, RM_RSTCTRL); | |
741 | prm_write_mod_reg(0, CORE_MOD, RM_RSTCTRL); | |
8111b221 | 742 | } |
8bd22949 | 743 | |
8111b221 KH |
744 | static void __init prcm_setup_regs(void) |
745 | { | |
8bd22949 KH |
746 | /* XXX Reset all wkdeps. This should be done when initializing |
747 | * powerdomains */ | |
748 | prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); | |
749 | prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); | |
750 | prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); | |
751 | prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); | |
752 | prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); | |
753 | prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); | |
754 | if (omap_rev() > OMAP3430_REV_ES1_0) { | |
755 | prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); | |
756 | prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); | |
757 | } else | |
758 | prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); | |
759 | ||
760 | /* | |
761 | * Enable interface clock autoidle for all modules. | |
762 | * Note that in the long run this should be done by clockfw | |
763 | */ | |
764 | cm_write_mod_reg( | |
8111b221 | 765 | OMAP3430_AUTO_MODEM | |
8bd22949 KH |
766 | OMAP3430ES2_AUTO_MMC3 | |
767 | OMAP3430ES2_AUTO_ICR | | |
768 | OMAP3430_AUTO_AES2 | | |
769 | OMAP3430_AUTO_SHA12 | | |
770 | OMAP3430_AUTO_DES2 | | |
771 | OMAP3430_AUTO_MMC2 | | |
772 | OMAP3430_AUTO_MMC1 | | |
773 | OMAP3430_AUTO_MSPRO | | |
774 | OMAP3430_AUTO_HDQ | | |
775 | OMAP3430_AUTO_MCSPI4 | | |
776 | OMAP3430_AUTO_MCSPI3 | | |
777 | OMAP3430_AUTO_MCSPI2 | | |
778 | OMAP3430_AUTO_MCSPI1 | | |
779 | OMAP3430_AUTO_I2C3 | | |
780 | OMAP3430_AUTO_I2C2 | | |
781 | OMAP3430_AUTO_I2C1 | | |
782 | OMAP3430_AUTO_UART2 | | |
783 | OMAP3430_AUTO_UART1 | | |
784 | OMAP3430_AUTO_GPT11 | | |
785 | OMAP3430_AUTO_GPT10 | | |
786 | OMAP3430_AUTO_MCBSP5 | | |
787 | OMAP3430_AUTO_MCBSP1 | | |
788 | OMAP3430ES1_AUTO_FAC | /* This is es1 only */ | |
789 | OMAP3430_AUTO_MAILBOXES | | |
790 | OMAP3430_AUTO_OMAPCTRL | | |
791 | OMAP3430ES1_AUTO_FSHOSTUSB | | |
792 | OMAP3430_AUTO_HSOTGUSB | | |
8111b221 | 793 | OMAP3430_AUTO_SAD2D | |
8bd22949 KH |
794 | OMAP3430_AUTO_SSI, |
795 | CORE_MOD, CM_AUTOIDLE1); | |
796 | ||
797 | cm_write_mod_reg( | |
798 | OMAP3430_AUTO_PKA | | |
799 | OMAP3430_AUTO_AES1 | | |
800 | OMAP3430_AUTO_RNG | | |
801 | OMAP3430_AUTO_SHA11 | | |
802 | OMAP3430_AUTO_DES1, | |
803 | CORE_MOD, CM_AUTOIDLE2); | |
804 | ||
805 | if (omap_rev() > OMAP3430_REV_ES1_0) { | |
806 | cm_write_mod_reg( | |
8111b221 | 807 | OMAP3430_AUTO_MAD2D | |
8bd22949 KH |
808 | OMAP3430ES2_AUTO_USBTLL, |
809 | CORE_MOD, CM_AUTOIDLE3); | |
810 | } | |
811 | ||
812 | cm_write_mod_reg( | |
813 | OMAP3430_AUTO_WDT2 | | |
814 | OMAP3430_AUTO_WDT1 | | |
815 | OMAP3430_AUTO_GPIO1 | | |
816 | OMAP3430_AUTO_32KSYNC | | |
817 | OMAP3430_AUTO_GPT12 | | |
818 | OMAP3430_AUTO_GPT1 , | |
819 | WKUP_MOD, CM_AUTOIDLE); | |
820 | ||
821 | cm_write_mod_reg( | |
822 | OMAP3430_AUTO_DSS, | |
823 | OMAP3430_DSS_MOD, | |
824 | CM_AUTOIDLE); | |
825 | ||
826 | cm_write_mod_reg( | |
827 | OMAP3430_AUTO_CAM, | |
828 | OMAP3430_CAM_MOD, | |
829 | CM_AUTOIDLE); | |
830 | ||
831 | cm_write_mod_reg( | |
832 | OMAP3430_AUTO_GPIO6 | | |
833 | OMAP3430_AUTO_GPIO5 | | |
834 | OMAP3430_AUTO_GPIO4 | | |
835 | OMAP3430_AUTO_GPIO3 | | |
836 | OMAP3430_AUTO_GPIO2 | | |
837 | OMAP3430_AUTO_WDT3 | | |
838 | OMAP3430_AUTO_UART3 | | |
839 | OMAP3430_AUTO_GPT9 | | |
840 | OMAP3430_AUTO_GPT8 | | |
841 | OMAP3430_AUTO_GPT7 | | |
842 | OMAP3430_AUTO_GPT6 | | |
843 | OMAP3430_AUTO_GPT5 | | |
844 | OMAP3430_AUTO_GPT4 | | |
845 | OMAP3430_AUTO_GPT3 | | |
846 | OMAP3430_AUTO_GPT2 | | |
847 | OMAP3430_AUTO_MCBSP4 | | |
848 | OMAP3430_AUTO_MCBSP3 | | |
849 | OMAP3430_AUTO_MCBSP2, | |
850 | OMAP3430_PER_MOD, | |
851 | CM_AUTOIDLE); | |
852 | ||
853 | if (omap_rev() > OMAP3430_REV_ES1_0) { | |
854 | cm_write_mod_reg( | |
855 | OMAP3430ES2_AUTO_USBHOST, | |
856 | OMAP3430ES2_USBHOST_MOD, | |
857 | CM_AUTOIDLE); | |
858 | } | |
859 | ||
860 | /* | |
861 | * Set all plls to autoidle. This is needed until autoidle is | |
862 | * enabled by clockfw | |
863 | */ | |
864 | cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, | |
865 | OMAP3430_IVA2_MOD, CM_AUTOIDLE2); | |
866 | cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, | |
867 | MPU_MOD, | |
868 | CM_AUTOIDLE2); | |
869 | cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | | |
870 | (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), | |
871 | PLL_MOD, | |
872 | CM_AUTOIDLE); | |
873 | cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, | |
874 | PLL_MOD, | |
875 | CM_AUTOIDLE2); | |
876 | ||
877 | /* | |
878 | * Enable control of expternal oscillator through | |
879 | * sys_clkreq. In the long run clock framework should | |
880 | * take care of this. | |
881 | */ | |
882 | prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, | |
883 | 1 << OMAP_AUTOEXTCLKMODE_SHIFT, | |
884 | OMAP3430_GR_MOD, | |
885 | OMAP3_PRM_CLKSRC_CTRL_OFFSET); | |
886 | ||
887 | /* setup wakup source */ | |
888 | prm_write_mod_reg(OMAP3430_EN_IO | OMAP3430_EN_GPIO1 | | |
889 | OMAP3430_EN_GPT1 | OMAP3430_EN_GPT12, | |
890 | WKUP_MOD, PM_WKEN); | |
891 | /* No need to write EN_IO, that is always enabled */ | |
892 | prm_write_mod_reg(OMAP3430_EN_GPIO1 | OMAP3430_EN_GPT1 | | |
893 | OMAP3430_EN_GPT12, | |
894 | WKUP_MOD, OMAP3430_PM_MPUGRPSEL); | |
895 | /* For some reason IO doesn't generate wakeup event even if | |
896 | * it is selected to mpu wakeup goup */ | |
897 | prm_write_mod_reg(OMAP3430_IO_EN | OMAP3430_WKUP_EN, | |
898 | OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); | |
1155e426 | 899 | |
b427f92f | 900 | /* Enable wakeups in PER */ |
eb350f74 KH |
901 | prm_write_mod_reg(OMAP3430_EN_GPIO2 | OMAP3430_EN_GPIO3 | |
902 | OMAP3430_EN_GPIO4 | OMAP3430_EN_GPIO5 | | |
b427f92f KH |
903 | OMAP3430_EN_GPIO6 | OMAP3430_EN_UART3, |
904 | OMAP3430_PER_MOD, PM_WKEN); | |
eb350f74 KH |
905 | /* and allow them to wake up MPU */ |
906 | prm_write_mod_reg(OMAP3430_GRPSEL_GPIO2 | OMAP3430_EN_GPIO3 | | |
907 | OMAP3430_GRPSEL_GPIO4 | OMAP3430_EN_GPIO5 | | |
b427f92f | 908 | OMAP3430_GRPSEL_GPIO6 | OMAP3430_EN_UART3, |
eb350f74 KH |
909 | OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); |
910 | ||
d3fd3290 KH |
911 | /* Don't attach IVA interrupts */ |
912 | prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); | |
913 | prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); | |
914 | prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); | |
915 | prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); | |
916 | ||
b1340d17 KH |
917 | /* Clear any pending 'reset' flags */ |
918 | prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST); | |
919 | prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST); | |
920 | prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST); | |
921 | prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST); | |
922 | prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST); | |
923 | prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST); | |
924 | prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST); | |
925 | ||
014c46db KH |
926 | /* Clear any pending PRCM interrupts */ |
927 | prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); | |
928 | ||
040fed05 KH |
929 | /* Don't attach IVA interrupts */ |
930 | prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); | |
931 | prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); | |
932 | prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); | |
933 | prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); | |
934 | ||
3a07ae30 KH |
935 | /* Clear any pending 'reset' flags */ |
936 | prm_write_mod_reg(0xffffffff, MPU_MOD, RM_RSTST); | |
937 | prm_write_mod_reg(0xffffffff, CORE_MOD, RM_RSTST); | |
938 | prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, RM_RSTST); | |
939 | prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, RM_RSTST); | |
940 | prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, RM_RSTST); | |
941 | prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, RM_RSTST); | |
942 | prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, RM_RSTST); | |
943 | ||
3a6667ac KH |
944 | /* Clear any pending PRCM interrupts */ |
945 | prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); | |
946 | ||
1155e426 | 947 | omap3_iva_idle(); |
8111b221 | 948 | omap3_d2d_idle(); |
8bd22949 KH |
949 | } |
950 | ||
c40552bc KH |
951 | void omap3_pm_off_mode_enable(int enable) |
952 | { | |
953 | struct power_state *pwrst; | |
954 | u32 state; | |
955 | ||
956 | if (enable) | |
957 | state = PWRDM_POWER_OFF; | |
958 | else | |
959 | state = PWRDM_POWER_RET; | |
960 | ||
961 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
962 | pwrst->next_state = state; | |
963 | set_pwrdm_state(pwrst->pwrdm, state); | |
964 | } | |
965 | } | |
966 | ||
68d4778c TK |
967 | int omap3_pm_get_suspend_state(struct powerdomain *pwrdm) |
968 | { | |
969 | struct power_state *pwrst; | |
970 | ||
971 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
972 | if (pwrst->pwrdm == pwrdm) | |
973 | return pwrst->next_state; | |
974 | } | |
975 | return -EINVAL; | |
976 | } | |
977 | ||
978 | int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state) | |
979 | { | |
980 | struct power_state *pwrst; | |
981 | ||
982 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
983 | if (pwrst->pwrdm == pwrdm) { | |
984 | pwrst->next_state = state; | |
985 | return 0; | |
986 | } | |
987 | } | |
988 | return -EINVAL; | |
989 | } | |
990 | ||
a23456e9 | 991 | static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) |
8bd22949 KH |
992 | { |
993 | struct power_state *pwrst; | |
994 | ||
995 | if (!pwrdm->pwrsts) | |
996 | return 0; | |
997 | ||
d3d381c6 | 998 | pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); |
8bd22949 KH |
999 | if (!pwrst) |
1000 | return -ENOMEM; | |
1001 | pwrst->pwrdm = pwrdm; | |
1002 | pwrst->next_state = PWRDM_POWER_RET; | |
1003 | list_add(&pwrst->node, &pwrst_list); | |
1004 | ||
1005 | if (pwrdm_has_hdwr_sar(pwrdm)) | |
1006 | pwrdm_enable_hdwr_sar(pwrdm); | |
1007 | ||
1008 | return set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); | |
1009 | } | |
1010 | ||
1011 | /* | |
1012 | * Enable hw supervised mode for all clockdomains if it's | |
1013 | * supported. Initiate sleep transition for other clockdomains, if | |
1014 | * they are not used | |
1015 | */ | |
a23456e9 | 1016 | static int __init clkdms_setup(struct clockdomain *clkdm, void *unused) |
8bd22949 KH |
1017 | { |
1018 | if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO) | |
1019 | omap2_clkdm_allow_idle(clkdm); | |
1020 | else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP && | |
1021 | atomic_read(&clkdm->usecount) == 0) | |
1022 | omap2_clkdm_sleep(clkdm); | |
1023 | return 0; | |
1024 | } | |
1025 | ||
3231fc88 RN |
1026 | void omap_push_sram_idle(void) |
1027 | { | |
1028 | _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend, | |
1029 | omap34xx_cpu_suspend_sz); | |
27d59a4a TK |
1030 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) |
1031 | _omap_save_secure_sram = omap_sram_push(save_secure_ram_context, | |
1032 | save_secure_ram_context_sz); | |
3231fc88 RN |
1033 | } |
1034 | ||
7cc515f7 | 1035 | static int __init omap3_pm_init(void) |
8bd22949 KH |
1036 | { |
1037 | struct power_state *pwrst, *tmp; | |
1038 | int ret; | |
1039 | ||
1040 | if (!cpu_is_omap34xx()) | |
1041 | return -ENODEV; | |
1042 | ||
1043 | printk(KERN_ERR "Power Management for TI OMAP3.\n"); | |
1044 | ||
1045 | /* XXX prcm_setup_regs needs to be before enabling hw | |
1046 | * supervised mode for powerdomains */ | |
1047 | prcm_setup_regs(); | |
1048 | ||
1049 | ret = request_irq(INT_34XX_PRCM_MPU_IRQ, | |
1050 | (irq_handler_t)prcm_interrupt_handler, | |
1051 | IRQF_DISABLED, "prcm", NULL); | |
1052 | if (ret) { | |
1053 | printk(KERN_ERR "request_irq failed to register for 0x%x\n", | |
1054 | INT_34XX_PRCM_MPU_IRQ); | |
1055 | goto err1; | |
1056 | } | |
1057 | ||
a23456e9 | 1058 | ret = pwrdm_for_each(pwrdms_setup, NULL); |
8bd22949 KH |
1059 | if (ret) { |
1060 | printk(KERN_ERR "Failed to setup powerdomains\n"); | |
1061 | goto err2; | |
1062 | } | |
1063 | ||
a23456e9 | 1064 | (void) clkdm_for_each(clkdms_setup, NULL); |
8bd22949 KH |
1065 | |
1066 | mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); | |
1067 | if (mpu_pwrdm == NULL) { | |
1068 | printk(KERN_ERR "Failed to get mpu_pwrdm\n"); | |
1069 | goto err2; | |
1070 | } | |
1071 | ||
fa3c2a4f RN |
1072 | neon_pwrdm = pwrdm_lookup("neon_pwrdm"); |
1073 | per_pwrdm = pwrdm_lookup("per_pwrdm"); | |
1074 | core_pwrdm = pwrdm_lookup("core_pwrdm"); | |
c16c3f67 | 1075 | cam_pwrdm = pwrdm_lookup("cam_pwrdm"); |
fa3c2a4f | 1076 | |
3231fc88 | 1077 | omap_push_sram_idle(); |
10f90ed2 | 1078 | #ifdef CONFIG_SUSPEND |
8bd22949 | 1079 | suspend_set_ops(&omap_pm_ops); |
10f90ed2 | 1080 | #endif /* CONFIG_SUSPEND */ |
8bd22949 KH |
1081 | |
1082 | pm_idle = omap3_pm_idle; | |
1083 | ||
fa3c2a4f RN |
1084 | pwrdm_add_wkdep(neon_pwrdm, mpu_pwrdm); |
1085 | /* | |
1086 | * REVISIT: This wkdep is only necessary when GPIO2-6 are enabled for | |
1087 | * IO-pad wakeup. Otherwise it will unnecessarily waste power | |
1088 | * waking up PER with every CORE wakeup - see | |
1089 | * http://marc.info/?l=linux-omap&m=121852150710062&w=2 | |
1090 | */ | |
1091 | pwrdm_add_wkdep(per_pwrdm, core_pwrdm); | |
1092 | ||
27d59a4a TK |
1093 | if (omap_type() != OMAP2_DEVICE_TYPE_GP) { |
1094 | omap3_secure_ram_storage = | |
1095 | kmalloc(0x803F, GFP_KERNEL); | |
1096 | if (!omap3_secure_ram_storage) | |
1097 | printk(KERN_ERR "Memory allocation failed when" | |
1098 | "allocating for secure sram context\n"); | |
9d97140b TK |
1099 | |
1100 | local_irq_disable(); | |
1101 | local_fiq_disable(); | |
1102 | ||
1103 | omap_dma_global_context_save(); | |
1104 | omap3_save_secure_ram_context(PWRDM_POWER_ON); | |
1105 | omap_dma_global_context_restore(); | |
1106 | ||
1107 | local_irq_enable(); | |
1108 | local_fiq_enable(); | |
27d59a4a | 1109 | } |
27d59a4a | 1110 | |
9d97140b | 1111 | omap3_save_scratchpad_contents(); |
8bd22949 KH |
1112 | err1: |
1113 | return ret; | |
1114 | err2: | |
1115 | free_irq(INT_34XX_PRCM_MPU_IRQ, NULL); | |
1116 | list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) { | |
1117 | list_del(&pwrst->node); | |
1118 | kfree(pwrst); | |
1119 | } | |
1120 | return ret; | |
1121 | } | |
1122 | ||
1123 | late_initcall(omap3_pm_init); |