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ARM: OMAP: Split plat/cpu.h into local soc.h for mach-omap1 and mach-omap2
[deliverable/linux.git] / arch / arm / mach-omap2 / pm34xx.c
CommitLineData
8bd22949
KH		 1/*
2 * OMAP3 Power Management Routines
3 *
4 * Copyright (C) 2006-2008 Nokia Corporation
5 * Tony Lindgren <tony@atomide.com>
6 * Jouni Hogander
7 *
2f5939c3
RN		 8 * Copyright (C) 2007 Texas Instruments, Inc.
9 * Rajendra Nayak <rnayak@ti.com>
10 *
8bd22949
KH		 11 * Copyright (C) 2005 Texas Instruments, Inc.
12 * Richard Woodruff <r-woodruff2@ti.com>
13 *
14 * Based on pm.c for omap1
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#include <linux/pm.h>
22#include <linux/suspend.h>
23#include <linux/interrupt.h>
24#include <linux/module.h>
25#include <linux/list.h>
26#include <linux/err.h>
27#include <linux/gpio.h>
c40552bc 28#include <linux/clk.h>
dccaad89 29#include <linux/delay.h>
5a0e3ad6 30#include <linux/slab.h>
4b25408f
TL		 31#include <linux/platform_data/gpio-omap.h>
32
5e7c58dc 33#include <trace/events/power.h>
8bd22949 34
2c74a0ce 35#include <asm/suspend.h>
9f97da78 36#include <asm/system_misc.h>
2c74a0ce 37
1540f214 38#include "clockdomain.h"
72e06d08 39#include "powerdomain.h"
2f5939c3 40#include <plat/prcm.h>
2b6c4e73 41#include <plat-omap/dma-omap.h>
8bd22949 42
622297fd
TL		 43#include "../plat-omap/sram.h"
44
e4c060db 45#include "soc.h"
4e65331c 46#include "common.h"
59fb659b 47#include "cm2xxx_3xxx.h"
8bd22949 48#include "cm-regbits-34xx.h"
99f0b8d6 49#include "gpmc.h"
8bd22949
KH		 50#include "prm-regbits-34xx.h"
51
59fb659b 52#include "prm2xxx_3xxx.h"
8bd22949 53#include "pm.h"
13a6fe0f 54#include "sdrc.h"
4814ced5 55#include "control.h"
13a6fe0f 56
8cdfd834
NM		 57/* pm34xx errata defined in pm.h */
58u16 pm34xx_errata;
59
8bd22949
KH		 60struct power_state {
61 struct powerdomain *pwrdm;
62 u32 next_state;
10f90ed2 63#ifdef CONFIG_SUSPEND
8bd22949 64 u32 saved_state;
10f90ed2 65#endif
8bd22949
KH		 66 struct list_head node;
67};
68
69static LIST_HEAD(pwrst_list);
70
27d59a4a 71static int (*_omap_save_secure_sram)(u32 *addr);
46e130d2 72void (*omap3_do_wfi_sram)(void);
27d59a4a 73
fa3c2a4f
RN		 74static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
75static struct powerdomain *core_pwrdm, *per_pwrdm;
3a7ec26b 76
2f5939c3
RN		 77static void omap3_core_save_context(void)
78{
596efe47 79 omap3_ctrl_save_padconf();
dccaad89
TK		 80
81 /*
82 * Force write last pad into memory, as this can fail in some
83521291 83 * cases according to errata 1.157, 1.185
dccaad89
TK		 84 */
85 omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
86 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
87
2f5939c3
RN		 88 /* Save the Interrupt controller context */
89 omap_intc_save_context();
90 /* Save the GPMC context */
91 omap3_gpmc_save_context();
92 /* Save the system control module context, padconf already save above*/
93 omap3_control_save_context();
f2d11858 94 omap_dma_global_context_save();
2f5939c3
RN		 95}
96
97static void omap3_core_restore_context(void)
98{
99 /* Restore the control module context, padconf restored by h/w */
100 omap3_control_restore_context();
101 /* Restore the GPMC context */
102 omap3_gpmc_restore_context();
103 /* Restore the interrupt controller context */
104 omap_intc_restore_context();
f2d11858 105 omap_dma_global_context_restore();
2f5939c3
RN		 106}
107
9d97140b
TK		 108/*
109 * FIXME: This function should be called before entering off-mode after
110 * OMAP3 secure services have been accessed. Currently it is only called
111 * once during boot sequence, but this works as we are not using secure
112 * services.
113 */
617fcc98 114static void omap3_save_secure_ram_context(void)
27d59a4a
TK		 115{
116 u32 ret;
617fcc98 117 int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
27d59a4a
TK		 118
119 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
27d59a4a
TK		 120 /*
121 * MPU next state must be set to POWER_ON temporarily,
122 * otherwise the WFI executed inside the ROM code
123 * will hang the system.
124 */
125 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
126 ret = _omap_save_secure_sram((u32 *)
127 __pa(omap3_secure_ram_storage));
617fcc98 128 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
27d59a4a
TK		 129 /* Following is for error tracking, it should not happen */
130 if (ret) {
98179856 131 pr_err("save_secure_sram() returns %08x\n", ret);
27d59a4a
TK		 132 while (1)
133 ;
134 }
135 }
136}
137
77da2d91
JH		 138/*
139 * PRCM Interrupt Handler Helper Function
140 *
141 * The purpose of this function is to clear any wake-up events latched
142 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
143 * may occur whilst attempting to clear a PM_WKST_x register and thus
144 * set another bit in this register. A while loop is used to ensure
145 * that any peripheral wake-up events occurring while attempting to
146 * clear the PM_WKST_x are detected and cleared.
147 */
22f51371 148static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
8bd22949 149{
71a80775 150 u32 wkst, fclk, iclk, clken;
77da2d91
JH		 151 u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
152 u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
153 u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
5d805978
PW		 154 u16 grpsel_off = (regs == 3) ?
155 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
8cb0ac99 156 int c = 0;
8bd22949 157
c4d7e58f
PW		 158 wkst = omap2_prm_read_mod_reg(module, wkst_off);
159 wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
22f51371 160 wkst &= ~ignore_bits;
8bd22949 161 if (wkst) {
c4d7e58f
PW		 162 iclk = omap2_cm_read_mod_reg(module, iclk_off);
163 fclk = omap2_cm_read_mod_reg(module, fclk_off);
77da2d91 164 while (wkst) {
71a80775 165 clken = wkst;
c4d7e58f 166 omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
71a80775
VP		 167 /*
168 * For USBHOST, we don't know whether HOST1 or
169 * HOST2 woke us up, so enable both f-clocks
170 */
171 if (module == OMAP3430ES2_USBHOST_MOD)
172 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
c4d7e58f
PW		 173 omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
174 omap2_prm_write_mod_reg(wkst, module, wkst_off);
175 wkst = omap2_prm_read_mod_reg(module, wkst_off);
22f51371 176 wkst &= ~ignore_bits;
8cb0ac99 177 c++;
77da2d91 178 }
c4d7e58f
PW		 179 omap2_cm_write_mod_reg(iclk, module, iclk_off);
180 omap2_cm_write_mod_reg(fclk, module, fclk_off);
8bd22949 181 }
8cb0ac99
PW		 182
183 return c;
184}
185
22f51371 186static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
8cb0ac99
PW		 187{
188 int c;
189
22f51371
TK		 190 c = prcm_clear_mod_irqs(WKUP_MOD, 1,
191 ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
8cb0ac99 192
22f51371 193 return c ? IRQ_HANDLED : IRQ_NONE;
77da2d91 194}
8bd22949 195
22f51371 196static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
77da2d91 197{
22f51371 198 int c;
d6290a3e 199
22f51371
TK		 200 /*
201 * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
202 * these are handled in a separate handler to avoid acking
203 * IO events before parsing in mux code
204 */
205 c = prcm_clear_mod_irqs(WKUP_MOD, 1,
206 OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
207 c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
208 c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
209 if (omap_rev() > OMAP3430_REV_ES1_0) {
210 c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
211 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
212 }
8bd22949 213
22f51371 214 return c ? IRQ_HANDLED : IRQ_NONE;
8bd22949
KH		 215}
216
cbe26349
RK		 217static void omap34xx_save_context(u32 *save)
218{
219 u32 val;
220
221 /* Read Auxiliary Control Register */
222 asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
223 *save++ = 1;
224 *save++ = val;
225
226 /* Read L2 AUX ctrl register */
227 asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
228 *save++ = 1;
229 *save++ = val;
230}
231
29cb3cd2 232static int omap34xx_do_sram_idle(unsigned long save_state)
57f277b0 233{
cbe26349 234 omap34xx_cpu_suspend(save_state);
29cb3cd2 235 return 0;
57f277b0
RN		 236}
237
99e6a4d2 238void omap_sram_idle(void)
8bd22949
KH		 239{
240 /* Variable to tell what needs to be saved and restored
241 * in omap_sram_idle*/
242 /* save_state = 0 => Nothing to save and restored */
243 /* save_state = 1 => Only L1 and logic lost */
244 /* save_state = 2 => Only L2 lost */
245 /* save_state = 3 => L1, L2 and logic lost */
fa3c2a4f
RN		 246 int save_state = 0;
247 int mpu_next_state = PWRDM_POWER_ON;
248 int per_next_state = PWRDM_POWER_ON;
249 int core_next_state = PWRDM_POWER_ON;
72e06d08 250 int per_going_off;
eeb3711b 251 int core_prev_state;
13a6fe0f 252 u32 sdrc_pwr = 0;
8bd22949 253
8bd22949
KH		 254 mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
255 switch (mpu_next_state) {
fa3c2a4f 256 case PWRDM_POWER_ON:
8bd22949
KH		 257 case PWRDM_POWER_RET:
258 /* No need to save context */
259 save_state = 0;
260 break;
61255ab9
RN		 261 case PWRDM_POWER_OFF:
262 save_state = 3;
263 break;
8bd22949
KH		 264 default:
265 /* Invalid state */
98179856 266 pr_err("Invalid mpu state in sram_idle\n");
8bd22949
KH		 267 return;
268 }
fe617af7 269
fa3c2a4f
RN		 270 /* NEON control */
271 if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
7139178e 272 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
fa3c2a4f 273
40742fa8 274 /* Enable IO-PAD and IO-CHAIN wakeups */
658ce97e 275 per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
ecf157d0 276 core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
40742fa8 277
e0e29fd7 278 pwrdm_pre_transition(NULL);
ff2f8e5f 279
40742fa8 280 /* PER */
658ce97e 281 if (per_next_state < PWRDM_POWER_ON) {
72e06d08 282 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
72e06d08 283 omap2_gpio_prepare_for_idle(per_going_off);
658ce97e
KH		 284 }
285
286 /* CORE */
fa3c2a4f 287 if (core_next_state < PWRDM_POWER_ON) {
2f5939c3
RN		 288 if (core_next_state == PWRDM_POWER_OFF) {
289 omap3_core_save_context();
f0611a5c 290 omap3_cm_save_context();
2f5939c3 291 }
fa3c2a4f 292 }
40742fa8 293
f18cc2ff 294 omap3_intc_prepare_idle();
8bd22949 295
13a6fe0f 296 /*
30474544
PW		 297 * On EMU/HS devices ROM code restores a SRDC value
298 * from scratchpad which has automatic self refresh on timeout
299 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
300 * Hence store/restore the SDRC_POWER register here.
301 */
302 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
303 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
304 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
f265dc4c 305 core_next_state == PWRDM_POWER_OFF)
13a6fe0f 306 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
13a6fe0f 307
61255ab9 308 /*
076f2cc4
RK		 309 * omap3_arm_context is the location where some ARM context
310 * get saved. The rest is placed on the stack, and restored
311 * from there before resuming.
61255ab9 312 */
cbe26349
RK		 313 if (save_state)
314 omap34xx_save_context(omap3_arm_context);
076f2cc4 315 if (save_state == 1 || save_state == 3)
2c74a0ce 316 cpu_suspend(save_state, omap34xx_do_sram_idle);
076f2cc4
RK		 317 else
318 omap34xx_do_sram_idle(save_state);
8bd22949 319
f265dc4c 320 /* Restore normal SDRC POWER settings */
30474544
PW		 321 if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
322 (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
323 omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
13a6fe0f
TK		 324 core_next_state == PWRDM_POWER_OFF)
325 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
326
658ce97e 327 /* CORE */
fa3c2a4f 328 if (core_next_state < PWRDM_POWER_ON) {
2f5939c3
RN		 329 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
330 if (core_prev_state == PWRDM_POWER_OFF) {
331 omap3_core_restore_context();
f0611a5c 332 omap3_cm_restore_context();
2f5939c3 333 omap3_sram_restore_context();
8a917d2f 334 omap2_sms_restore_context();
2f5939c3 335 }
658ce97e 336 if (core_next_state == PWRDM_POWER_OFF)
c4d7e58f 337 omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
658ce97e
KH		 338 OMAP3430_GR_MOD,
339 OMAP3_PRM_VOLTCTRL_OFFSET);
340 }
f18cc2ff 341 omap3_intc_resume_idle();
658ce97e 342
e0e29fd7
KH		 343 pwrdm_post_transition(NULL);
344
658ce97e 345 /* PER */
e0e29fd7 346 if (per_next_state < PWRDM_POWER_ON)
43ffcd9a 347 omap2_gpio_resume_after_idle();
8bd22949
KH		 348}
349
8bd22949
KH		 350static void omap3_pm_idle(void)
351{
8bd22949
KH		 352 local_fiq_disable();
353
0bcd24b0 354 if (omap_irq_pending())
8bd22949
KH		 355 goto out;
356
5e7c58dc
JP		 357 trace_power_start(POWER_CSTATE, 1, smp_processor_id());
358 trace_cpu_idle(1, smp_processor_id());
359
8bd22949
KH		 360 omap_sram_idle();
361
5e7c58dc
JP		 362 trace_power_end(smp_processor_id());
363 trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
364
8bd22949
KH		 365out:
366 local_fiq_enable();
8bd22949
KH		 367}
368
10f90ed2 369#ifdef CONFIG_SUSPEND
8bd22949
KH		 370static int omap3_pm_suspend(void)
371{
372 struct power_state *pwrst;
373 int state, ret = 0;
374
375 /* Read current next_pwrsts */
376 list_for_each_entry(pwrst, &pwrst_list, node)
377 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
378 /* Set ones wanted by suspend */
379 list_for_each_entry(pwrst, &pwrst_list, node) {
eb6a2c75 380 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
8bd22949
KH		 381 goto restore;
382 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
383 goto restore;
384 }
385
2bbe3af3
TK		 386 omap3_intc_suspend();
387
8bd22949
KH		 388 omap_sram_idle();
389
390restore:
391 /* Restore next_pwrsts */
392 list_for_each_entry(pwrst, &pwrst_list, node) {
8bd22949
KH		 393 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
394 if (state > pwrst->next_state) {
7852ec05
PW		 395 pr_info("Powerdomain (%s) didn't enter target state %d\n",
396 pwrst->pwrdm->name, pwrst->next_state);
8bd22949
KH		 397 ret = -1;
398 }
eb6a2c75 399 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
8bd22949
KH		 400 }
401 if (ret)
98179856 402 pr_err("Could not enter target state in pm_suspend\n");
8bd22949 403 else
98179856 404 pr_info("Successfully put all powerdomains to target state\n");
8bd22949
KH		 405
406 return ret;
407}
408
10f90ed2 409#endif /* CONFIG_SUSPEND */
8bd22949 410
1155e426
KH		 411
412/**
413 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
414 * retention
415 *
416 * In cases where IVA2 is activated by bootcode, it may prevent
417 * full-chip retention or off-mode because it is not idle. This
418 * function forces the IVA2 into idle state so it can go
419 * into retention/off and thus allow full-chip retention/off.
420 *
421 **/
422static void __init omap3_iva_idle(void)
423{
424 /* ensure IVA2 clock is disabled */
c4d7e58f 425 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
1155e426
KH		 426
427 /* if no clock activity, nothing else to do */
c4d7e58f 428 if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
1155e426
KH		 429 OMAP3430_CLKACTIVITY_IVA2_MASK))
430 return;
431
432 /* Reset IVA2 */
c4d7e58f 433 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
2bc4ef71
PW		 434 OMAP3430_RST2_IVA2_MASK |
435 OMAP3430_RST3_IVA2_MASK,
37903009 436 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
1155e426
KH		 437
438 /* Enable IVA2 clock */
c4d7e58f 439 omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
1155e426
KH		 440 OMAP3430_IVA2_MOD, CM_FCLKEN);
441
442 /* Set IVA2 boot mode to 'idle' */
443 omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
444 OMAP343X_CONTROL_IVA2_BOOTMOD);
445
446 /* Un-reset IVA2 */
c4d7e58f 447 omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
1155e426
KH		 448
449 /* Disable IVA2 clock */
c4d7e58f 450 omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
1155e426
KH		 451
452 /* Reset IVA2 */
c4d7e58f 453 omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
2bc4ef71
PW		 454 OMAP3430_RST2_IVA2_MASK |
455 OMAP3430_RST3_IVA2_MASK,
37903009 456 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
1155e426
KH		 457}
458
8111b221 459static void __init omap3_d2d_idle(void)
8bd22949 460{
8111b221
KH		 461 u16 mask, padconf;
462
463 /* In a stand alone OMAP3430 where there is not a stacked
464 * modem for the D2D Idle Ack and D2D MStandby must be pulled
465 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
466 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
467 mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
468 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
469 padconf |= mask;
470 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
471
472 padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
473 padconf |= mask;
474 omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
475
8bd22949 476 /* reset modem */
c4d7e58f 477 omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
2bc4ef71 478 OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
37903009 479 CORE_MOD, OMAP2_RM_RSTCTRL);
c4d7e58f 480 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
8111b221 481}
8bd22949 482
8111b221
KH		 483static void __init prcm_setup_regs(void)
484{
e5863689
G		 485 u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
486 OMAP3630_EN_UART4_MASK : 0;
487 u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
488 OMAP3630_GRPSEL_UART4_MASK : 0;
489
4ef70c06 490 /* XXX This should be handled by hwmod code or SCM init code */
2fd0f75c 491 omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
b296c811 492
8bd22949
KH		 493 /*
494 * Enable control of expternal oscillator through
495 * sys_clkreq. In the long run clock framework should
496 * take care of this.
497 */
c4d7e58f 498 omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
8bd22949
KH		 499 1 << OMAP_AUTOEXTCLKMODE_SHIFT,
500 OMAP3430_GR_MOD,
501 OMAP3_PRM_CLKSRC_CTRL_OFFSET);
502
503 /* setup wakup source */
c4d7e58f 504 omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
2fd0f75c 505 OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
8bd22949
KH		 506 WKUP_MOD, PM_WKEN);
507 /* No need to write EN_IO, that is always enabled */
c4d7e58f 508 omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
275f675c
PW		 509 OMAP3430_GRPSEL_GPT1_MASK |
510 OMAP3430_GRPSEL_GPT12_MASK,
8bd22949 511 WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
1155e426 512
b92c5721 513 /* Enable PM_WKEN to support DSS LPR */
c4d7e58f 514 omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
b92c5721
SV		 515 OMAP3430_DSS_MOD, PM_WKEN);
516
b427f92f 517 /* Enable wakeups in PER */
c4d7e58f 518 omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
e5863689 519 OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
2fd0f75c
PW		 520 OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
521 OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
522 OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
523 OMAP3430_EN_MCBSP4_MASK,
b427f92f 524 OMAP3430_PER_MOD, PM_WKEN);
eb350f74 525 /* and allow them to wake up MPU */
c4d7e58f 526 omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
e5863689 527 OMAP3430_GRPSEL_GPIO2_MASK |
275f675c
PW		 528 OMAP3430_GRPSEL_GPIO3_MASK |
529 OMAP3430_GRPSEL_GPIO4_MASK |
530 OMAP3430_GRPSEL_GPIO5_MASK |
531 OMAP3430_GRPSEL_GPIO6_MASK |
532 OMAP3430_GRPSEL_UART3_MASK |
533 OMAP3430_GRPSEL_MCBSP2_MASK |
534 OMAP3430_GRPSEL_MCBSP3_MASK |
535 OMAP3430_GRPSEL_MCBSP4_MASK,
eb350f74
KH		 536 OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
537
d3fd3290 538 /* Don't attach IVA interrupts */
a819c4f1
MG		 539 if (omap3_has_iva()) {
540 omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
541 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
542 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
543 omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
544 OMAP3430_PM_IVAGRPSEL);
545 }
d3fd3290 546
b1340d17 547 /* Clear any pending 'reset' flags */
c4d7e58f
PW		 548 omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
549 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
550 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
551 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
552 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
553 omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
554 omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
b1340d17 555
014c46db 556 /* Clear any pending PRCM interrupts */
c4d7e58f 557 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
014c46db 558
a819c4f1
MG		 559 if (omap3_has_iva())
560 omap3_iva_idle();
561
8111b221 562 omap3_d2d_idle();
8bd22949
KH		 563}
564
c40552bc
KH		 565void omap3_pm_off_mode_enable(int enable)
566{
567 struct power_state *pwrst;
568 u32 state;
569
570 if (enable)
571 state = PWRDM_POWER_OFF;
572 else
573 state = PWRDM_POWER_RET;
574
575 list_for_each_entry(pwrst, &pwrst_list, node) {
cc1b6028
EV		 576 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
577 pwrst->pwrdm == core_pwrdm &&
578 state == PWRDM_POWER_OFF) {
579 pwrst->next_state = PWRDM_POWER_RET;
e16b41bf 580 pr_warn("%s: Core OFF disabled due to errata i583\n",
cc1b6028
EV		 581 __func__);
582 } else {
583 pwrst->next_state = state;
584 }
585 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
c40552bc
KH		 586 }
587}
588
68d4778c
TK		 589int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
590{
591 struct power_state *pwrst;
592
593 list_for_each_entry(pwrst, &pwrst_list, node) {
594 if (pwrst->pwrdm == pwrdm)
595 return pwrst->next_state;
596 }
597 return -EINVAL;
598}
599
600int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
601{
602 struct power_state *pwrst;
603
604 list_for_each_entry(pwrst, &pwrst_list, node) {
605 if (pwrst->pwrdm == pwrdm) {
606 pwrst->next_state = state;
607 return 0;
608 }
609 }
610 return -EINVAL;
611}
612
a23456e9 613static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
8bd22949
KH		 614{
615 struct power_state *pwrst;
616
617 if (!pwrdm->pwrsts)
618 return 0;
619
d3d381c6 620 pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
8bd22949
KH		 621 if (!pwrst)
622 return -ENOMEM;
623 pwrst->pwrdm = pwrdm;
624 pwrst->next_state = PWRDM_POWER_RET;
625 list_add(&pwrst->node, &pwrst_list);
626
627 if (pwrdm_has_hdwr_sar(pwrdm))
628 pwrdm_enable_hdwr_sar(pwrdm);
629
eb6a2c75 630 return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
8bd22949
KH		 631}
632
46e130d2
JP		 633/*
634 * Push functions to SRAM
635 *
636 * The minimum set of functions is pushed to SRAM for execution:
637 * - omap3_do_wfi for erratum i581 WA,
638 * - save_secure_ram_context for security extensions.
639 */
3231fc88
RN		 640void omap_push_sram_idle(void)
641{
46e130d2
JP		 642 omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);
643
27d59a4a
TK		 644 if (omap_type() != OMAP2_DEVICE_TYPE_GP)
645 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
646 save_secure_ram_context_sz);
3231fc88
RN		 647}
648
8cdfd834
NM		 649static void __init pm_errata_configure(void)
650{
c4236d2e 651 if (cpu_is_omap3630()) {
458e999e 652 pm34xx_errata |= PM_RTA_ERRATUM_i608;
c4236d2e
PDS		 653 /* Enable the l2 cache toggling in sleep logic */
654 enable_omap3630_toggle_l2_on_restore();
cc1b6028
EV		 655 if (omap_rev() < OMAP3630_REV_ES1_2)
656 pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
c4236d2e 657 }
8cdfd834
NM		 658}
659
bbd707ac 660int __init omap3_pm_init(void)
8bd22949
KH		 661{
662 struct power_state *pwrst, *tmp;
eeb3711b 663 struct clockdomain *neon_clkdm, *mpu_clkdm;
8bd22949
KH		 664 int ret;
665
b02b9172
PW		 666 if (!omap3_has_io_chain_ctrl())
667 pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");
668
8cdfd834
NM		 669 pm_errata_configure();
670
8bd22949
KH		 671 /* XXX prcm_setup_regs needs to be before enabling hw
672 * supervised mode for powerdomains */
673 prcm_setup_regs();
674
22f51371
TK		 675 ret = request_irq(omap_prcm_event_to_irq("wkup"),
676 _prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);
677
678 if (ret) {
679 pr_err("pm: Failed to request pm_wkup irq\n");
680 goto err1;
681 }
682
683 /* IO interrupt is shared with mux code */
684 ret = request_irq(omap_prcm_event_to_irq("io"),
685 _prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
686 omap3_pm_init);
99b59df0 687 enable_irq(omap_prcm_event_to_irq("io"));
22f51371 688
8bd22949 689 if (ret) {
22f51371 690 pr_err("pm: Failed to request pm_io irq\n");
ce229c5d 691 goto err2;
8bd22949
KH		 692 }
693
a23456e9 694 ret = pwrdm_for_each(pwrdms_setup, NULL);
8bd22949 695 if (ret) {
98179856 696 pr_err("Failed to setup powerdomains\n");
ce229c5d 697 goto err3;
8bd22949
KH		 698 }
699
92206fd2 700 (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
8bd22949
KH		 701
702 mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
703 if (mpu_pwrdm == NULL) {
98179856 704 pr_err("Failed to get mpu_pwrdm\n");
ce229c5d
MG		 705 ret = -EINVAL;
706 goto err3;
8bd22949
KH		 707 }
708
fa3c2a4f
RN		 709 neon_pwrdm = pwrdm_lookup("neon_pwrdm");
710 per_pwrdm = pwrdm_lookup("per_pwrdm");
711 core_pwrdm = pwrdm_lookup("core_pwrdm");
712
55ed9694
PW		 713 neon_clkdm = clkdm_lookup("neon_clkdm");
714 mpu_clkdm = clkdm_lookup("mpu_clkdm");
55ed9694 715
10f90ed2 716#ifdef CONFIG_SUSPEND
1416408d
PW		 717 omap_pm_suspend = omap3_pm_suspend;
718#endif
8bd22949 719
0bcd24b0 720 arm_pm_idle = omap3_pm_idle;
0343371e 721 omap3_idle_init();
8bd22949 722
458e999e
NM		 723 /*
724 * RTA is disabled during initialization as per erratum i608
725 * it is safer to disable RTA by the bootloader, but we would like
726 * to be doubly sure here and prevent any mishaps.
727 */
728 if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
729 omap3630_ctrl_disable_rta();
730
55ed9694 731 clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
27d59a4a
TK		 732 if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
733 omap3_secure_ram_storage =
734 kmalloc(0x803F, GFP_KERNEL);
735 if (!omap3_secure_ram_storage)
7852ec05 736 pr_err("Memory allocation failed when allocating for secure sram context\n");
9d97140b
TK		 737
738 local_irq_disable();
739 local_fiq_disable();
740
741 omap_dma_global_context_save();
617fcc98 742 omap3_save_secure_ram_context();
9d97140b
TK		 743 omap_dma_global_context_restore();
744
745 local_irq_enable();
746 local_fiq_enable();
27d59a4a 747 }
27d59a4a 748
9d97140b 749 omap3_save_scratchpad_contents();
8bd22949 750 return ret;
ce229c5d
MG		 751
752err3:
8bd22949
KH		 753 list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
754 list_del(&pwrst->node);
755 kfree(pwrst);
756 }
ce229c5d
MG		 757 free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
758err2:
759 free_irq(omap_prcm_event_to_irq("wkup"), NULL);
760err1:
8bd22949
KH		 761 return ret;
762}
Linux kernel - Deliverables
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