Commit | Line | Data |
---|---|---|
5643aebb | 1 | /* |
705814b5 | 2 | * OMAP4+ Power Management Routines |
5643aebb | 3 | * |
705814b5 | 4 | * Copyright (C) 2010-2013 Texas Instruments, Inc. |
5643aebb | 5 | * Rajendra Nayak <rnayak@ti.com> |
e44f9a77 | 6 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
5643aebb RN |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/pm.h> | |
14 | #include <linux/suspend.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/slab.h> | |
9f97da78 | 19 | #include <asm/system_misc.h> |
5643aebb | 20 | |
e4c060db | 21 | #include "soc.h" |
4e65331c | 22 | #include "common.h" |
3c50729b | 23 | #include "clockdomain.h" |
72e06d08 | 24 | #include "powerdomain.h" |
e44f9a77 | 25 | #include "pm.h" |
5643aebb | 26 | |
de70af49 NM |
27 | u16 pm44xx_errata; |
28 | ||
5643aebb RN |
29 | struct power_state { |
30 | struct powerdomain *pwrdm; | |
31 | u32 next_state; | |
32 | #ifdef CONFIG_SUSPEND | |
33 | u32 saved_state; | |
3ba2a739 | 34 | u32 saved_logic_state; |
5643aebb RN |
35 | #endif |
36 | struct list_head node; | |
37 | }; | |
38 | ||
39 | static LIST_HEAD(pwrst_list); | |
40 | ||
41 | #ifdef CONFIG_SUSPEND | |
5643aebb RN |
42 | static int omap4_pm_suspend(void) |
43 | { | |
e44f9a77 SS |
44 | struct power_state *pwrst; |
45 | int state, ret = 0; | |
46 | u32 cpu_id = smp_processor_id(); | |
47 | ||
48 | /* Save current powerdomain state */ | |
49 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
50 | pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); | |
3ba2a739 | 51 | pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm); |
e44f9a77 SS |
52 | } |
53 | ||
54 | /* Set targeted power domain states by suspend */ | |
55 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
56 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); | |
3ba2a739 | 57 | pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF); |
e44f9a77 SS |
58 | } |
59 | ||
60 | /* | |
61 | * For MPUSS to hit power domain retention(CSWR or OSWR), | |
62 | * CPU0 and CPU1 power domains need to be in OFF or DORMANT state, | |
63 | * since CPU power domain CSWR is not supported by hardware | |
64 | * Only master CPU follows suspend path. All other CPUs follow | |
65 | * CPU hotplug path in system wide suspend. On OMAP4, CPU power | |
66 | * domain CSWR is not supported by hardware. | |
67 | * More details can be found in OMAP4430 TRM section 4.3.4.2. | |
68 | */ | |
69 | omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF); | |
70 | ||
71 | /* Restore next powerdomain state */ | |
72 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
73 | state = pwrdm_read_prev_pwrst(pwrst->pwrdm); | |
74 | if (state > pwrst->next_state) { | |
7852ec05 PW |
75 | pr_info("Powerdomain (%s) didn't enter target state %d\n", |
76 | pwrst->pwrdm->name, pwrst->next_state); | |
e44f9a77 SS |
77 | ret = -1; |
78 | } | |
79 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); | |
3ba2a739 | 80 | pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state); |
e44f9a77 | 81 | } |
60480098 | 82 | if (ret) { |
e44f9a77 | 83 | pr_crit("Could not enter target state in pm_suspend\n"); |
60480098 RN |
84 | /* |
85 | * OMAP4 chip PM currently works only with certain (newer) | |
86 | * versions of bootloaders. This is due to missing code in the | |
87 | * kernel to properly reset and initialize some devices. | |
88 | * Warn the user about the bootloader version being one of the | |
89 | * possible causes. | |
90 | * http://www.spinics.net/lists/arm-kernel/msg218641.html | |
91 | */ | |
92 | pr_warn("A possible cause could be an old bootloader - try u-boot >= v2012.07\n"); | |
93 | } else { | |
e44f9a77 | 94 | pr_info("Successfully put all powerdomains to target state\n"); |
60480098 | 95 | } |
e44f9a77 | 96 | |
5643aebb RN |
97 | return 0; |
98 | } | |
2e4b62dc DG |
99 | #else |
100 | #define omap4_pm_suspend NULL | |
5643aebb RN |
101 | #endif /* CONFIG_SUSPEND */ |
102 | ||
103 | static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) | |
104 | { | |
105 | struct power_state *pwrst; | |
106 | ||
107 | if (!pwrdm->pwrsts) | |
108 | return 0; | |
109 | ||
e44f9a77 SS |
110 | /* |
111 | * Skip CPU0 and CPU1 power domains. CPU1 is programmed | |
112 | * through hotplug path and CPU0 explicitly programmed | |
113 | * further down in the code path | |
114 | */ | |
115 | if (!strncmp(pwrdm->name, "cpu", 3)) | |
116 | return 0; | |
117 | ||
5643aebb RN |
118 | pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); |
119 | if (!pwrst) | |
120 | return -ENOMEM; | |
e44f9a77 | 121 | |
5643aebb | 122 | pwrst->pwrdm = pwrdm; |
e44f9a77 | 123 | pwrst->next_state = PWRDM_POWER_RET; |
5643aebb RN |
124 | list_add(&pwrst->node, &pwrst_list); |
125 | ||
e44f9a77 | 126 | return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); |
5643aebb RN |
127 | } |
128 | ||
72826b9f SS |
129 | /** |
130 | * omap_default_idle - OMAP4 default ilde routine.' | |
131 | * | |
132 | * Implements OMAP4 memory, IO ordering requirements which can't be addressed | |
62006324 PB |
133 | * with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPU_IDLE and |
134 | * by secondary CPU with CONFIG_CPU_IDLE. | |
72826b9f SS |
135 | */ |
136 | static void omap_default_idle(void) | |
137 | { | |
72826b9f | 138 | omap_do_wfi(); |
72826b9f SS |
139 | } |
140 | ||
5643aebb | 141 | /** |
705814b5 | 142 | * omap4_init_static_deps - Add OMAP4 static dependencies |
5643aebb | 143 | * |
705814b5 SS |
144 | * Add needed static clockdomain dependencies on OMAP4 devices. |
145 | * Return: 0 on success or 'err' on failures | |
5643aebb | 146 | */ |
705814b5 | 147 | static inline int omap4_init_static_deps(void) |
5643aebb | 148 | { |
6cf38956 | 149 | struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm; |
d5336a5a | 150 | struct clockdomain *ducati_clkdm, *l3_2_clkdm; |
705814b5 | 151 | int ret = 0; |
5643aebb | 152 | |
361b02f3 SS |
153 | if (omap_rev() == OMAP4430_REV_ES1_0) { |
154 | WARN(1, "Power Management not supported on OMAP4430 ES1.0\n"); | |
155 | return -ENODEV; | |
156 | } | |
157 | ||
5643aebb | 158 | pr_err("Power Management for TI OMAP4.\n"); |
60480098 RN |
159 | /* |
160 | * OMAP4 chip PM currently works only with certain (newer) | |
161 | * versions of bootloaders. This is due to missing code in the | |
162 | * kernel to properly reset and initialize some devices. | |
163 | * http://www.spinics.net/lists/arm-kernel/msg218641.html | |
164 | */ | |
165 | pr_warn("OMAP4 PM: u-boot >= v2012.07 is required for full PM support\n"); | |
5643aebb | 166 | |
5643aebb RN |
167 | ret = pwrdm_for_each(pwrdms_setup, NULL); |
168 | if (ret) { | |
169 | pr_err("Failed to setup powerdomains\n"); | |
705814b5 | 170 | return ret; |
5643aebb | 171 | } |
5643aebb | 172 | |
12f27826 SS |
173 | /* |
174 | * The dynamic dependency between MPUSS -> MEMIF and | |
175 | * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as | |
176 | * expected. The hardware recommendation is to enable static | |
177 | * dependencies for these to avoid system lock ups or random crashes. | |
705814b5 SS |
178 | * The L4 wakeup depedency is added to workaround the OCP sync hardware |
179 | * BUG with 32K synctimer which lead to incorrect timer value read | |
180 | * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which | |
181 | * are part of L4 wakeup clockdomain. | |
12f27826 SS |
182 | */ |
183 | mpuss_clkdm = clkdm_lookup("mpuss_clkdm"); | |
184 | emif_clkdm = clkdm_lookup("l3_emif_clkdm"); | |
185 | l3_1_clkdm = clkdm_lookup("l3_1_clkdm"); | |
186 | l3_2_clkdm = clkdm_lookup("l3_2_clkdm"); | |
12f27826 | 187 | ducati_clkdm = clkdm_lookup("ducati_clkdm"); |
6cf38956 | 188 | if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) || |
d5336a5a | 189 | (!l3_2_clkdm) || (!ducati_clkdm)) |
705814b5 | 190 | return -EINVAL; |
12f27826 SS |
191 | |
192 | ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm); | |
193 | ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm); | |
194 | ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm); | |
12f27826 SS |
195 | ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm); |
196 | ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm); | |
197 | if (ret) { | |
7852ec05 | 198 | pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n"); |
705814b5 SS |
199 | return -EINVAL; |
200 | } | |
201 | ||
202 | return ret; | |
de70af49 NM |
203 | } |
204 | ||
205 | /** | |
206 | * omap4_pm_init_early - Does early initialization necessary for OMAP4+ devices | |
207 | * | |
208 | * Initializes basic stuff for power management functionality. | |
209 | */ | |
210 | int __init omap4_pm_init_early(void) | |
211 | { | |
212 | if (cpu_is_omap446x()) | |
213 | pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD; | |
214 | ||
215 | return 0; | |
705814b5 SS |
216 | } |
217 | ||
218 | /** | |
219 | * omap4_pm_init - Init routine for OMAP4+ devices | |
220 | * | |
221 | * Initializes all powerdomain and clockdomain target states | |
222 | * and all PRCM settings. | |
223 | * Return: Returns the error code returned by called functions. | |
224 | */ | |
225 | int __init omap4_pm_init(void) | |
226 | { | |
227 | int ret = 0; | |
228 | ||
229 | if (omap_rev() == OMAP4430_REV_ES1_0) { | |
230 | WARN(1, "Power Management not supported on OMAP4430 ES1.0\n"); | |
231 | return -ENODEV; | |
232 | } | |
233 | ||
234 | pr_info("Power Management for TI OMAP4+ devices.\n"); | |
235 | ||
236 | ret = pwrdm_for_each(pwrdms_setup, NULL); | |
237 | if (ret) { | |
238 | pr_err("Failed to setup powerdomains.\n"); | |
12f27826 SS |
239 | goto err2; |
240 | } | |
241 | ||
705814b5 SS |
242 | if (cpu_is_omap44xx()) { |
243 | ret = omap4_init_static_deps(); | |
244 | if (ret) | |
245 | goto err2; | |
246 | } | |
247 | ||
b2b9762f SS |
248 | ret = omap4_mpuss_init(); |
249 | if (ret) { | |
250 | pr_err("Failed to initialise OMAP4 MPUSS\n"); | |
251 | goto err2; | |
252 | } | |
253 | ||
92206fd2 | 254 | (void) clkdm_for_each(omap_pm_clkdms_setup, NULL); |
3c50729b | 255 | |
2e4b62dc | 256 | omap_common_suspend_init(omap4_pm_suspend); |
5643aebb | 257 | |
ae940913 | 258 | /* Overwrite the default cpu_do_idle() */ |
0bcd24b0 | 259 | arm_pm_idle = omap_default_idle; |
72826b9f | 260 | |
705814b5 SS |
261 | if (cpu_is_omap44xx()) |
262 | omap4_idle_init(); | |
98272660 | 263 | |
5643aebb RN |
264 | err2: |
265 | return ret; | |
266 | } |