Commit | Line | Data |
---|---|---|
5643aebb | 1 | /* |
705814b5 | 2 | * OMAP4+ Power Management Routines |
5643aebb | 3 | * |
705814b5 | 4 | * Copyright (C) 2010-2013 Texas Instruments, Inc. |
5643aebb | 5 | * Rajendra Nayak <rnayak@ti.com> |
e44f9a77 | 6 | * Santosh Shilimkar <santosh.shilimkar@ti.com> |
5643aebb RN |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #include <linux/pm.h> | |
14 | #include <linux/suspend.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/err.h> | |
18 | #include <linux/slab.h> | |
9f97da78 | 19 | #include <asm/system_misc.h> |
5643aebb | 20 | |
e4c060db | 21 | #include "soc.h" |
4e65331c | 22 | #include "common.h" |
3c50729b | 23 | #include "clockdomain.h" |
72e06d08 | 24 | #include "powerdomain.h" |
e44f9a77 | 25 | #include "pm.h" |
5643aebb RN |
26 | |
27 | struct power_state { | |
28 | struct powerdomain *pwrdm; | |
29 | u32 next_state; | |
30 | #ifdef CONFIG_SUSPEND | |
31 | u32 saved_state; | |
3ba2a739 | 32 | u32 saved_logic_state; |
5643aebb RN |
33 | #endif |
34 | struct list_head node; | |
35 | }; | |
36 | ||
37 | static LIST_HEAD(pwrst_list); | |
38 | ||
39 | #ifdef CONFIG_SUSPEND | |
5643aebb RN |
40 | static int omap4_pm_suspend(void) |
41 | { | |
e44f9a77 SS |
42 | struct power_state *pwrst; |
43 | int state, ret = 0; | |
44 | u32 cpu_id = smp_processor_id(); | |
45 | ||
46 | /* Save current powerdomain state */ | |
47 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
48 | pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm); | |
3ba2a739 | 49 | pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm); |
e44f9a77 SS |
50 | } |
51 | ||
52 | /* Set targeted power domain states by suspend */ | |
53 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
54 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); | |
3ba2a739 | 55 | pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF); |
e44f9a77 SS |
56 | } |
57 | ||
58 | /* | |
59 | * For MPUSS to hit power domain retention(CSWR or OSWR), | |
60 | * CPU0 and CPU1 power domains need to be in OFF or DORMANT state, | |
61 | * since CPU power domain CSWR is not supported by hardware | |
62 | * Only master CPU follows suspend path. All other CPUs follow | |
63 | * CPU hotplug path in system wide suspend. On OMAP4, CPU power | |
64 | * domain CSWR is not supported by hardware. | |
65 | * More details can be found in OMAP4430 TRM section 4.3.4.2. | |
66 | */ | |
67 | omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF); | |
68 | ||
69 | /* Restore next powerdomain state */ | |
70 | list_for_each_entry(pwrst, &pwrst_list, node) { | |
71 | state = pwrdm_read_prev_pwrst(pwrst->pwrdm); | |
72 | if (state > pwrst->next_state) { | |
7852ec05 PW |
73 | pr_info("Powerdomain (%s) didn't enter target state %d\n", |
74 | pwrst->pwrdm->name, pwrst->next_state); | |
e44f9a77 SS |
75 | ret = -1; |
76 | } | |
77 | omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); | |
3ba2a739 | 78 | pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state); |
e44f9a77 | 79 | } |
60480098 | 80 | if (ret) { |
e44f9a77 | 81 | pr_crit("Could not enter target state in pm_suspend\n"); |
60480098 RN |
82 | /* |
83 | * OMAP4 chip PM currently works only with certain (newer) | |
84 | * versions of bootloaders. This is due to missing code in the | |
85 | * kernel to properly reset and initialize some devices. | |
86 | * Warn the user about the bootloader version being one of the | |
87 | * possible causes. | |
88 | * http://www.spinics.net/lists/arm-kernel/msg218641.html | |
89 | */ | |
90 | pr_warn("A possible cause could be an old bootloader - try u-boot >= v2012.07\n"); | |
91 | } else { | |
e44f9a77 | 92 | pr_info("Successfully put all powerdomains to target state\n"); |
60480098 | 93 | } |
e44f9a77 | 94 | |
5643aebb RN |
95 | return 0; |
96 | } | |
5643aebb RN |
97 | #endif /* CONFIG_SUSPEND */ |
98 | ||
99 | static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused) | |
100 | { | |
101 | struct power_state *pwrst; | |
102 | ||
103 | if (!pwrdm->pwrsts) | |
104 | return 0; | |
105 | ||
e44f9a77 SS |
106 | /* |
107 | * Skip CPU0 and CPU1 power domains. CPU1 is programmed | |
108 | * through hotplug path and CPU0 explicitly programmed | |
109 | * further down in the code path | |
110 | */ | |
111 | if (!strncmp(pwrdm->name, "cpu", 3)) | |
112 | return 0; | |
113 | ||
5643aebb RN |
114 | pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); |
115 | if (!pwrst) | |
116 | return -ENOMEM; | |
e44f9a77 | 117 | |
5643aebb | 118 | pwrst->pwrdm = pwrdm; |
e44f9a77 | 119 | pwrst->next_state = PWRDM_POWER_RET; |
5643aebb RN |
120 | list_add(&pwrst->node, &pwrst_list); |
121 | ||
e44f9a77 | 122 | return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state); |
5643aebb RN |
123 | } |
124 | ||
72826b9f SS |
125 | /** |
126 | * omap_default_idle - OMAP4 default ilde routine.' | |
127 | * | |
128 | * Implements OMAP4 memory, IO ordering requirements which can't be addressed | |
62006324 PB |
129 | * with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPU_IDLE and |
130 | * by secondary CPU with CONFIG_CPU_IDLE. | |
72826b9f SS |
131 | */ |
132 | static void omap_default_idle(void) | |
133 | { | |
72826b9f | 134 | omap_do_wfi(); |
72826b9f SS |
135 | } |
136 | ||
5643aebb | 137 | /** |
705814b5 | 138 | * omap4_init_static_deps - Add OMAP4 static dependencies |
5643aebb | 139 | * |
705814b5 SS |
140 | * Add needed static clockdomain dependencies on OMAP4 devices. |
141 | * Return: 0 on success or 'err' on failures | |
5643aebb | 142 | */ |
705814b5 | 143 | static inline int omap4_init_static_deps(void) |
5643aebb | 144 | { |
6cf38956 | 145 | struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm; |
d5336a5a | 146 | struct clockdomain *ducati_clkdm, *l3_2_clkdm; |
705814b5 | 147 | int ret = 0; |
5643aebb | 148 | |
361b02f3 SS |
149 | if (omap_rev() == OMAP4430_REV_ES1_0) { |
150 | WARN(1, "Power Management not supported on OMAP4430 ES1.0\n"); | |
151 | return -ENODEV; | |
152 | } | |
153 | ||
5643aebb | 154 | pr_err("Power Management for TI OMAP4.\n"); |
60480098 RN |
155 | /* |
156 | * OMAP4 chip PM currently works only with certain (newer) | |
157 | * versions of bootloaders. This is due to missing code in the | |
158 | * kernel to properly reset and initialize some devices. | |
159 | * http://www.spinics.net/lists/arm-kernel/msg218641.html | |
160 | */ | |
161 | pr_warn("OMAP4 PM: u-boot >= v2012.07 is required for full PM support\n"); | |
5643aebb | 162 | |
5643aebb RN |
163 | ret = pwrdm_for_each(pwrdms_setup, NULL); |
164 | if (ret) { | |
165 | pr_err("Failed to setup powerdomains\n"); | |
705814b5 | 166 | return ret; |
5643aebb | 167 | } |
5643aebb | 168 | |
12f27826 SS |
169 | /* |
170 | * The dynamic dependency between MPUSS -> MEMIF and | |
171 | * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as | |
172 | * expected. The hardware recommendation is to enable static | |
173 | * dependencies for these to avoid system lock ups or random crashes. | |
705814b5 SS |
174 | * The L4 wakeup depedency is added to workaround the OCP sync hardware |
175 | * BUG with 32K synctimer which lead to incorrect timer value read | |
176 | * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which | |
177 | * are part of L4 wakeup clockdomain. | |
12f27826 SS |
178 | */ |
179 | mpuss_clkdm = clkdm_lookup("mpuss_clkdm"); | |
180 | emif_clkdm = clkdm_lookup("l3_emif_clkdm"); | |
181 | l3_1_clkdm = clkdm_lookup("l3_1_clkdm"); | |
182 | l3_2_clkdm = clkdm_lookup("l3_2_clkdm"); | |
12f27826 | 183 | ducati_clkdm = clkdm_lookup("ducati_clkdm"); |
6cf38956 | 184 | if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) || |
d5336a5a | 185 | (!l3_2_clkdm) || (!ducati_clkdm)) |
705814b5 | 186 | return -EINVAL; |
12f27826 SS |
187 | |
188 | ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm); | |
189 | ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm); | |
190 | ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm); | |
12f27826 SS |
191 | ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm); |
192 | ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm); | |
193 | if (ret) { | |
7852ec05 | 194 | pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n"); |
705814b5 SS |
195 | return -EINVAL; |
196 | } | |
197 | ||
198 | return ret; | |
199 | } | |
200 | ||
201 | /** | |
202 | * omap4_pm_init - Init routine for OMAP4+ devices | |
203 | * | |
204 | * Initializes all powerdomain and clockdomain target states | |
205 | * and all PRCM settings. | |
206 | * Return: Returns the error code returned by called functions. | |
207 | */ | |
208 | int __init omap4_pm_init(void) | |
209 | { | |
210 | int ret = 0; | |
211 | ||
212 | if (omap_rev() == OMAP4430_REV_ES1_0) { | |
213 | WARN(1, "Power Management not supported on OMAP4430 ES1.0\n"); | |
214 | return -ENODEV; | |
215 | } | |
216 | ||
217 | pr_info("Power Management for TI OMAP4+ devices.\n"); | |
218 | ||
219 | ret = pwrdm_for_each(pwrdms_setup, NULL); | |
220 | if (ret) { | |
221 | pr_err("Failed to setup powerdomains.\n"); | |
12f27826 SS |
222 | goto err2; |
223 | } | |
224 | ||
705814b5 SS |
225 | if (cpu_is_omap44xx()) { |
226 | ret = omap4_init_static_deps(); | |
227 | if (ret) | |
228 | goto err2; | |
229 | } | |
230 | ||
b2b9762f SS |
231 | ret = omap4_mpuss_init(); |
232 | if (ret) { | |
233 | pr_err("Failed to initialise OMAP4 MPUSS\n"); | |
234 | goto err2; | |
235 | } | |
236 | ||
92206fd2 | 237 | (void) clkdm_for_each(omap_pm_clkdms_setup, NULL); |
3c50729b | 238 | |
5643aebb | 239 | #ifdef CONFIG_SUSPEND |
1416408d PW |
240 | omap_pm_suspend = omap4_pm_suspend; |
241 | #endif | |
5643aebb | 242 | |
ae940913 | 243 | /* Overwrite the default cpu_do_idle() */ |
0bcd24b0 | 244 | arm_pm_idle = omap_default_idle; |
72826b9f | 245 | |
705814b5 SS |
246 | if (cpu_is_omap44xx()) |
247 | omap4_idle_init(); | |
98272660 | 248 | |
5643aebb RN |
249 | err2: |
250 | return ret; | |
251 | } |