[deliverable/linux.git] / arch / arm / mach-omap2 / pm44xx.c

/*
 * OMAP4 Power Management Routines
 *
 * Copyright (C) 2010-2011 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
 * Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/pm.h>
#include <linux/suspend.h>
#include <linux/module.h>
#include <linux/list.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <asm/system_misc.h>

#include "common.h"
#include "clockdomain.h"
#include "powerdomain.h"
#include "pm.h"

struct power_state {
	struct powerdomain *pwrdm;
	u32 next_state;
#ifdef CONFIG_SUSPEND
	u32 saved_state;
	u32 saved_logic_state;
#endif
	struct list_head node;
};

static LIST_HEAD(pwrst_list);

#ifdef CONFIG_SUSPEND
static int omap4_pm_suspend(void)
{
	struct power_state *pwrst;
	int state, ret = 0;
	u32 cpu_id = smp_processor_id();

	/* Save current powerdomain state */
	list_for_each_entry(pwrst, &pwrst_list, node) {
		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
		pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm);
	}

	/* Set targeted power domain states by suspend */
	list_for_each_entry(pwrst, &pwrst_list, node) {
		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
		pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF);
	}

	/*
	 * For MPUSS to hit power domain retention(CSWR or OSWR),
	 * CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
	 * since CPU power domain CSWR is not supported by hardware
	 * Only master CPU follows suspend path. All other CPUs follow
	 * CPU hotplug path in system wide suspend. On OMAP4, CPU power
	 * domain CSWR is not supported by hardware.
	 * More details can be found in OMAP4430 TRM section 4.3.4.2.
	 */
	omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF);

	/* Restore next powerdomain state */
	list_for_each_entry(pwrst, &pwrst_list, node) {
		state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
		if (state > pwrst->next_state) {
			pr_info("Powerdomain (%s) didn't enter "
			       "target state %d\n",
			       pwrst->pwrdm->name, pwrst->next_state);
			ret = -1;
		}
		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
		pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
	}
	if (ret)
		pr_crit("Could not enter target state in pm_suspend\n");
	else
		pr_info("Successfully put all powerdomains to target state\n");

	return 0;
}
#endif /* CONFIG_SUSPEND */

static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
{
	struct power_state *pwrst;

	if (!pwrdm->pwrsts)
		return 0;

	/*
	 * Skip CPU0 and CPU1 power domains. CPU1 is programmed
	 * through hotplug path and CPU0 explicitly programmed
	 * further down in the code path
	 */
	if (!strncmp(pwrdm->name, "cpu", 3))
		return 0;

	/*
	 * FIXME: Remove this check when core retention is supported
	 * Only MPUSS power domain is added in the list.
	 */
	if (strcmp(pwrdm->name, "mpu_pwrdm"))
		return 0;

	pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
	if (!pwrst)
		return -ENOMEM;

	pwrst->pwrdm = pwrdm;
	pwrst->next_state = PWRDM_POWER_RET;
	list_add(&pwrst->node, &pwrst_list);

	return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
}

/**
 * omap_default_idle - OMAP4 default ilde routine.'
 *
 * Implements OMAP4 memory, IO ordering requirements which can't be addressed
 * with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPUIDLE and
 * by secondary CPU with CONFIG_CPUIDLE.
 */
static void omap_default_idle(void)
{
	local_fiq_disable();

	omap_do_wfi();

	local_fiq_enable();
}

/**
 * omap4_pm_init - Init routine for OMAP4 PM
 *
 * Initializes all powerdomain and clockdomain target states
 * and all PRCM settings.
 */
int __init omap4_pm_init(void)
{
	int ret;
	struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm, *l4wkup;
	struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm;

	if (omap_rev() == OMAP4430_REV_ES1_0) {
		WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
		return -ENODEV;
	}

	pr_err("Power Management for TI OMAP4.\n");

	ret = pwrdm_for_each(pwrdms_setup, NULL);
	if (ret) {
		pr_err("Failed to setup powerdomains\n");
		goto err2;
	}

	/*
	 * The dynamic dependency between MPUSS -> MEMIF and
	 * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
	 * expected. The hardware recommendation is to enable static
	 * dependencies for these to avoid system lock ups or random crashes.
	 * The L4 wakeup depedency is added to workaround the OCP sync hardware
	 * BUG with 32K synctimer which lead to incorrect timer value read
	 * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
	 * are part of L4 wakeup clockdomain.
	 */
	mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
	emif_clkdm = clkdm_lookup("l3_emif_clkdm");
	l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
	l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
	l4_per_clkdm = clkdm_lookup("l4_per_clkdm");
	l4wkup = clkdm_lookup("l4_wkup_clkdm");
	ducati_clkdm = clkdm_lookup("ducati_clkdm");
	if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) || (!l4wkup) ||
		(!l3_2_clkdm) || (!ducati_clkdm) || (!l4_per_clkdm))
		goto err2;

	ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
	ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
	ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
	ret |= clkdm_add_wkdep(mpuss_clkdm, l4_per_clkdm);
	ret |= clkdm_add_wkdep(mpuss_clkdm, l4wkup);
	ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
	ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
	if (ret) {
		pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 "
				"wakeup dependency\n");
		goto err2;
	}

	ret = omap4_mpuss_init();
	if (ret) {
		pr_err("Failed to initialise OMAP4 MPUSS\n");
		goto err2;
	}

	(void) clkdm_for_each(omap_pm_clkdms_setup, NULL);

#ifdef CONFIG_SUSPEND
	omap_pm_suspend = omap4_pm_suspend;
#endif

	/* Overwrite the default cpu_do_idle() */
	arm_pm_idle = omap_default_idle;

	omap4_idle_init();

err2:
	return ret;
}
Commit	Line	Data
5643aebb RN	1	/*
	2	* OMAP4 Power Management Routines
	3	*
e44f9a77	4	* Copyright (C) 2010-2011 Texas Instruments, Inc.
5643aebb	5	* Rajendra Nayak <rnayak@ti.com>
e44f9a77	6	* Santosh Shilimkar <santosh.shilimkar@ti.com>
5643aebb RN	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/pm.h>
	14	#include <linux/suspend.h>
	15	#include <linux/module.h>
	16	#include <linux/list.h>
	17	#include <linux/err.h>
	18	#include <linux/slab.h>
9f97da78	19	#include <asm/system_misc.h>
5643aebb	20
4e65331c	21	#include "common.h"
3c50729b	22	#include "clockdomain.h"
72e06d08	23	#include "powerdomain.h"
e44f9a77	24	#include "pm.h"
5643aebb RN	25
	26	struct power_state {
	27	struct powerdomain *pwrdm;
	28	u32 next_state;
	29	#ifdef CONFIG_SUSPEND
	30	u32 saved_state;
3ba2a739	31	u32 saved_logic_state;
5643aebb RN	32	#endif
	33	struct list_head node;
	34	};
	35
	36	static LIST_HEAD(pwrst_list);
	37
	38	#ifdef CONFIG_SUSPEND
5643aebb RN	39	static int omap4_pm_suspend(void)
5643aebb RN	40	{
e44f9a77 SS	41	struct power_state *pwrst;
	42	int state, ret = 0;
	43	u32 cpu_id = smp_processor_id();
	44
	45	/* Save current powerdomain state */
	46	list_for_each_entry(pwrst, &pwrst_list, node) {
	47	pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
3ba2a739	48	pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm);
e44f9a77 SS	49	}
	50
	51	/* Set targeted power domain states by suspend */
	52	list_for_each_entry(pwrst, &pwrst_list, node) {
	53	omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
3ba2a739	54	pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF);
e44f9a77 SS	55	}
	56
	57	/*
	58	* For MPUSS to hit power domain retention(CSWR or OSWR),
	59	* CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
	60	* since CPU power domain CSWR is not supported by hardware
	61	* Only master CPU follows suspend path. All other CPUs follow
	62	* CPU hotplug path in system wide suspend. On OMAP4, CPU power
	63	* domain CSWR is not supported by hardware.
	64	* More details can be found in OMAP4430 TRM section 4.3.4.2.
	65	*/
	66	omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF);
	67
	68	/* Restore next powerdomain state */
	69	list_for_each_entry(pwrst, &pwrst_list, node) {
	70	state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
	71	if (state > pwrst->next_state) {
	72	pr_info("Powerdomain (%s) didn't enter "
	73	"target state %d\n",
	74	pwrst->pwrdm->name, pwrst->next_state);
	75	ret = -1;
	76	}
	77	omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
3ba2a739	78	pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
e44f9a77 SS	79	}
	80	if (ret)
	81	pr_crit("Could not enter target state in pm_suspend\n");
	82	else
	83	pr_info("Successfully put all powerdomains to target state\n");
	84
5643aebb RN	85	return 0;
5643aebb RN	86	}
5643aebb RN	87	#endif /* CONFIG_SUSPEND */
	88
	89	static int __init pwrdms_setup(struct powerdomain pwrdm, void unused)
	90	{
	91	struct power_state *pwrst;
	92
	93	if (!pwrdm->pwrsts)
	94	return 0;
	95
e44f9a77 SS	96	/*
	97	* Skip CPU0 and CPU1 power domains. CPU1 is programmed
	98	* through hotplug path and CPU0 explicitly programmed
	99	* further down in the code path
	100	*/
	101	if (!strncmp(pwrdm->name, "cpu", 3))
	102	return 0;
	103
	104	/*
	105	* FIXME: Remove this check when core retention is supported
	106	* Only MPUSS power domain is added in the list.
	107	*/
	108	if (strcmp(pwrdm->name, "mpu_pwrdm"))
	109	return 0;
	110
5643aebb RN	111	pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
	112	if (!pwrst)
	113	return -ENOMEM;
e44f9a77	114
5643aebb	115	pwrst->pwrdm = pwrdm;
e44f9a77	116	pwrst->next_state = PWRDM_POWER_RET;
5643aebb RN	117	list_add(&pwrst->node, &pwrst_list);
5643aebb RN	118
e44f9a77	119	return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
5643aebb RN	120	}
5643aebb RN	121
72826b9f SS	122	/**
	123	* omap_default_idle - OMAP4 default ilde routine.'
	124	*
	125	* Implements OMAP4 memory, IO ordering requirements which can't be addressed
ae940913	126	* with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPUIDLE and
72826b9f SS	127	* by secondary CPU with CONFIG_CPUIDLE.
	128	*/
	129	static void omap_default_idle(void)
	130	{
72826b9f SS	131	local_fiq_disable();
	132
	133	omap_do_wfi();
	134
	135	local_fiq_enable();
72826b9f SS	136	}
72826b9f SS	137
5643aebb RN	138	/**
	139	* omap4_pm_init - Init routine for OMAP4 PM
	140	*
	141	* Initializes all powerdomain and clockdomain target states
	142	* and all PRCM settings.
	143	*/
bbd707ac	144	int __init omap4_pm_init(void)
5643aebb RN	145	{
5643aebb RN	146	int ret;
68523f42	147	struct clockdomain emif_clkdm, mpuss_clkdm, l3_1_clkdm, l4wkup;
12f27826	148	struct clockdomain ducati_clkdm, l3_2_clkdm, *l4_per_clkdm;
5643aebb	149
361b02f3 SS	150	if (omap_rev() == OMAP4430_REV_ES1_0) {
	151	WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
	152	return -ENODEV;
	153	}
	154
5643aebb RN	155	pr_err("Power Management for TI OMAP4.\n");
5643aebb RN	156
5643aebb RN	157	ret = pwrdm_for_each(pwrdms_setup, NULL);
	158	if (ret) {
	159	pr_err("Failed to setup powerdomains\n");
	160	goto err2;
	161	}
5643aebb	162
12f27826 SS	163	/*
	164	* The dynamic dependency between MPUSS -> MEMIF and
	165	* MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
	166	* expected. The hardware recommendation is to enable static
	167	* dependencies for these to avoid system lock ups or random crashes.
68523f42 SS	168	* The L4 wakeup depedency is added to workaround the OCP sync hardware
	169	* BUG with 32K synctimer which lead to incorrect timer value read
	170	* from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
	171	* are part of L4 wakeup clockdomain.
12f27826 SS	172	*/
	173	mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
	174	emif_clkdm = clkdm_lookup("l3_emif_clkdm");
	175	l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
	176	l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
	177	l4_per_clkdm = clkdm_lookup("l4_per_clkdm");
68523f42	178	l4wkup = clkdm_lookup("l4_wkup_clkdm");
12f27826	179	ducati_clkdm = clkdm_lookup("ducati_clkdm");
68523f42	180	if ((!mpuss_clkdm) \|\| (!emif_clkdm) \|\| (!l3_1_clkdm) \|\| (!l4wkup) \|\|
12f27826 SS	181	(!l3_2_clkdm) \|\| (!ducati_clkdm) \|\| (!l4_per_clkdm))
	182	goto err2;
	183
	184	ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
	185	ret \|= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
	186	ret \|= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
	187	ret \|= clkdm_add_wkdep(mpuss_clkdm, l4_per_clkdm);
68523f42	188	ret \|= clkdm_add_wkdep(mpuss_clkdm, l4wkup);
12f27826 SS	189	ret \|= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
	190	ret \|= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
	191	if (ret) {
	192	pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 "
	193	"wakeup dependency\n");
	194	goto err2;
	195	}
	196
b2b9762f SS	197	ret = omap4_mpuss_init();
	198	if (ret) {
	199	pr_err("Failed to initialise OMAP4 MPUSS\n");
	200	goto err2;
	201	}
	202
92206fd2	203	(void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
3c50729b	204
5643aebb	205	#ifdef CONFIG_SUSPEND
1416408d PW	206	omap_pm_suspend = omap4_pm_suspend;
1416408d PW	207	#endif
5643aebb	208
ae940913	209	/* Overwrite the default cpu_do_idle() */
0bcd24b0	210	arm_pm_idle = omap_default_idle;
72826b9f	211
98272660 SS	212	omap4_idle_init();
98272660 SS	213
5643aebb RN	214	err2:
	215	return ret;
	216	}