[deliverable/linux.git] / arch / arm / mach-omap2 / pm44xx.c

/*
 * OMAP4+ Power Management Routines
 *
 * Copyright (C) 2010-2013 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
 * Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/pm.h>
#include <linux/suspend.h>
#include <linux/module.h>
#include <linux/list.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <asm/system_misc.h>

#include "soc.h"
#include "common.h"
#include "clockdomain.h"
#include "powerdomain.h"
#include "pm.h"

u16 pm44xx_errata;

struct power_state {
	struct powerdomain *pwrdm;
	u32 next_state;
#ifdef CONFIG_SUSPEND
	u32 saved_state;
	u32 saved_logic_state;
#endif
	struct list_head node;
};

static LIST_HEAD(pwrst_list);

#ifdef CONFIG_SUSPEND
static int omap4_pm_suspend(void)
{
	struct power_state *pwrst;
	int state, ret = 0;
	u32 cpu_id = smp_processor_id();

	/* Save current powerdomain state */
	list_for_each_entry(pwrst, &pwrst_list, node) {
		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
		pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm);
	}

	/* Set targeted power domain states by suspend */
	list_for_each_entry(pwrst, &pwrst_list, node) {
		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
		pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF);
	}

	/*
	 * For MPUSS to hit power domain retention(CSWR or OSWR),
	 * CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
	 * since CPU power domain CSWR is not supported by hardware
	 * Only master CPU follows suspend path. All other CPUs follow
	 * CPU hotplug path in system wide suspend. On OMAP4, CPU power
	 * domain CSWR is not supported by hardware.
	 * More details can be found in OMAP4430 TRM section 4.3.4.2.
	 */
	omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF);

	/* Restore next powerdomain state */
	list_for_each_entry(pwrst, &pwrst_list, node) {
		state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
		if (state > pwrst->next_state) {
			pr_info("Powerdomain (%s) didn't enter target state %d\n",
				pwrst->pwrdm->name, pwrst->next_state);
			ret = -1;
		}
		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
		pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
	}
	if (ret) {
		pr_crit("Could not enter target state in pm_suspend\n");
		/*
		 * OMAP4 chip PM currently works only with certain (newer)
		 * versions of bootloaders. This is due to missing code in the
		 * kernel to properly reset and initialize some devices.
		 * Warn the user about the bootloader version being one of the
		 * possible causes.
		 * http://www.spinics.net/lists/arm-kernel/msg218641.html
		 */
		pr_warn("A possible cause could be an old bootloader - try u-boot >= v2012.07\n");
	} else {
		pr_info("Successfully put all powerdomains to target state\n");
	}

	return 0;
}
#endif /* CONFIG_SUSPEND */

static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
{
	struct power_state *pwrst;

	if (!pwrdm->pwrsts)
		return 0;

	/*
	 * Skip CPU0 and CPU1 power domains. CPU1 is programmed
	 * through hotplug path and CPU0 explicitly programmed
	 * further down in the code path
	 */
	if (!strncmp(pwrdm->name, "cpu", 3))
		return 0;

	pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
	if (!pwrst)
		return -ENOMEM;

	pwrst->pwrdm = pwrdm;
	pwrst->next_state = PWRDM_POWER_RET;
	list_add(&pwrst->node, &pwrst_list);

	return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
}

/**
 * omap_default_idle - OMAP4 default ilde routine.'
 *
 * Implements OMAP4 memory, IO ordering requirements which can't be addressed
 * with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPU_IDLE and
 * by secondary CPU with CONFIG_CPU_IDLE.
 */
static void omap_default_idle(void)
{
	omap_do_wfi();
}

/**
 * omap4_init_static_deps - Add OMAP4 static dependencies
 *
 * Add needed static clockdomain dependencies on OMAP4 devices.
 * Return: 0 on success or 'err' on failures
 */
static inline int omap4_init_static_deps(void)
{
	struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
	struct clockdomain *ducati_clkdm, *l3_2_clkdm;
	int ret = 0;

	if (omap_rev() == OMAP4430_REV_ES1_0) {
		WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
		return -ENODEV;
	}

	pr_err("Power Management for TI OMAP4.\n");
	/*
	 * OMAP4 chip PM currently works only with certain (newer)
	 * versions of bootloaders. This is due to missing code in the
	 * kernel to properly reset and initialize some devices.
	 * http://www.spinics.net/lists/arm-kernel/msg218641.html
	 */
	pr_warn("OMAP4 PM: u-boot >= v2012.07 is required for full PM support\n");

	ret = pwrdm_for_each(pwrdms_setup, NULL);
	if (ret) {
		pr_err("Failed to setup powerdomains\n");
		return ret;
	}

	/*
	 * The dynamic dependency between MPUSS -> MEMIF and
	 * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
	 * expected. The hardware recommendation is to enable static
	 * dependencies for these to avoid system lock ups or random crashes.
	 * The L4 wakeup depedency is added to workaround the OCP sync hardware
	 * BUG with 32K synctimer which lead to incorrect timer value read
	 * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
	 * are part of L4 wakeup clockdomain.
	 */
	mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
	emif_clkdm = clkdm_lookup("l3_emif_clkdm");
	l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
	l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
	ducati_clkdm = clkdm_lookup("ducati_clkdm");
	if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
		(!l3_2_clkdm) || (!ducati_clkdm))
		return -EINVAL;

	ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
	ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
	ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
	ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
	ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
	if (ret) {
		pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n");
		return -EINVAL;
	}

	return ret;
}

/**
 * omap4_pm_init_early - Does early initialization necessary for OMAP4+ devices
 *
 * Initializes basic stuff for power management functionality.
 */
int __init omap4_pm_init_early(void)
{
	if (cpu_is_omap446x())
		pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;

	return 0;
}

/**
 * omap4_pm_init - Init routine for OMAP4+ devices
 *
 * Initializes all powerdomain and clockdomain target states
 * and all PRCM settings.
 * Return: Returns the error code returned by called functions.
 */
int __init omap4_pm_init(void)
{
	int ret = 0;

	if (omap_rev() == OMAP4430_REV_ES1_0) {
		WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
		return -ENODEV;
	}

	pr_info("Power Management for TI OMAP4+ devices.\n");

	ret = pwrdm_for_each(pwrdms_setup, NULL);
	if (ret) {
		pr_err("Failed to setup powerdomains.\n");
		goto err2;
	}

	if (cpu_is_omap44xx()) {
		ret = omap4_init_static_deps();
		if (ret)
			goto err2;
	}

	ret = omap4_mpuss_init();
	if (ret) {
		pr_err("Failed to initialise OMAP4 MPUSS\n");
		goto err2;
	}

	(void) clkdm_for_each(omap_pm_clkdms_setup, NULL);

#ifdef CONFIG_SUSPEND
	omap_pm_suspend = omap4_pm_suspend;
#endif

	/* Overwrite the default cpu_do_idle() */
	arm_pm_idle = omap_default_idle;

	if (cpu_is_omap44xx())
		omap4_idle_init();

err2:
	return ret;
}
Commit	Line	Data
5643aebb	1	/*
705814b5	2	* OMAP4+ Power Management Routines
5643aebb	3	*
705814b5	4	* Copyright (C) 2010-2013 Texas Instruments, Inc.
5643aebb	5	* Rajendra Nayak <rnayak@ti.com>
e44f9a77	6	* Santosh Shilimkar <santosh.shilimkar@ti.com>
5643aebb RN	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/pm.h>
	14	#include <linux/suspend.h>
	15	#include <linux/module.h>
	16	#include <linux/list.h>
	17	#include <linux/err.h>
	18	#include <linux/slab.h>
9f97da78	19	#include <asm/system_misc.h>
5643aebb	20
e4c060db	21	#include "soc.h"
4e65331c	22	#include "common.h"
3c50729b	23	#include "clockdomain.h"
72e06d08	24	#include "powerdomain.h"
e44f9a77	25	#include "pm.h"
5643aebb	26
de70af49 NM	27	u16 pm44xx_errata;
de70af49 NM	28
5643aebb RN	29	struct power_state {
	30	struct powerdomain *pwrdm;
	31	u32 next_state;
	32	#ifdef CONFIG_SUSPEND
	33	u32 saved_state;
3ba2a739	34	u32 saved_logic_state;
5643aebb RN	35	#endif
	36	struct list_head node;
	37	};
	38
	39	static LIST_HEAD(pwrst_list);
	40
	41	#ifdef CONFIG_SUSPEND
5643aebb RN	42	static int omap4_pm_suspend(void)
5643aebb RN	43	{
e44f9a77 SS	44	struct power_state *pwrst;
	45	int state, ret = 0;
	46	u32 cpu_id = smp_processor_id();
	47
	48	/* Save current powerdomain state */
	49	list_for_each_entry(pwrst, &pwrst_list, node) {
	50	pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
3ba2a739	51	pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm);
e44f9a77 SS	52	}
	53
	54	/* Set targeted power domain states by suspend */
	55	list_for_each_entry(pwrst, &pwrst_list, node) {
	56	omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
3ba2a739	57	pwrdm_set_logic_retst(pwrst->pwrdm, PWRDM_POWER_OFF);
e44f9a77 SS	58	}
	59
	60	/*
	61	* For MPUSS to hit power domain retention(CSWR or OSWR),
	62	* CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
	63	* since CPU power domain CSWR is not supported by hardware
	64	* Only master CPU follows suspend path. All other CPUs follow
	65	* CPU hotplug path in system wide suspend. On OMAP4, CPU power
	66	* domain CSWR is not supported by hardware.
	67	* More details can be found in OMAP4430 TRM section 4.3.4.2.
	68	*/
	69	omap4_enter_lowpower(cpu_id, PWRDM_POWER_OFF);
	70
	71	/* Restore next powerdomain state */
	72	list_for_each_entry(pwrst, &pwrst_list, node) {
	73	state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
	74	if (state > pwrst->next_state) {
7852ec05 PW	75	pr_info("Powerdomain (%s) didn't enter target state %d\n",
7852ec05 PW	76	pwrst->pwrdm->name, pwrst->next_state);
e44f9a77 SS	77	ret = -1;
	78	}
	79	omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
3ba2a739	80	pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
e44f9a77	81	}
60480098	82	if (ret) {
e44f9a77	83	pr_crit("Could not enter target state in pm_suspend\n");
60480098 RN	84	/*
	85	* OMAP4 chip PM currently works only with certain (newer)
	86	* versions of bootloaders. This is due to missing code in the
	87	* kernel to properly reset and initialize some devices.
	88	* Warn the user about the bootloader version being one of the
	89	* possible causes.
	90	* http://www.spinics.net/lists/arm-kernel/msg218641.html
	91	*/
	92	pr_warn("A possible cause could be an old bootloader - try u-boot >= v2012.07\n");
	93	} else {
e44f9a77	94	pr_info("Successfully put all powerdomains to target state\n");
60480098	95	}
e44f9a77	96
5643aebb RN	97	return 0;
5643aebb RN	98	}
5643aebb RN	99	#endif /* CONFIG_SUSPEND */
	100
	101	static int __init pwrdms_setup(struct powerdomain pwrdm, void unused)
	102	{
	103	struct power_state *pwrst;
	104
	105	if (!pwrdm->pwrsts)
	106	return 0;
	107
e44f9a77 SS	108	/*
	109	* Skip CPU0 and CPU1 power domains. CPU1 is programmed
	110	* through hotplug path and CPU0 explicitly programmed
	111	* further down in the code path
	112	*/
	113	if (!strncmp(pwrdm->name, "cpu", 3))
	114	return 0;
	115
5643aebb RN	116	pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
	117	if (!pwrst)
	118	return -ENOMEM;
e44f9a77	119
5643aebb	120	pwrst->pwrdm = pwrdm;
e44f9a77	121	pwrst->next_state = PWRDM_POWER_RET;
5643aebb RN	122	list_add(&pwrst->node, &pwrst_list);
5643aebb RN	123
e44f9a77	124	return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
5643aebb RN	125	}
5643aebb RN	126
72826b9f SS	127	/**
	128	* omap_default_idle - OMAP4 default ilde routine.'
	129	*
	130	* Implements OMAP4 memory, IO ordering requirements which can't be addressed
62006324 PB	131	* with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPU_IDLE and
62006324 PB	132	* by secondary CPU with CONFIG_CPU_IDLE.
72826b9f SS	133	*/
	134	static void omap_default_idle(void)
	135	{
72826b9f	136	omap_do_wfi();
72826b9f SS	137	}
72826b9f SS	138
5643aebb	139	/**
705814b5	140	* omap4_init_static_deps - Add OMAP4 static dependencies
5643aebb	141	*
705814b5 SS	142	* Add needed static clockdomain dependencies on OMAP4 devices.
705814b5 SS	143	* Return: 0 on success or 'err' on failures
5643aebb	144	*/
705814b5	145	static inline int omap4_init_static_deps(void)
5643aebb	146	{
6cf38956	147	struct clockdomain emif_clkdm, mpuss_clkdm, *l3_1_clkdm;
d5336a5a	148	struct clockdomain ducati_clkdm, l3_2_clkdm;
705814b5	149	int ret = 0;
5643aebb	150
361b02f3 SS	151	if (omap_rev() == OMAP4430_REV_ES1_0) {
	152	WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
	153	return -ENODEV;
	154	}
	155
5643aebb	156	pr_err("Power Management for TI OMAP4.\n");
60480098 RN	157	/*
	158	* OMAP4 chip PM currently works only with certain (newer)
	159	* versions of bootloaders. This is due to missing code in the
	160	* kernel to properly reset and initialize some devices.
	161	* http://www.spinics.net/lists/arm-kernel/msg218641.html
	162	*/
	163	pr_warn("OMAP4 PM: u-boot >= v2012.07 is required for full PM support\n");
5643aebb	164
5643aebb RN	165	ret = pwrdm_for_each(pwrdms_setup, NULL);
	166	if (ret) {
	167	pr_err("Failed to setup powerdomains\n");
705814b5	168	return ret;
5643aebb	169	}
5643aebb	170
12f27826 SS	171	/*
	172	* The dynamic dependency between MPUSS -> MEMIF and
	173	* MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
	174	* expected. The hardware recommendation is to enable static
	175	* dependencies for these to avoid system lock ups or random crashes.
705814b5 SS	176	* The L4 wakeup depedency is added to workaround the OCP sync hardware
	177	* BUG with 32K synctimer which lead to incorrect timer value read
	178	* from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
	179	* are part of L4 wakeup clockdomain.
12f27826 SS	180	*/
	181	mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
	182	emif_clkdm = clkdm_lookup("l3_emif_clkdm");
	183	l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
	184	l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
12f27826	185	ducati_clkdm = clkdm_lookup("ducati_clkdm");
6cf38956	186	if ((!mpuss_clkdm) \|\| (!emif_clkdm) \|\| (!l3_1_clkdm) \|\|
d5336a5a	187	(!l3_2_clkdm) \|\| (!ducati_clkdm))
705814b5	188	return -EINVAL;
12f27826 SS	189
	190	ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
	191	ret \|= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
	192	ret \|= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
12f27826 SS	193	ret \|= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
	194	ret \|= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
	195	if (ret) {
7852ec05	196	pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n");
705814b5 SS	197	return -EINVAL;
	198	}
	199
	200	return ret;
de70af49 NM	201	}
	202
	203	/**
	204	* omap4_pm_init_early - Does early initialization necessary for OMAP4+ devices
	205	*
	206	* Initializes basic stuff for power management functionality.
	207	*/
	208	int __init omap4_pm_init_early(void)
	209	{
	210	if (cpu_is_omap446x())
	211	pm44xx_errata \|= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
	212
	213	return 0;
705814b5 SS	214	}
	215
	216	/**
	217	* omap4_pm_init - Init routine for OMAP4+ devices
	218	*
	219	* Initializes all powerdomain and clockdomain target states
	220	* and all PRCM settings.
	221	* Return: Returns the error code returned by called functions.
	222	*/
	223	int __init omap4_pm_init(void)
	224	{
	225	int ret = 0;
	226
	227	if (omap_rev() == OMAP4430_REV_ES1_0) {
	228	WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
	229	return -ENODEV;
	230	}
	231
	232	pr_info("Power Management for TI OMAP4+ devices.\n");
	233
	234	ret = pwrdm_for_each(pwrdms_setup, NULL);
	235	if (ret) {
	236	pr_err("Failed to setup powerdomains.\n");
12f27826 SS	237	goto err2;
	238	}
	239
705814b5 SS	240	if (cpu_is_omap44xx()) {
	241	ret = omap4_init_static_deps();
	242	if (ret)
	243	goto err2;
	244	}
	245
b2b9762f SS	246	ret = omap4_mpuss_init();
	247	if (ret) {
	248	pr_err("Failed to initialise OMAP4 MPUSS\n");
	249	goto err2;
	250	}
	251
92206fd2	252	(void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
3c50729b	253
5643aebb	254	#ifdef CONFIG_SUSPEND
1416408d PW	255	omap_pm_suspend = omap4_pm_suspend;
1416408d PW	256	#endif
5643aebb	257
ae940913	258	/* Overwrite the default cpu_do_idle() */
0bcd24b0	259	arm_pm_idle = omap_default_idle;
72826b9f	260
705814b5 SS	261	if (cpu_is_omap44xx())
705814b5 SS	262	omap4_idle_init();
98272660	263
5643aebb RN	264	err2:
	265	return ret;
	266	}