[deliverable/linux.git] / arch / arm / mach-omap2 / pm44xx.c

/*
 * OMAP4+ Power Management Routines
 *
 * Copyright (C) 2010-2013 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
 * Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/pm.h>
#include <linux/suspend.h>
#include <linux/module.h>
#include <linux/list.h>
#include <linux/err.h>
#include <linux/slab.h>
#include <asm/system_misc.h>

#include "soc.h"
#include "common.h"
#include "clockdomain.h"
#include "powerdomain.h"
#include "pm.h"

u16 pm44xx_errata;

struct power_state {
	struct powerdomain *pwrdm;
	u32 next_state;
	u32 next_logic_state;
#ifdef CONFIG_SUSPEND
	u32 saved_state;
	u32 saved_logic_state;
#endif
	struct list_head node;
};

static u32 cpu_suspend_state = PWRDM_POWER_OFF;

static LIST_HEAD(pwrst_list);

#ifdef CONFIG_SUSPEND
static int omap4_pm_suspend(void)
{
	struct power_state *pwrst;
	int state, ret = 0;
	u32 cpu_id = smp_processor_id();

	/* Save current powerdomain state */
	list_for_each_entry(pwrst, &pwrst_list, node) {
		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
		pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm);
	}

	/* Set targeted power domain states by suspend */
	list_for_each_entry(pwrst, &pwrst_list, node) {
		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
		pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->next_logic_state);
	}

	/*
	 * For MPUSS to hit power domain retention(CSWR or OSWR),
	 * CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
	 * since CPU power domain CSWR is not supported by hardware
	 * Only master CPU follows suspend path. All other CPUs follow
	 * CPU hotplug path in system wide suspend. On OMAP4, CPU power
	 * domain CSWR is not supported by hardware.
	 * More details can be found in OMAP4430 TRM section 4.3.4.2.
	 */
	omap4_enter_lowpower(cpu_id, cpu_suspend_state);

	/* Restore next powerdomain state */
	list_for_each_entry(pwrst, &pwrst_list, node) {
		state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
		if (state > pwrst->next_state) {
			pr_info("Powerdomain (%s) didn't enter target state %d\n",
				pwrst->pwrdm->name, pwrst->next_state);
			ret = -1;
		}
		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
		pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
	}
	if (ret) {
		pr_crit("Could not enter target state in pm_suspend\n");
		/*
		 * OMAP4 chip PM currently works only with certain (newer)
		 * versions of bootloaders. This is due to missing code in the
		 * kernel to properly reset and initialize some devices.
		 * Warn the user about the bootloader version being one of the
		 * possible causes.
		 * http://www.spinics.net/lists/arm-kernel/msg218641.html
		 */
		pr_warn("A possible cause could be an old bootloader - try u-boot >= v2012.07\n");
	} else {
		pr_info("Successfully put all powerdomains to target state\n");
	}

	return 0;
}
#else
#define omap4_pm_suspend NULL
#endif /* CONFIG_SUSPEND */

static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
{
	struct power_state *pwrst;

	if (!pwrdm->pwrsts)
		return 0;

	/*
	 * Skip CPU0 and CPU1 power domains. CPU1 is programmed
	 * through hotplug path and CPU0 explicitly programmed
	 * further down in the code path
	 */
	if (!strncmp(pwrdm->name, "cpu", 3)) {
		if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
			cpu_suspend_state = PWRDM_POWER_RET;
		return 0;
	}

	pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
	if (!pwrst)
		return -ENOMEM;

	pwrst->pwrdm = pwrdm;
	pwrst->next_state = pwrdm_get_valid_lp_state(pwrdm, false,
						     PWRDM_POWER_RET);
	pwrst->next_logic_state = pwrdm_get_valid_lp_state(pwrdm, true,
							   PWRDM_POWER_OFF);

	list_add(&pwrst->node, &pwrst_list);

	return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
}

/**
 * omap_default_idle - OMAP4 default ilde routine.'
 *
 * Implements OMAP4 memory, IO ordering requirements which can't be addressed
 * with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPU_IDLE and
 * by secondary CPU with CONFIG_CPU_IDLE.
 */
static void omap_default_idle(void)
{
	omap_do_wfi();
}

/**
 * omap4_init_static_deps - Add OMAP4 static dependencies
 *
 * Add needed static clockdomain dependencies on OMAP4 devices.
 * Return: 0 on success or 'err' on failures
 */
static inline int omap4_init_static_deps(void)
{
	struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
	struct clockdomain *ducati_clkdm, *l3_2_clkdm;
	int ret = 0;

	/*
	 * The dynamic dependency between MPUSS -> MEMIF and
	 * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
	 * expected. The hardware recommendation is to enable static
	 * dependencies for these to avoid system lock ups or random crashes.
	 * The L4 wakeup depedency is added to workaround the OCP sync hardware
	 * BUG with 32K synctimer which lead to incorrect timer value read
	 * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
	 * are part of L4 wakeup clockdomain.
	 */
	mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
	emif_clkdm = clkdm_lookup("l3_emif_clkdm");
	l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
	l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
	ducati_clkdm = clkdm_lookup("ducati_clkdm");
	if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
		(!l3_2_clkdm) || (!ducati_clkdm))
		return -EINVAL;

	ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
	ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
	ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
	ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
	ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
	if (ret) {
		pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n");
		return -EINVAL;
	}

	return ret;
}

/**
 * omap5_dra7_init_static_deps - Init static clkdm dependencies on OMAP5 and
 *				 DRA7
 *
 * The dynamic dependency between MPUSS -> EMIF is broken and has
 * not worked as expected. The hardware recommendation is to
 * enable static dependencies for these to avoid system
 * lock ups or random crashes.
 */
static inline int omap5_dra7_init_static_deps(void)
{
	struct clockdomain *mpuss_clkdm, *emif_clkdm;
	int ret;

	mpuss_clkdm = clkdm_lookup("mpu_clkdm");
	emif_clkdm = clkdm_lookup("emif_clkdm");
	if (!mpuss_clkdm || !emif_clkdm)
		return -EINVAL;

	ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
	if (ret)
		pr_err("Failed to add MPUSS -> EMIF wakeup dependency\n");

	return ret;
}

/**
 * omap4_pm_init_early - Does early initialization necessary for OMAP4+ devices
 *
 * Initializes basic stuff for power management functionality.
 */
int __init omap4_pm_init_early(void)
{
	if (cpu_is_omap446x())
		pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;

	if (soc_is_omap54xx() || soc_is_dra7xx())
		pm44xx_errata |= PM_OMAP4_CPU_OSWR_DISABLE;

	return 0;
}

/**
 * omap4_pm_init - Init routine for OMAP4+ devices
 *
 * Initializes all powerdomain and clockdomain target states
 * and all PRCM settings.
 * Return: Returns the error code returned by called functions.
 */
int __init omap4_pm_init(void)
{
	int ret = 0;

	if (omap_rev() == OMAP4430_REV_ES1_0) {
		WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
		return -ENODEV;
	}

	pr_info("Power Management for TI OMAP4+ devices.\n");

	/*
	 * OMAP4 chip PM currently works only with certain (newer)
	 * versions of bootloaders. This is due to missing code in the
	 * kernel to properly reset and initialize some devices.
	 * http://www.spinics.net/lists/arm-kernel/msg218641.html
	 */
	if (cpu_is_omap44xx())
		pr_warn("OMAP4 PM: u-boot >= v2012.07 is required for full PM support\n");

	ret = pwrdm_for_each(pwrdms_setup, NULL);
	if (ret) {
		pr_err("Failed to setup powerdomains.\n");
		goto err2;
	}

	if (cpu_is_omap44xx())
		ret = omap4_init_static_deps();
	else if (soc_is_omap54xx() || soc_is_dra7xx())
		ret = omap5_dra7_init_static_deps();

	if (ret) {
		pr_err("Failed to initialise static dependencies.\n");
		goto err2;
	}

	ret = omap4_mpuss_init();
	if (ret) {
		pr_err("Failed to initialise OMAP4 MPUSS\n");
		goto err2;
	}

	(void) clkdm_for_each(omap_pm_clkdms_setup, NULL);

	omap_common_suspend_init(omap4_pm_suspend);

	/* Overwrite the default cpu_do_idle() */
	arm_pm_idle = omap_default_idle;

	if (cpu_is_omap44xx())
		omap4_idle_init();

err2:
	return ret;
}
Commit	Line	Data
5643aebb	1	/*
705814b5	2	* OMAP4+ Power Management Routines
5643aebb	3	*
705814b5	4	* Copyright (C) 2010-2013 Texas Instruments, Inc.
5643aebb	5	* Rajendra Nayak <rnayak@ti.com>
e44f9a77	6	* Santosh Shilimkar <santosh.shilimkar@ti.com>
5643aebb RN	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/pm.h>
	14	#include <linux/suspend.h>
	15	#include <linux/module.h>
	16	#include <linux/list.h>
	17	#include <linux/err.h>
	18	#include <linux/slab.h>
9f97da78	19	#include <asm/system_misc.h>
5643aebb	20
e4c060db	21	#include "soc.h"
4e65331c	22	#include "common.h"
3c50729b	23	#include "clockdomain.h"
72e06d08	24	#include "powerdomain.h"
e44f9a77	25	#include "pm.h"
5643aebb	26
de70af49 NM	27	u16 pm44xx_errata;
de70af49 NM	28
5643aebb RN	29	struct power_state {
	30	struct powerdomain *pwrdm;
	31	u32 next_state;
46ba5526	32	u32 next_logic_state;
5643aebb RN	33	#ifdef CONFIG_SUSPEND
5643aebb RN	34	u32 saved_state;
3ba2a739	35	u32 saved_logic_state;
5643aebb RN	36	#endif
	37	struct list_head node;
	38	};
	39
6099dd37 RN	40	static u32 cpu_suspend_state = PWRDM_POWER_OFF;
6099dd37 RN	41
5643aebb RN	42	static LIST_HEAD(pwrst_list);
	43
	44	#ifdef CONFIG_SUSPEND
5643aebb RN	45	static int omap4_pm_suspend(void)
5643aebb RN	46	{
e44f9a77 SS	47	struct power_state *pwrst;
	48	int state, ret = 0;
	49	u32 cpu_id = smp_processor_id();
	50
	51	/* Save current powerdomain state */
	52	list_for_each_entry(pwrst, &pwrst_list, node) {
	53	pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
3ba2a739	54	pwrst->saved_logic_state = pwrdm_read_logic_retst(pwrst->pwrdm);
e44f9a77 SS	55	}
	56
	57	/* Set targeted power domain states by suspend */
	58	list_for_each_entry(pwrst, &pwrst_list, node) {
	59	omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
46ba5526	60	pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->next_logic_state);
e44f9a77 SS	61	}
	62
	63	/*
	64	* For MPUSS to hit power domain retention(CSWR or OSWR),
	65	* CPU0 and CPU1 power domains need to be in OFF or DORMANT state,
	66	* since CPU power domain CSWR is not supported by hardware
	67	* Only master CPU follows suspend path. All other CPUs follow
	68	* CPU hotplug path in system wide suspend. On OMAP4, CPU power
	69	* domain CSWR is not supported by hardware.
	70	* More details can be found in OMAP4430 TRM section 4.3.4.2.
	71	*/
6099dd37	72	omap4_enter_lowpower(cpu_id, cpu_suspend_state);
e44f9a77 SS	73
	74	/* Restore next powerdomain state */
	75	list_for_each_entry(pwrst, &pwrst_list, node) {
	76	state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
	77	if (state > pwrst->next_state) {
7852ec05 PW	78	pr_info("Powerdomain (%s) didn't enter target state %d\n",
7852ec05 PW	79	pwrst->pwrdm->name, pwrst->next_state);
e44f9a77 SS	80	ret = -1;
	81	}
	82	omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
3ba2a739	83	pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
e44f9a77	84	}
60480098	85	if (ret) {
e44f9a77	86	pr_crit("Could not enter target state in pm_suspend\n");
60480098 RN	87	/*
	88	* OMAP4 chip PM currently works only with certain (newer)
	89	* versions of bootloaders. This is due to missing code in the
	90	* kernel to properly reset and initialize some devices.
	91	* Warn the user about the bootloader version being one of the
	92	* possible causes.
	93	* http://www.spinics.net/lists/arm-kernel/msg218641.html
	94	*/
	95	pr_warn("A possible cause could be an old bootloader - try u-boot >= v2012.07\n");
	96	} else {
e44f9a77	97	pr_info("Successfully put all powerdomains to target state\n");
60480098	98	}
e44f9a77	99
5643aebb RN	100	return 0;
5643aebb RN	101	}
2e4b62dc DG	102	#else
2e4b62dc DG	103	#define omap4_pm_suspend NULL
5643aebb RN	104	#endif /* CONFIG_SUSPEND */
	105
	106	static int __init pwrdms_setup(struct powerdomain pwrdm, void unused)
	107	{
	108	struct power_state *pwrst;
	109
	110	if (!pwrdm->pwrsts)
	111	return 0;
	112
e44f9a77 SS	113	/*
	114	* Skip CPU0 and CPU1 power domains. CPU1 is programmed
	115	* through hotplug path and CPU0 explicitly programmed
	116	* further down in the code path
	117	*/
6099dd37 RN	118	if (!strncmp(pwrdm->name, "cpu", 3)) {
	119	if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
	120	cpu_suspend_state = PWRDM_POWER_RET;
e44f9a77	121	return 0;
6099dd37	122	}
e44f9a77	123
5643aebb RN	124	pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
	125	if (!pwrst)
	126	return -ENOMEM;
e44f9a77	127
5643aebb	128	pwrst->pwrdm = pwrdm;
bd7593c6 NM	129	pwrst->next_state = pwrdm_get_valid_lp_state(pwrdm, false,
	130	PWRDM_POWER_RET);
	131	pwrst->next_logic_state = pwrdm_get_valid_lp_state(pwrdm, true,
	132	PWRDM_POWER_OFF);
46ba5526	133
5643aebb RN	134	list_add(&pwrst->node, &pwrst_list);
5643aebb RN	135
e44f9a77	136	return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
5643aebb RN	137	}
5643aebb RN	138
72826b9f SS	139	/**
	140	* omap_default_idle - OMAP4 default ilde routine.'
	141	*
	142	* Implements OMAP4 memory, IO ordering requirements which can't be addressed
62006324 PB	143	* with default cpu_do_idle() hook. Used by all CPUs with !CONFIG_CPU_IDLE and
62006324 PB	144	* by secondary CPU with CONFIG_CPU_IDLE.
72826b9f SS	145	*/
	146	static void omap_default_idle(void)
	147	{
72826b9f	148	omap_do_wfi();
72826b9f SS	149	}
72826b9f SS	150
5643aebb	151	/**
705814b5	152	* omap4_init_static_deps - Add OMAP4 static dependencies
5643aebb	153	*
705814b5 SS	154	* Add needed static clockdomain dependencies on OMAP4 devices.
705814b5 SS	155	* Return: 0 on success or 'err' on failures
5643aebb	156	*/
705814b5	157	static inline int omap4_init_static_deps(void)
5643aebb	158	{
6cf38956	159	struct clockdomain emif_clkdm, mpuss_clkdm, *l3_1_clkdm;
d5336a5a	160	struct clockdomain ducati_clkdm, l3_2_clkdm;
705814b5	161	int ret = 0;
5643aebb	162
12f27826 SS	163	/*
	164	* The dynamic dependency between MPUSS -> MEMIF and
	165	* MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
	166	* expected. The hardware recommendation is to enable static
	167	* dependencies for these to avoid system lock ups or random crashes.
705814b5 SS	168	* The L4 wakeup depedency is added to workaround the OCP sync hardware
	169	* BUG with 32K synctimer which lead to incorrect timer value read
	170	* from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
	171	* are part of L4 wakeup clockdomain.
12f27826 SS	172	*/
	173	mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
	174	emif_clkdm = clkdm_lookup("l3_emif_clkdm");
	175	l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
	176	l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
12f27826	177	ducati_clkdm = clkdm_lookup("ducati_clkdm");
6cf38956	178	if ((!mpuss_clkdm) \|\| (!emif_clkdm) \|\| (!l3_1_clkdm) \|\|
d5336a5a	179	(!l3_2_clkdm) \|\| (!ducati_clkdm))
705814b5	180	return -EINVAL;
12f27826 SS	181
	182	ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
	183	ret \|= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
	184	ret \|= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
12f27826 SS	185	ret \|= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
	186	ret \|= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
	187	if (ret) {
7852ec05	188	pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n");
705814b5 SS	189	return -EINVAL;
	190	}
	191
	192	return ret;
de70af49 NM	193	}
de70af49 NM	194
d2136bce SS	195	/**
	196	* omap5_dra7_init_static_deps - Init static clkdm dependencies on OMAP5 and
	197	* DRA7
	198	*
	199	* The dynamic dependency between MPUSS -> EMIF is broken and has
	200	* not worked as expected. The hardware recommendation is to
	201	* enable static dependencies for these to avoid system
	202	* lock ups or random crashes.
	203	*/
	204	static inline int omap5_dra7_init_static_deps(void)
	205	{
	206	struct clockdomain mpuss_clkdm, emif_clkdm;
	207	int ret;
	208
	209	mpuss_clkdm = clkdm_lookup("mpu_clkdm");
	210	emif_clkdm = clkdm_lookup("emif_clkdm");
	211	if (!mpuss_clkdm \|\| !emif_clkdm)
	212	return -EINVAL;
	213
	214	ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
	215	if (ret)
	216	pr_err("Failed to add MPUSS -> EMIF wakeup dependency\n");
	217
	218	return ret;
	219	}
	220
de70af49 NM	221	/**
	222	* omap4_pm_init_early - Does early initialization necessary for OMAP4+ devices
	223	*
	224	* Initializes basic stuff for power management functionality.
	225	*/
	226	int __init omap4_pm_init_early(void)
	227	{
	228	if (cpu_is_omap446x())
	229	pm44xx_errata \|= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
	230
6099dd37 RN	231	if (soc_is_omap54xx() \|\| soc_is_dra7xx())
	232	pm44xx_errata \|= PM_OMAP4_CPU_OSWR_DISABLE;
	233
de70af49	234	return 0;
705814b5 SS	235	}
	236
	237	/**
	238	* omap4_pm_init - Init routine for OMAP4+ devices
	239	*
	240	* Initializes all powerdomain and clockdomain target states
	241	* and all PRCM settings.
	242	* Return: Returns the error code returned by called functions.
	243	*/
	244	int __init omap4_pm_init(void)
	245	{
	246	int ret = 0;
	247
	248	if (omap_rev() == OMAP4430_REV_ES1_0) {
	249	WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
	250	return -ENODEV;
	251	}
	252
	253	pr_info("Power Management for TI OMAP4+ devices.\n");
	254
9008d83f NM	255	/*
	256	* OMAP4 chip PM currently works only with certain (newer)
	257	* versions of bootloaders. This is due to missing code in the
	258	* kernel to properly reset and initialize some devices.
	259	* http://www.spinics.net/lists/arm-kernel/msg218641.html
	260	*/
	261	if (cpu_is_omap44xx())
	262	pr_warn("OMAP4 PM: u-boot >= v2012.07 is required for full PM support\n");
	263
705814b5 SS	264	ret = pwrdm_for_each(pwrdms_setup, NULL);
	265	if (ret) {
	266	pr_err("Failed to setup powerdomains.\n");
12f27826 SS	267	goto err2;
	268	}
	269
d2136bce	270	if (cpu_is_omap44xx())
705814b5	271	ret = omap4_init_static_deps();
d2136bce SS	272	else if (soc_is_omap54xx() \|\| soc_is_dra7xx())
	273	ret = omap5_dra7_init_static_deps();
	274
	275	if (ret) {
	276	pr_err("Failed to initialise static dependencies.\n");
	277	goto err2;
705814b5 SS	278	}
705814b5 SS	279
b2b9762f SS	280	ret = omap4_mpuss_init();
	281	if (ret) {
	282	pr_err("Failed to initialise OMAP4 MPUSS\n");
	283	goto err2;
	284	}
	285
92206fd2	286	(void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
3c50729b	287
2e4b62dc	288	omap_common_suspend_init(omap4_pm_suspend);
5643aebb	289
ae940913	290	/* Overwrite the default cpu_do_idle() */
0bcd24b0	291	arm_pm_idle = omap_default_idle;
72826b9f	292
705814b5 SS	293	if (cpu_is_omap44xx())
705814b5 SS	294	omap4_idle_init();
98272660	295
5643aebb RN	296	err2:
	297	return ret;
	298	}