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Merge remote-tracking branch 'asoc/topic/wm8994' into asoc-next
[deliverable/linux.git] / arch / arm / mach-omap2 / powerdomain.h
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ad67ef68 1/*
a64bb9cd 2 * OMAP2/3/4 powerdomain control
ad67ef68 3 *
72e06d08 4 * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc.
694606c4 5 * Copyright (C) 2007-2011 Nokia Corporation
ad67ef68 6 *
72e06d08 7 * Paul Walmsley
ad67ef68
PW		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
6e01478a
PW		 12 *
13 * XXX This should be moved to the mach-omap2/ directory at the earliest
14 * opportunity.
ad67ef68
PW		 15 */
16
72e06d08
PW		 17#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
18#define __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
ad67ef68
PW		 19
20#include <linux/types.h>
21#include <linux/list.h>
22
72e06d08 23#include <linux/atomic.h>
ad67ef68 24
8f1bec24
KH		 25#include "voltage.h"
26
ad67ef68
PW		 27/* Powerdomain basic power states */
28#define PWRDM_POWER_OFF 0x0
29#define PWRDM_POWER_RET 0x1
30#define PWRDM_POWER_INACTIVE 0x2
31#define PWRDM_POWER_ON 0x3
32
2354eb5a
PW		 33#define PWRDM_MAX_PWRSTS 4
34
ad67ef68 35/* Powerdomain allowable state bitfields */
d3353e16 36#define PWRSTS_ON (1 << PWRDM_POWER_ON)
694606c4
PW		 37#define PWRSTS_INACTIVE (1 << PWRDM_POWER_INACTIVE)
38#define PWRSTS_RET (1 << PWRDM_POWER_RET)
bb722f33 39#define PWRSTS_OFF (1 << PWRDM_POWER_OFF)
ad67ef68 40
694606c4
PW		 41#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON)
42#define PWRSTS_OFF_RET (PWRSTS_OFF | PWRSTS_RET)
43#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
44#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON)
ad67ef68
PW		 45
46
0b7cbfb5
PW		 47/* Powerdomain flags */
48#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
3863c74b
TG		 49#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits
50 * in MEM bank 1 position. This is
51 * true for OMAP3430
52 */
90dbc7b0
RN		 53#define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /*
54 * support to transition from a
55 * sleep state to a lower sleep
56 * state without waking up the
57 * powerdomain
58 */
0b7cbfb5 59
ad67ef68 60/*
38900c27
AP		 61 * Number of memory banks that are power-controllable. On OMAP4430, the
62 * maximum is 5.
ad67ef68 63 */
38900c27 64#define PWRDM_MAX_MEM_BANKS 5
ad67ef68 65
8420bb13
PW		 66/*
67 * Maximum number of clockdomains that can be associated with a powerdomain.
3f0ea764 68 * PER powerdomain on AM33XX is the worst case
8420bb13 69 */
3f0ea764 70#define PWRDM_MAX_CLKDMS 11
8420bb13 71
ad67ef68
PW		 72/* XXX A completely arbitrary number. What is reasonable here? */
73#define PWRDM_TRANSITION_BAILOUT 100000
74
8420bb13 75struct clockdomain;
ad67ef68
PW		 76struct powerdomain;
77
f0271d65
PW		 78/**
79 * struct powerdomain - OMAP powerdomain
80 * @name: Powerdomain name
8f1bec24 81 * @voltdm: voltagedomain containing this powerdomain
f0271d65 82 * @prcm_offs: the address offset from CM_BASE/PRM_BASE
a64bb9cd 83 * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs
f0271d65
PW		 84 * @pwrsts: Possible powerdomain power states
85 * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
86 * @flags: Powerdomain flags
87 * @banks: Number of software-controllable memory banks in this powerdomain
88 * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
89 * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
90 * @pwrdm_clkdms: Clockdomains in this powerdomain
91 * @node: list_head linking all powerdomains
e69c22b1 92 * @voltdm_node: list_head linking all powerdomains in a voltagedomain
3f0ea764
VH		 93 * @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs
94 * @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs
95 * @logicretstate_mask: (AM33XX only) mask for logic retention bitfield
96 * in @pwrstctrl_offs
97 * @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs
98 * @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs
99 * @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs
100 * @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield
101 * in @pwrstctrl_offs
f0271d65
PW		 102 * @state:
103 * @state_counter:
104 * @timer:
105 * @state_timer:
a64bb9cd
PW		 106 *
107 * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h.
f0271d65 108 */
ad67ef68 109struct powerdomain {
ad67ef68 110 const char *name;
8f1bec24
KH		 111 union {
112 const char *name;
113 struct voltagedomain *ptr;
114 } voltdm;
e0594b44 115 const s16 prcm_offs;
ad67ef68 116 const u8 pwrsts;
ad67ef68 117 const u8 pwrsts_logic_ret;
0b7cbfb5 118 const u8 flags;
ad67ef68 119 const u8 banks;
ad67ef68 120 const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
ad67ef68 121 const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
a64bb9cd 122 const u8 prcm_partition;
8420bb13 123 struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
ad67ef68 124 struct list_head node;
e69c22b1 125 struct list_head voltdm_node;
ba20bb12 126 int state;
2354eb5a 127 unsigned state_counter[PWRDM_MAX_PWRSTS];
cde08f81
TG		 128 unsigned ret_logic_off_counter;
129 unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
331b93f4 130
3f0ea764
VH		 131 const u8 pwrstctrl_offs;
132 const u8 pwrstst_offs;
133 const u32 logicretstate_mask;
134 const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS];
135 const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS];
136 const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS];
137 const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS];
138
331b93f4
PDS		 139#ifdef CONFIG_PM_DEBUG
140 s64 timer;
2354eb5a 141 s64 state_timer[PWRDM_MAX_PWRSTS];
331b93f4 142#endif
ad67ef68
PW		 143};
144
3b1e8b21 145/**
25985edc 146 * struct pwrdm_ops - Arch specific function implementations
3b1e8b21
RN		 147 * @pwrdm_set_next_pwrst: Set the target power state for a pd
148 * @pwrdm_read_next_pwrst: Read the target power state set for a pd
149 * @pwrdm_read_pwrst: Read the current power state of a pd
150 * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd
151 * @pwrdm_set_logic_retst: Set the logic state in RET for a pd
152 * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd
153 * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd
154 * @pwrdm_read_logic_pwrst: Read the current logic state of a pd
155 * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd
156 * @pwrdm_read_logic_retst: Read the logic state in RET for a pd
157 * @pwrdm_read_mem_pwrst: Read the current memory state of a pd
158 * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd
159 * @pwrdm_read_mem_retst: Read the memory state in RET for a pd
160 * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd
161 * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd
162 * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
163 * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
164 * @pwrdm_wait_transition: Wait for a pd state transition to complete
165 */
166struct pwrdm_ops {
167 int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst);
168 int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm);
169 int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm);
170 int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm);
171 int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst);
172 int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
173 int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
174 int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm);
175 int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm);
176 int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm);
177 int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
178 int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
179 int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);
180 int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm);
181 int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm);
182 int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
183 int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
184 int (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
185};
ad67ef68 186
129c65ee
PW		 187int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs);
188int pwrdm_register_pwrdms(struct powerdomain **pwrdm_list);
189int pwrdm_complete_init(void);
ad67ef68 190
ad67ef68
PW		 191struct powerdomain *pwrdm_lookup(const char *name);
192
a23456e9
PDS		 193int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
194 void *user);
ee894b18
AB		 195int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
196 void *user);
ad67ef68 197
8420bb13
PW		 198int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
199int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
200int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
201 int (*fn)(struct powerdomain *pwrdm,
202 struct clockdomain *clkdm));
048a7034 203struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm);
8420bb13 204
ad67ef68
PW		 205int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
206
207int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
208int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
fecb494b 209int pwrdm_read_pwrst(struct powerdomain *pwrdm);
ad67ef68
PW		 210int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
211int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
212
213int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
214int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
215int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
216
217int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
218int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
1e3d0d2b 219int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
ad67ef68
PW		 220int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
221int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
1e3d0d2b 222int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
ad67ef68 223
0b7cbfb5
PW		 224int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
225int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
226bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
227
ad67ef68
PW		 228int pwrdm_wait_transition(struct powerdomain *pwrdm);
229
ba20bb12 230int pwrdm_state_switch(struct powerdomain *pwrdm);
e0555489
KH		 231int pwrdm_pre_transition(struct powerdomain *pwrdm);
232int pwrdm_post_transition(struct powerdomain *pwrdm);
04aeae77 233int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
fc013873 234int pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
694606c4 235bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
ba20bb12 236
8179488a
PW		 237extern void omap242x_powerdomains_init(void);
238extern void omap243x_powerdomains_init(void);
6e01478a 239extern void omap3xxx_powerdomains_init(void);
3f0ea764 240extern void am33xx_powerdomains_init(void);
6e01478a
PW		 241extern void omap44xx_powerdomains_init(void);
242
72e06d08
PW		 243extern struct pwrdm_ops omap2_pwrdm_operations;
244extern struct pwrdm_ops omap3_pwrdm_operations;
3f0ea764 245extern struct pwrdm_ops am33xx_pwrdm_operations;
72e06d08
PW		 246extern struct pwrdm_ops omap4_pwrdm_operations;
247
248/* Common Internal functions used across OMAP rev's */
249extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank);
250extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank);
251extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank);
252
253extern struct powerdomain wkup_omap2_pwrdm;
254extern struct powerdomain gfx_omap2_pwrdm;
255
256
ad67ef68 257#endif
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