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Merge tag 'microblaze-3.17-rc1' of git://git.monstr.eu/linux-2.6-microblaze
[deliverable/linux.git] / arch / arm / mach-omap2 / powerdomain.h
CommitLineData
ad67ef68 1/*
a64bb9cd 2 * OMAP2/3/4 powerdomain control
ad67ef68 3 *
72e06d08 4 * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc.
694606c4 5 * Copyright (C) 2007-2011 Nokia Corporation
ad67ef68 6 *
72e06d08 7 * Paul Walmsley
ad67ef68
PW		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
6e01478a
PW		 12 *
13 * XXX This should be moved to the mach-omap2/ directory at the earliest
14 * opportunity.
ad67ef68
PW		 15 */
16
72e06d08
PW		 17#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
18#define __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
ad67ef68
PW		 19
20#include <linux/types.h>
21#include <linux/list.h>
3a090284 22#include <linux/spinlock.h>
ad67ef68 23
ad67ef68
PW		 24/* Powerdomain basic power states */
25#define PWRDM_POWER_OFF 0x0
26#define PWRDM_POWER_RET 0x1
27#define PWRDM_POWER_INACTIVE 0x2
28#define PWRDM_POWER_ON 0x3
29
2354eb5a
PW		 30#define PWRDM_MAX_PWRSTS 4
31
ad67ef68 32/* Powerdomain allowable state bitfields */
d3353e16 33#define PWRSTS_ON (1 << PWRDM_POWER_ON)
694606c4
PW		 34#define PWRSTS_INACTIVE (1 << PWRDM_POWER_INACTIVE)
35#define PWRSTS_RET (1 << PWRDM_POWER_RET)
bb722f33 36#define PWRSTS_OFF (1 << PWRDM_POWER_OFF)
ad67ef68 37
694606c4
PW		 38#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON)
39#define PWRSTS_OFF_RET (PWRSTS_OFF | PWRSTS_RET)
40#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
41#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON)
ad67ef68
PW		 42
43
562e54d1
PW		 44/*
45 * Powerdomain flags (struct powerdomain.flags)
46 *
47 * PWRDM_HAS_HDWR_SAR - powerdomain has hardware save-and-restore support
48 *
49 * PWRDM_HAS_MPU_QUIRK - MPU pwr domain has MEM bank 0 bits in MEM
50 * bank 1 position. This is true for OMAP3430
51 *
52 * PWRDM_HAS_LOWPOWERSTATECHANGE - can transition from a sleep state
53 * to a lower sleep state without waking up the powerdomain
54 */
55#define PWRDM_HAS_HDWR_SAR BIT(0)
56#define PWRDM_HAS_MPU_QUIRK BIT(1)
57#define PWRDM_HAS_LOWPOWERSTATECHANGE BIT(2)
0b7cbfb5 58
ad67ef68 59/*
38900c27
AP		 60 * Number of memory banks that are power-controllable. On OMAP4430, the
61 * maximum is 5.
ad67ef68 62 */
38900c27 63#define PWRDM_MAX_MEM_BANKS 5
ad67ef68 64
8420bb13
PW		 65/*
66 * Maximum number of clockdomains that can be associated with a powerdomain.
3f0ea764 67 * PER powerdomain on AM33XX is the worst case
8420bb13 68 */
3f0ea764 69#define PWRDM_MAX_CLKDMS 11
8420bb13 70
ad67ef68
PW		 71/* XXX A completely arbitrary number. What is reasonable here? */
72#define PWRDM_TRANSITION_BAILOUT 100000
73
8420bb13 74struct clockdomain;
ad67ef68 75struct powerdomain;
4794208c 76struct voltagedomain;
ad67ef68 77
f0271d65
PW		 78/**
79 * struct powerdomain - OMAP powerdomain
80 * @name: Powerdomain name
8f1bec24 81 * @voltdm: voltagedomain containing this powerdomain
f0271d65 82 * @prcm_offs: the address offset from CM_BASE/PRM_BASE
a64bb9cd 83 * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs
f0271d65
PW		 84 * @pwrsts: Possible powerdomain power states
85 * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
86 * @flags: Powerdomain flags
87 * @banks: Number of software-controllable memory banks in this powerdomain
88 * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
89 * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
90 * @pwrdm_clkdms: Clockdomains in this powerdomain
91 * @node: list_head linking all powerdomains
e69c22b1 92 * @voltdm_node: list_head linking all powerdomains in a voltagedomain
3f0ea764
VH		 93 * @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs
94 * @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs
95 * @logicretstate_mask: (AM33XX only) mask for logic retention bitfield
96 * in @pwrstctrl_offs
97 * @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs
98 * @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs
99 * @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs
100 * @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield
101 * in @pwrstctrl_offs
f0271d65
PW		 102 * @state:
103 * @state_counter:
104 * @timer:
105 * @state_timer:
3a090284
PW		 106 * @_lock: spinlock used to serialize powerdomain and some clockdomain ops
107 * @_lock_flags: stored flags when @_lock is taken
a64bb9cd
PW		 108 *
109 * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h.
f0271d65 110 */
ad67ef68 111struct powerdomain {
ad67ef68 112 const char *name;
8f1bec24
KH		 113 union {
114 const char *name;
115 struct voltagedomain *ptr;
116 } voltdm;
e0594b44 117 const s16 prcm_offs;
ad67ef68 118 const u8 pwrsts;
ad67ef68 119 const u8 pwrsts_logic_ret;
0b7cbfb5 120 const u8 flags;
ad67ef68 121 const u8 banks;
ad67ef68 122 const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
ad67ef68 123 const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
a64bb9cd 124 const u8 prcm_partition;
8420bb13 125 struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
ad67ef68 126 struct list_head node;
e69c22b1 127 struct list_head voltdm_node;
ba20bb12 128 int state;
2354eb5a 129 unsigned state_counter[PWRDM_MAX_PWRSTS];
cde08f81
TG		 130 unsigned ret_logic_off_counter;
131 unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
3a090284
PW		 132 spinlock_t _lock;
133 unsigned long _lock_flags;
3f0ea764
VH		 134 const u8 pwrstctrl_offs;
135 const u8 pwrstst_offs;
136 const u32 logicretstate_mask;
137 const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS];
138 const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS];
139 const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS];
140 const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS];
141
331b93f4
PDS		 142#ifdef CONFIG_PM_DEBUG
143 s64 timer;
2354eb5a 144 s64 state_timer[PWRDM_MAX_PWRSTS];
331b93f4 145#endif
ad67ef68
PW		 146};
147
3b1e8b21 148/**
25985edc 149 * struct pwrdm_ops - Arch specific function implementations
3b1e8b21
RN		 150 * @pwrdm_set_next_pwrst: Set the target power state for a pd
151 * @pwrdm_read_next_pwrst: Read the target power state set for a pd
152 * @pwrdm_read_pwrst: Read the current power state of a pd
153 * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd
154 * @pwrdm_set_logic_retst: Set the logic state in RET for a pd
155 * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd
156 * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd
157 * @pwrdm_read_logic_pwrst: Read the current logic state of a pd
158 * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd
159 * @pwrdm_read_logic_retst: Read the logic state in RET for a pd
160 * @pwrdm_read_mem_pwrst: Read the current memory state of a pd
161 * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd
162 * @pwrdm_read_mem_retst: Read the memory state in RET for a pd
163 * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd
164 * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd
165 * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
166 * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
167 * @pwrdm_wait_transition: Wait for a pd state transition to complete
cd8abed1 168 * @pwrdm_has_voltdm: Check if a voltdm association is needed
c4978fba
PW		 169 *
170 * Regarding @pwrdm_set_lowpwrstchange: On the OMAP2 and 3-family
171 * chips, a powerdomain's power state is not allowed to directly
172 * transition from one low-power state (e.g., CSWR) to another
173 * low-power state (e.g., OFF) without first waking up the
174 * powerdomain. This wastes energy. So OMAP4 chips support the
175 * ability to transition a powerdomain power state directly from one
176 * low-power state to another. The function pointed to by
177 * @pwrdm_set_lowpwrstchange is intended to configure the OMAP4
178 * hardware powerdomain state machine to enable this feature.
3b1e8b21
RN		 179 */
180struct pwrdm_ops {
181 int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst);
182 int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm);
183 int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm);
184 int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm);
185 int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst);
186 int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
187 int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
188 int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm);
189 int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm);
190 int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm);
191 int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
192 int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
193 int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);
194 int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm);
195 int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm);
196 int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
197 int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
198 int (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
cd8abed1 199 int (*pwrdm_has_voltdm)(void);
3b1e8b21 200};
ad67ef68 201
129c65ee
PW		 202int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs);
203int pwrdm_register_pwrdms(struct powerdomain **pwrdm_list);
204int pwrdm_complete_init(void);
ad67ef68 205
ad67ef68
PW		 206struct powerdomain *pwrdm_lookup(const char *name);
207
a23456e9
PDS		 208int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
209 void *user);
ee894b18
AB		 210int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
211 void *user);
ad67ef68 212
8420bb13
PW		 213int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
214int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
215int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
216 int (*fn)(struct powerdomain *pwrdm,
217 struct clockdomain *clkdm));
048a7034 218struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm);
8420bb13 219
ad67ef68
PW		 220int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
221
222int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
223int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
fecb494b 224int pwrdm_read_pwrst(struct powerdomain *pwrdm);
ad67ef68
PW		 225int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
226int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
227
228int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
229int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
230int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
231
232int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
233int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
1e3d0d2b 234int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
ad67ef68
PW		 235int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
236int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
1e3d0d2b 237int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
ad67ef68 238
0b7cbfb5
PW		 239int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
240int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
241bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
242
3a090284 243int pwrdm_state_switch_nolock(struct powerdomain *pwrdm);
ba20bb12 244int pwrdm_state_switch(struct powerdomain *pwrdm);
e0555489
KH		 245int pwrdm_pre_transition(struct powerdomain *pwrdm);
246int pwrdm_post_transition(struct powerdomain *pwrdm);
fc013873 247int pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
694606c4 248bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
ba20bb12 249
c4978fba
PW		 250extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 state);
251
8179488a
PW		 252extern void omap242x_powerdomains_init(void);
253extern void omap243x_powerdomains_init(void);
6e01478a 254extern void omap3xxx_powerdomains_init(void);
3f0ea764 255extern void am33xx_powerdomains_init(void);
6e01478a 256extern void omap44xx_powerdomains_init(void);
411f968f 257extern void omap54xx_powerdomains_init(void);
97dd16b1 258extern void dra7xx_powerdomains_init(void);
eadc62fc 259void am43xx_powerdomains_init(void);
6e01478a 260
72e06d08
PW		 261extern struct pwrdm_ops omap2_pwrdm_operations;
262extern struct pwrdm_ops omap3_pwrdm_operations;
3f0ea764 263extern struct pwrdm_ops am33xx_pwrdm_operations;
72e06d08
PW		 264extern struct pwrdm_ops omap4_pwrdm_operations;
265
266/* Common Internal functions used across OMAP rev's */
267extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank);
268extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank);
269extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank);
270
271extern struct powerdomain wkup_omap2_pwrdm;
272extern struct powerdomain gfx_omap2_pwrdm;
273
3a090284
PW		 274extern void pwrdm_lock(struct powerdomain *pwrdm);
275extern void pwrdm_unlock(struct powerdomain *pwrdm);
72e06d08 276
ad67ef68 277#endif
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