Commit | Line | Data |
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ad67ef68 | 1 | /* |
a64bb9cd | 2 | * OMAP2/3/4 powerdomain control |
ad67ef68 | 3 | * |
72e06d08 | 4 | * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc. |
6e01478a | 5 | * Copyright (C) 2007-2010 Nokia Corporation |
ad67ef68 | 6 | * |
72e06d08 | 7 | * Paul Walmsley |
ad67ef68 PW |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
6e01478a PW |
12 | * |
13 | * XXX This should be moved to the mach-omap2/ directory at the earliest | |
14 | * opportunity. | |
ad67ef68 PW |
15 | */ |
16 | ||
72e06d08 PW |
17 | #ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H |
18 | #define __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H | |
ad67ef68 PW |
19 | |
20 | #include <linux/types.h> | |
21 | #include <linux/list.h> | |
22 | ||
72e06d08 | 23 | #include <linux/atomic.h> |
ad67ef68 | 24 | |
ce491cf8 | 25 | #include <plat/cpu.h> |
ad67ef68 | 26 | |
ad67ef68 PW |
27 | /* Powerdomain basic power states */ |
28 | #define PWRDM_POWER_OFF 0x0 | |
29 | #define PWRDM_POWER_RET 0x1 | |
30 | #define PWRDM_POWER_INACTIVE 0x2 | |
31 | #define PWRDM_POWER_ON 0x3 | |
32 | ||
2354eb5a PW |
33 | #define PWRDM_MAX_PWRSTS 4 |
34 | ||
ad67ef68 | 35 | /* Powerdomain allowable state bitfields */ |
d3353e16 | 36 | #define PWRSTS_ON (1 << PWRDM_POWER_ON) |
bb722f33 | 37 | #define PWRSTS_OFF (1 << PWRDM_POWER_OFF) |
ad67ef68 PW |
38 | #define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ |
39 | (1 << PWRDM_POWER_ON)) | |
40 | ||
41 | #define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \ | |
42 | (1 << PWRDM_POWER_RET)) | |
43 | ||
f37c6dfa AP |
44 | #define PWRSTS_RET_ON ((1 << PWRDM_POWER_RET) | \ |
45 | (1 << PWRDM_POWER_ON)) | |
46 | ||
ad67ef68 PW |
47 | #define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON)) |
48 | ||
49 | ||
0b7cbfb5 PW |
50 | /* Powerdomain flags */ |
51 | #define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */ | |
3863c74b TG |
52 | #define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits |
53 | * in MEM bank 1 position. This is | |
54 | * true for OMAP3430 | |
55 | */ | |
90dbc7b0 RN |
56 | #define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /* |
57 | * support to transition from a | |
58 | * sleep state to a lower sleep | |
59 | * state without waking up the | |
60 | * powerdomain | |
61 | */ | |
0b7cbfb5 | 62 | |
ad67ef68 | 63 | /* |
38900c27 AP |
64 | * Number of memory banks that are power-controllable. On OMAP4430, the |
65 | * maximum is 5. | |
ad67ef68 | 66 | */ |
38900c27 | 67 | #define PWRDM_MAX_MEM_BANKS 5 |
ad67ef68 | 68 | |
8420bb13 PW |
69 | /* |
70 | * Maximum number of clockdomains that can be associated with a powerdomain. | |
38900c27 | 71 | * CORE powerdomain on OMAP4 is the worst case |
8420bb13 | 72 | */ |
38900c27 | 73 | #define PWRDM_MAX_CLKDMS 9 |
8420bb13 | 74 | |
ad67ef68 PW |
75 | /* XXX A completely arbitrary number. What is reasonable here? */ |
76 | #define PWRDM_TRANSITION_BAILOUT 100000 | |
77 | ||
8420bb13 | 78 | struct clockdomain; |
ad67ef68 PW |
79 | struct powerdomain; |
80 | ||
f0271d65 PW |
81 | /** |
82 | * struct powerdomain - OMAP powerdomain | |
83 | * @name: Powerdomain name | |
84 | * @omap_chip: represents the OMAP chip types containing this pwrdm | |
85 | * @prcm_offs: the address offset from CM_BASE/PRM_BASE | |
a64bb9cd | 86 | * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs |
f0271d65 PW |
87 | * @pwrsts: Possible powerdomain power states |
88 | * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION | |
89 | * @flags: Powerdomain flags | |
90 | * @banks: Number of software-controllable memory banks in this powerdomain | |
91 | * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION | |
92 | * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON | |
93 | * @pwrdm_clkdms: Clockdomains in this powerdomain | |
94 | * @node: list_head linking all powerdomains | |
95 | * @state: | |
96 | * @state_counter: | |
97 | * @timer: | |
98 | * @state_timer: | |
a64bb9cd PW |
99 | * |
100 | * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h. | |
f0271d65 | 101 | */ |
ad67ef68 | 102 | struct powerdomain { |
ad67ef68 | 103 | const char *name; |
ad67ef68 | 104 | const struct omap_chip_id omap_chip; |
e0594b44 | 105 | const s16 prcm_offs; |
ad67ef68 | 106 | const u8 pwrsts; |
ad67ef68 | 107 | const u8 pwrsts_logic_ret; |
0b7cbfb5 | 108 | const u8 flags; |
ad67ef68 | 109 | const u8 banks; |
ad67ef68 | 110 | const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS]; |
ad67ef68 | 111 | const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS]; |
a64bb9cd | 112 | const u8 prcm_partition; |
8420bb13 | 113 | struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS]; |
ad67ef68 | 114 | struct list_head node; |
ba20bb12 | 115 | int state; |
2354eb5a | 116 | unsigned state_counter[PWRDM_MAX_PWRSTS]; |
cde08f81 TG |
117 | unsigned ret_logic_off_counter; |
118 | unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS]; | |
331b93f4 PDS |
119 | |
120 | #ifdef CONFIG_PM_DEBUG | |
121 | s64 timer; | |
2354eb5a | 122 | s64 state_timer[PWRDM_MAX_PWRSTS]; |
331b93f4 | 123 | #endif |
ad67ef68 PW |
124 | }; |
125 | ||
3b1e8b21 RN |
126 | /** |
127 | * struct pwrdm_ops - Arch specfic function implementations | |
128 | * @pwrdm_set_next_pwrst: Set the target power state for a pd | |
129 | * @pwrdm_read_next_pwrst: Read the target power state set for a pd | |
130 | * @pwrdm_read_pwrst: Read the current power state of a pd | |
131 | * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd | |
132 | * @pwrdm_set_logic_retst: Set the logic state in RET for a pd | |
133 | * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd | |
134 | * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd | |
135 | * @pwrdm_read_logic_pwrst: Read the current logic state of a pd | |
136 | * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd | |
137 | * @pwrdm_read_logic_retst: Read the logic state in RET for a pd | |
138 | * @pwrdm_read_mem_pwrst: Read the current memory state of a pd | |
139 | * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd | |
140 | * @pwrdm_read_mem_retst: Read the memory state in RET for a pd | |
141 | * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd | |
142 | * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd | |
143 | * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd | |
144 | * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep | |
145 | * @pwrdm_wait_transition: Wait for a pd state transition to complete | |
146 | */ | |
147 | struct pwrdm_ops { | |
148 | int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst); | |
149 | int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm); | |
150 | int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm); | |
151 | int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm); | |
152 | int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst); | |
153 | int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst); | |
154 | int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst); | |
155 | int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm); | |
156 | int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm); | |
157 | int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm); | |
158 | int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank); | |
159 | int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank); | |
160 | int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank); | |
161 | int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm); | |
162 | int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm); | |
163 | int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm); | |
164 | int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm); | |
165 | int (*pwrdm_wait_transition)(struct powerdomain *pwrdm); | |
166 | }; | |
ad67ef68 | 167 | |
74bea6b9 | 168 | void pwrdm_fw_init(void); |
3b1e8b21 | 169 | void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs); |
ad67ef68 | 170 | |
ad67ef68 PW |
171 | struct powerdomain *pwrdm_lookup(const char *name); |
172 | ||
a23456e9 PDS |
173 | int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), |
174 | void *user); | |
ee894b18 AB |
175 | int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user), |
176 | void *user); | |
ad67ef68 | 177 | |
8420bb13 PW |
178 | int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); |
179 | int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); | |
180 | int pwrdm_for_each_clkdm(struct powerdomain *pwrdm, | |
181 | int (*fn)(struct powerdomain *pwrdm, | |
182 | struct clockdomain *clkdm)); | |
183 | ||
ad67ef68 PW |
184 | int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); |
185 | ||
186 | int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); | |
187 | int pwrdm_read_next_pwrst(struct powerdomain *pwrdm); | |
fecb494b | 188 | int pwrdm_read_pwrst(struct powerdomain *pwrdm); |
ad67ef68 PW |
189 | int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm); |
190 | int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm); | |
191 | ||
192 | int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst); | |
193 | int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); | |
194 | int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); | |
195 | ||
196 | int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm); | |
197 | int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm); | |
1e3d0d2b | 198 | int pwrdm_read_logic_retst(struct powerdomain *pwrdm); |
ad67ef68 PW |
199 | int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank); |
200 | int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank); | |
1e3d0d2b | 201 | int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank); |
ad67ef68 | 202 | |
0b7cbfb5 PW |
203 | int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm); |
204 | int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm); | |
205 | bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm); | |
206 | ||
ad67ef68 PW |
207 | int pwrdm_wait_transition(struct powerdomain *pwrdm); |
208 | ||
ba20bb12 PDS |
209 | int pwrdm_state_switch(struct powerdomain *pwrdm); |
210 | int pwrdm_clkdm_state_switch(struct clockdomain *clkdm); | |
211 | int pwrdm_pre_transition(void); | |
212 | int pwrdm_post_transition(void); | |
04aeae77 | 213 | int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm); |
7f595674 | 214 | u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm); |
ba20bb12 | 215 | |
6e01478a PW |
216 | extern void omap2xxx_powerdomains_init(void); |
217 | extern void omap3xxx_powerdomains_init(void); | |
218 | extern void omap44xx_powerdomains_init(void); | |
219 | ||
72e06d08 PW |
220 | extern struct pwrdm_ops omap2_pwrdm_operations; |
221 | extern struct pwrdm_ops omap3_pwrdm_operations; | |
222 | extern struct pwrdm_ops omap4_pwrdm_operations; | |
223 | ||
224 | /* Common Internal functions used across OMAP rev's */ | |
225 | extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank); | |
226 | extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank); | |
227 | extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank); | |
228 | ||
229 | extern struct powerdomain wkup_omap2_pwrdm; | |
230 | extern struct powerdomain gfx_omap2_pwrdm; | |
231 | ||
232 | ||
ad67ef68 | 233 | #endif |