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f327e07b RN |
1 | /* |
2 | * OMAP2 and OMAP3 powerdomain control | |
3 | * | |
4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. | |
5 | * Copyright (C) 2007-2009 Nokia Corporation | |
6 | * | |
7 | * Derived from mach-omap2/powerdomain.c written by Paul Walmsley | |
8 | * Rajendra Nayak <rnayak@ti.com> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/io.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/delay.h> | |
18 | #include <plat/prcm.h> | |
19 | #include "prm.h" | |
20 | #include "prm-regbits-34xx.h" | |
21 | #include "powerdomains.h" | |
22 | ||
23 | /* Common functions across OMAP2 and OMAP3 */ | |
24 | static int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) | |
25 | { | |
26 | prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, | |
27 | (pwrst << OMAP_POWERSTATE_SHIFT), | |
28 | pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); | |
29 | return 0; | |
30 | } | |
31 | ||
32 | static int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) | |
33 | { | |
34 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, | |
35 | OMAP2_PM_PWSTCTRL, OMAP_POWERSTATE_MASK); | |
36 | } | |
37 | ||
38 | static int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm) | |
39 | { | |
40 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, | |
41 | OMAP2_PM_PWSTST, OMAP_POWERSTATEST_MASK); | |
42 | } | |
43 | ||
12627578 RN |
44 | static int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) |
45 | { | |
46 | u32 v; | |
47 | ||
48 | v = pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE_MASK); | |
49 | prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v, | |
50 | pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); | |
51 | ||
52 | return 0; | |
53 | } | |
54 | ||
f327e07b RN |
55 | /* Applicable only for OMAP3. Not supported on OMAP2 */ |
56 | static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) | |
57 | { | |
58 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST, | |
59 | OMAP3430_LASTPOWERSTATEENTERED_MASK); | |
60 | } | |
61 | ||
12627578 RN |
62 | static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) |
63 | { | |
64 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, | |
65 | OMAP3430_LOGICSTATEST_MASK); | |
66 | } | |
67 | ||
68 | static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm) | |
69 | { | |
70 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL, | |
71 | OMAP3430_LOGICSTATEST_MASK); | |
72 | } | |
73 | ||
74 | static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) | |
75 | { | |
76 | return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST, | |
77 | OMAP3430_LASTLOGICSTATEENTERED_MASK); | |
78 | } | |
79 | ||
f327e07b RN |
80 | struct pwrdm_ops omap2_pwrdm_operations = { |
81 | .pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst, | |
82 | .pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst, | |
83 | .pwrdm_read_pwrst = omap2_pwrdm_read_pwrst, | |
12627578 | 84 | .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst, |
f327e07b RN |
85 | }; |
86 | ||
87 | struct pwrdm_ops omap3_pwrdm_operations = { | |
88 | .pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst, | |
89 | .pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst, | |
90 | .pwrdm_read_pwrst = omap2_pwrdm_read_pwrst, | |
91 | .pwrdm_read_prev_pwrst = omap3_pwrdm_read_prev_pwrst, | |
12627578 RN |
92 | .pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst, |
93 | .pwrdm_read_logic_pwrst = omap3_pwrdm_read_logic_pwrst, | |
94 | .pwrdm_read_logic_retst = omap3_pwrdm_read_logic_retst, | |
95 | .pwrdm_read_prev_logic_pwrst = omap3_pwrdm_read_prev_logic_pwrst, | |
f327e07b | 96 | }; |