[deliverable/linux.git] / arch / arm / mach-omap2 / powerdomains34xx.h

/*
 * OMAP3 powerdomain definitions
 *
 * Copyright (C) 2007-2008 Texas Instruments, Inc.
 * Copyright (C) 2007-2010 Nokia Corporation
 *
 * Written by Paul Walmsley
 * Debugging and integration fixes by Jouni Högander
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX

/*
 * N.B. If powerdomains are added or removed from this file, update
 * the array in mach-omap2/powerdomains.h.
 */

#include <plat/powerdomain.h>

#include "prcm-common.h"
#include "prm.h"
#include "prm-regbits-34xx.h"
#include "cm.h"
#include "cm-regbits-34xx.h"

/*
 * 34XX-specific powerdomains, dependencies
 */

#ifdef CONFIG_ARCH_OMAP3

/*
 * Powerdomains
 */

static struct powerdomain iva2_pwrdm = {
	.name		  = "iva2_pwrdm",
	.prcm_offs	  = OMAP3430_IVA2_MOD,
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 4,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,
		[1] = PWRSTS_OFF_RET,
		[2] = PWRSTS_OFF_RET,
		[3] = PWRSTS_OFF_RET,
	},
	.pwrsts_mem_on	  = {
		[0] = PWRDM_POWER_ON,
		[1] = PWRDM_POWER_ON,
		[2] = PWRSTS_OFF_ON,
		[3] = PWRDM_POWER_ON,
	},
};

static struct powerdomain mpu_3xxx_pwrdm = {
	.name		  = "mpu_pwrdm",
	.prcm_offs	  = MPU_MOD,
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.flags		  = PWRDM_HAS_MPU_QUIRK,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_OFF_ON,
	},
};

/*
 * The USBTLL Save-and-Restore mechanism is broken on
 * 3430s upto ES3.0 and 3630ES1.0. Hence this feature
 * needs to be disabled on these chips.
 * Refer: 3430 errata ID i459 and 3630 errata ID i579
 */
static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
	.name		  = "core_pwrdm",
	.prcm_offs	  = CORE_MOD,
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 |
					   CHIP_IS_OMAP3430ES2 |
					   CHIP_IS_OMAP3430ES3_0 |
					   CHIP_IS_OMAP3630ES1),
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 2,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,	 /* MEM1RETSTATE */
		[1] = PWRSTS_OFF_RET,	 /* MEM2RETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
		[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	},
};

static struct powerdomain core_3xxx_es3_1_pwrdm = {
	.name		  = "core_pwrdm",
	.prcm_offs	  = CORE_MOD,
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1 |
					  CHIP_GE_OMAP3630ES1_1),
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.flags		  = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
	.banks		  = 2,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,	 /* MEM1RETSTATE */
		[1] = PWRSTS_OFF_RET,	 /* MEM2RETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
		[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	},
};

static struct powerdomain dss_pwrdm = {
	.name		  = "dss_pwrdm",
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	.prcm_offs	  = OMAP3430_DSS_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRDM_POWER_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRDM_POWER_ON,  /* MEMONSTATE */
	},
};

/*
 * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
 * possible SGX powerstate, the SGX device itself does not support
 * retention.
 */
static struct powerdomain sgx_pwrdm = {
	.name		  = "sgx_pwrdm",
	.prcm_offs	  = OMAP3430ES2_SGX_MOD,
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
	/* XXX This is accurate for 3430 SGX, but what about GFX? */
	.pwrsts		  = PWRSTS_OFF_ON,
	.pwrsts_logic_ret = PWRDM_POWER_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRDM_POWER_ON,  /* MEMONSTATE */
	},
};

static struct powerdomain cam_pwrdm = {
	.name		  = "cam_pwrdm",
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	.prcm_offs	  = OMAP3430_CAM_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRDM_POWER_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRDM_POWER_ON,  /* MEMONSTATE */
	},
};

static struct powerdomain per_pwrdm = {
	.name		  = "per_pwrdm",
	.prcm_offs	  = OMAP3430_PER_MOD,
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRDM_POWER_ON,  /* MEMONSTATE */
	},
};

static struct powerdomain emu_pwrdm = {
	.name		= "emu_pwrdm",
	.prcm_offs	= OMAP3430_EMU_MOD,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct powerdomain neon_pwrdm = {
	.name		  = "neon_pwrdm",
	.prcm_offs	  = OMAP3430_NEON_MOD,
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRDM_POWER_RET,
};

static struct powerdomain usbhost_pwrdm = {
	.name		  = "usbhost_pwrdm",
	.prcm_offs	  = OMAP3430ES2_USBHOST_MOD,
	.omap_chip	  = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRDM_POWER_RET,
	/*
	 * REVISIT: Enabling usb host save and restore mechanism seems to
	 * leave the usb host domain permanently in ACTIVE mode after
	 * changing the usb host power domain state from OFF to active once.
	 * Disabling for now.
	 */
	/*.flags	  = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRDM_POWER_ON,  /* MEMONSTATE */
	},
};

static struct powerdomain dpll1_pwrdm = {
	.name		= "dpll1_pwrdm",
	.prcm_offs	= MPU_MOD,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct powerdomain dpll2_pwrdm = {
	.name		= "dpll2_pwrdm",
	.prcm_offs	= OMAP3430_IVA2_MOD,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct powerdomain dpll3_pwrdm = {
	.name		= "dpll3_pwrdm",
	.prcm_offs	= PLL_MOD,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct powerdomain dpll4_pwrdm = {
	.name		= "dpll4_pwrdm",
	.prcm_offs	= PLL_MOD,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};

static struct powerdomain dpll5_pwrdm = {
	.name		= "dpll5_pwrdm",
	.prcm_offs	= PLL_MOD,
	.omap_chip	= OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
};


#endif    /* CONFIG_ARCH_OMAP3 */


#endif
Commit	Line	Data
ecb24aa1	1	/*
98fa3d8a	2	* OMAP3 powerdomain definitions
ecb24aa1 PW	3	*
ecb24aa1 PW	4	* Copyright (C) 2007-2008 Texas Instruments, Inc.
98fa3d8a	5	* Copyright (C) 2007-2010 Nokia Corporation
ecb24aa1 PW	6	*
	7	* Written by Paul Walmsley
	8	* Debugging and integration fixes by Jouni Högander
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
	16	#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS34XX
	17
	18	/*
	19	* N.B. If powerdomains are added or removed from this file, update
	20	* the array in mach-omap2/powerdomains.h.
	21	*/
	22
ce491cf8	23	#include <plat/powerdomain.h>
ecb24aa1 PW	24
	25	#include "prcm-common.h"
	26	#include "prm.h"
	27	#include "prm-regbits-34xx.h"
	28	#include "cm.h"
	29	#include "cm-regbits-34xx.h"
	30
	31	/*
	32	* 34XX-specific powerdomains, dependencies
	33	*/
	34
98fa3d8a	35	#ifdef CONFIG_ARCH_OMAP3
ecb24aa1	36
ecb24aa1 PW	37	/*
	38	* Powerdomains
	39	*/
	40
	41	static struct powerdomain iva2_pwrdm = {
	42	.name = "iva2_pwrdm",
	43	.prcm_offs = OMAP3430_IVA2_MOD,
	44	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
ecb24aa1 PW	45	.pwrsts = PWRSTS_OFF_RET_ON,
	46	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	47	.banks = 4,
	48	.pwrsts_mem_ret = {
	49	[0] = PWRSTS_OFF_RET,
	50	[1] = PWRSTS_OFF_RET,
	51	[2] = PWRSTS_OFF_RET,
	52	[3] = PWRSTS_OFF_RET,
	53	},
	54	.pwrsts_mem_on = {
	55	[0] = PWRDM_POWER_ON,
	56	[1] = PWRDM_POWER_ON,
	57	[2] = PWRSTS_OFF_ON,
	58	[3] = PWRDM_POWER_ON,
	59	},
	60	};
	61
98fa3d8a	62	static struct powerdomain mpu_3xxx_pwrdm = {
ecb24aa1 PW	63	.name = "mpu_pwrdm",
	64	.prcm_offs = MPU_MOD,
	65	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
ecb24aa1 PW	66	.pwrsts = PWRSTS_OFF_RET_ON,
ecb24aa1 PW	67	.pwrsts_logic_ret = PWRSTS_OFF_RET,
3863c74b	68	.flags = PWRDM_HAS_MPU_QUIRK,
ecb24aa1 PW	69	.banks = 1,
	70	.pwrsts_mem_ret = {
	71	[0] = PWRSTS_OFF_RET,
	72	},
	73	.pwrsts_mem_on = {
	74	[0] = PWRSTS_OFF_ON,
	75	},
	76	};
	77
58dcfb3a AG	78	/*
	79	* The USBTLL Save-and-Restore mechanism is broken on
	80	* 3430s upto ES3.0 and 3630ES1.0. Hence this feature
	81	* needs to be disabled on these chips.
	82	* Refer: 3430 errata ID i459 and 3630 errata ID i579
	83	*/
98fa3d8a	84	static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
ecb24aa1 PW	85	.name = "core_pwrdm",
ecb24aa1 PW	86	.prcm_offs = CORE_MOD,
7eb1afc9 PW	87	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 \|
7eb1afc9 PW	88	CHIP_IS_OMAP3430ES2 \|
58dcfb3a AG	89	CHIP_IS_OMAP3430ES3_0 \|
58dcfb3a AG	90	CHIP_IS_OMAP3630ES1),
7eb1afc9	91	.pwrsts = PWRSTS_OFF_RET_ON,
4133a44e	92	.pwrsts_logic_ret = PWRSTS_OFF_RET,
7eb1afc9 PW	93	.banks = 2,
	94	.pwrsts_mem_ret = {
	95	[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
	96	[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
	97	},
	98	.pwrsts_mem_on = {
	99	[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
	100	[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	101	},
	102	};
	103
98fa3d8a	104	static struct powerdomain core_3xxx_es3_1_pwrdm = {
7eb1afc9 PW	105	.name = "core_pwrdm",
7eb1afc9 PW	106	.prcm_offs = CORE_MOD,
58dcfb3a AG	107	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1 \|
58dcfb3a AG	108	CHIP_GE_OMAP3630ES1_1),
ecb24aa1	109	.pwrsts = PWRSTS_OFF_RET_ON,
4133a44e	110	.pwrsts_logic_ret = PWRSTS_OFF_RET,
7eb1afc9	111	.flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
ecb24aa1 PW	112	.banks = 2,
	113	.pwrsts_mem_ret = {
	114	[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
	115	[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
	116	},
	117	.pwrsts_mem_on = {
	118	[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
	119	[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	120	},
	121	};
	122
ecb24aa1 PW	123	static struct powerdomain dss_pwrdm = {
	124	.name = "dss_pwrdm",
	125	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	126	.prcm_offs = OMAP3430_DSS_MOD,
ecb24aa1 PW	127	.pwrsts = PWRSTS_OFF_RET_ON,
	128	.pwrsts_logic_ret = PWRDM_POWER_RET,
	129	.banks = 1,
	130	.pwrsts_mem_ret = {
	131	[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	132	},
	133	.pwrsts_mem_on = {
	134	[0] = PWRDM_POWER_ON, /* MEMONSTATE */
	135	},
	136	};
	137
be48ea74 PW	138	/*
	139	* Although the 34XX TRM Rev K Table 4-371 notes that retention is a
	140	* possible SGX powerstate, the SGX device itself does not support
	141	* retention.
	142	*/
ecb24aa1 PW	143	static struct powerdomain sgx_pwrdm = {
	144	.name = "sgx_pwrdm",
	145	.prcm_offs = OMAP3430ES2_SGX_MOD,
d41ad520	146	.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
ecb24aa1	147	/* XXX This is accurate for 3430 SGX, but what about GFX? */
be48ea74	148	.pwrsts = PWRSTS_OFF_ON,
ecb24aa1 PW	149	.pwrsts_logic_ret = PWRDM_POWER_RET,
	150	.banks = 1,
	151	.pwrsts_mem_ret = {
	152	[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	153	},
	154	.pwrsts_mem_on = {
	155	[0] = PWRDM_POWER_ON, /* MEMONSTATE */
	156	},
	157	};
	158
	159	static struct powerdomain cam_pwrdm = {
	160	.name = "cam_pwrdm",
	161	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	162	.prcm_offs = OMAP3430_CAM_MOD,
ecb24aa1 PW	163	.pwrsts = PWRSTS_OFF_RET_ON,
	164	.pwrsts_logic_ret = PWRDM_POWER_RET,
	165	.banks = 1,
	166	.pwrsts_mem_ret = {
	167	[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	168	},
	169	.pwrsts_mem_on = {
	170	[0] = PWRDM_POWER_ON, /* MEMONSTATE */
	171	},
	172	};
	173
	174	static struct powerdomain per_pwrdm = {
	175	.name = "per_pwrdm",
	176	.prcm_offs = OMAP3430_PER_MOD,
	177	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
ecb24aa1 PW	178	.pwrsts = PWRSTS_OFF_RET_ON,
	179	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	180	.banks = 1,
	181	.pwrsts_mem_ret = {
	182	[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	183	},
	184	.pwrsts_mem_on = {
	185	[0] = PWRDM_POWER_ON, /* MEMONSTATE */
	186	},
	187	};
	188
	189	static struct powerdomain emu_pwrdm = {
	190	.name = "emu_pwrdm",
	191	.prcm_offs = OMAP3430_EMU_MOD,
	192	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	193	};
	194
	195	static struct powerdomain neon_pwrdm = {
	196	.name = "neon_pwrdm",
	197	.prcm_offs = OMAP3430_NEON_MOD,
	198	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
ecb24aa1 PW	199	.pwrsts = PWRSTS_OFF_RET_ON,
	200	.pwrsts_logic_ret = PWRDM_POWER_RET,
	201	};
	202
	203	static struct powerdomain usbhost_pwrdm = {
	204	.name = "usbhost_pwrdm",
	205	.prcm_offs = OMAP3430ES2_USBHOST_MOD,
d41ad520	206	.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
ecb24aa1 PW	207	.pwrsts = PWRSTS_OFF_RET_ON,
ecb24aa1 PW	208	.pwrsts_logic_ret = PWRDM_POWER_RET,
867d320b KJ	209	/*
	210	* REVISIT: Enabling usb host save and restore mechanism seems to
	211	* leave the usb host domain permanently in ACTIVE mode after
	212	* changing the usb host power domain state from OFF to active once.
	213	* Disabling for now.
	214	*/
	215	/.flags = PWRDM_HAS_HDWR_SAR,/ /* for USBHOST ctrlr only */
ecb24aa1 PW	216	.banks = 1,
	217	.pwrsts_mem_ret = {
	218	[0] = PWRDM_POWER_RET, /* MEMRETSTATE */
	219	},
	220	.pwrsts_mem_on = {
	221	[0] = PWRDM_POWER_ON, /* MEMONSTATE */
	222	},
	223	};
	224
46e0ccf8 PW	225	static struct powerdomain dpll1_pwrdm = {
	226	.name = "dpll1_pwrdm",
	227	.prcm_offs = MPU_MOD,
	228	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	229	};
	230
	231	static struct powerdomain dpll2_pwrdm = {
	232	.name = "dpll2_pwrdm",
	233	.prcm_offs = OMAP3430_IVA2_MOD,
	234	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	235	};
	236
	237	static struct powerdomain dpll3_pwrdm = {
	238	.name = "dpll3_pwrdm",
	239	.prcm_offs = PLL_MOD,
	240	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	241	};
	242
	243	static struct powerdomain dpll4_pwrdm = {
	244	.name = "dpll4_pwrdm",
	245	.prcm_offs = PLL_MOD,
	246	.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
	247	};
	248
	249	static struct powerdomain dpll5_pwrdm = {
	250	.name = "dpll5_pwrdm",
	251	.prcm_offs = PLL_MOD,
d41ad520	252	.omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
46e0ccf8 PW	253	};
	254
	255
98fa3d8a	256	#endif /* CONFIG_ARCH_OMAP3 */
ecb24aa1 PW	257
	258
	259	#endif