[deliverable/linux.git] / arch / arm / mach-omap2 / powerdomains3xxx_data.c

/*
 * OMAP3 powerdomain definitions
 *
 * Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
 * Copyright (C) 2007-2011 Nokia Corporation
 *
 * Paul Walmsley, Jouni Högander
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/bug.h>

#include <plat/cpu.h>

#include "powerdomain.h"
#include "powerdomains2xxx_3xxx_data.h"

#include "prcm-common.h"
#include "prm2xxx_3xxx.h"
#include "prm-regbits-34xx.h"
#include "cm2xxx_3xxx.h"
#include "cm-regbits-34xx.h"

/*
 * 34XX-specific powerdomains, dependencies
 */

/*
 * Powerdomains
 */

static struct powerdomain iva2_pwrdm = {
	.name		  = "iva2_pwrdm",
	.prcm_offs	  = OMAP3430_IVA2_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 4,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,
		[1] = PWRSTS_OFF_RET,
		[2] = PWRSTS_OFF_RET,
		[3] = PWRSTS_OFF_RET,
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,
		[1] = PWRSTS_ON,
		[2] = PWRSTS_OFF_ON,
		[3] = PWRSTS_ON,
	},
	.voltdm           = { .name = "mpu_iva" },
};

static struct powerdomain mpu_3xxx_pwrdm = {
	.name		  = "mpu_pwrdm",
	.prcm_offs	  = MPU_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.flags		  = PWRDM_HAS_MPU_QUIRK,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_OFF_ON,
	},
	.voltdm           = { .name = "mpu_iva" },
};

static struct powerdomain mpu_am35x_pwrdm = {
	.name		  = "mpu_pwrdm",
	.prcm_offs	  = MPU_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.flags		  = PWRDM_HAS_MPU_QUIRK,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_ON,
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,
	},
	.voltdm           = { .name = "mpu_iva" },
};

/*
 * The USBTLL Save-and-Restore mechanism is broken on
 * 3430s up to ES3.0 and 3630ES1.0. Hence this feature
 * needs to be disabled on these chips.
 * Refer: 3430 errata ID i459 and 3630 errata ID i579
 *
 * Note: setting the SAR flag could help for errata ID i478
 *  which applies to 3430 <= ES3.1, but since the SAR feature
 *  is broken, do not use it.
 */
static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
	.name		  = "core_pwrdm",
	.prcm_offs	  = CORE_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 2,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,	 /* MEM1RETSTATE */
		[1] = PWRSTS_OFF_RET,	 /* MEM2RETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
		[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	},
	.voltdm           = { .name = "core" },
};

static struct powerdomain core_3xxx_es3_1_pwrdm = {
	.name		  = "core_pwrdm",
	.prcm_offs	  = CORE_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	/*
	 * Setting the SAR flag for errata ID i478 which applies
	 *  to 3430 <= ES3.1
	 */
	.flags		  = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
	.banks		  = 2,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_OFF_RET,	 /* MEM1RETSTATE */
		[1] = PWRSTS_OFF_RET,	 /* MEM2RETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
		[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	},
	.voltdm           = { .name = "core" },
};

static struct powerdomain core_am35x_pwrdm = {
	.name		  = "core_pwrdm",
	.prcm_offs	  = CORE_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.banks		  = 2,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_ON,	 /* MEM1RETSTATE */
		[1] = PWRSTS_ON,	 /* MEM2RETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON, /* MEM1ONSTATE */
		[1] = PWRSTS_ON, /* MEM2ONSTATE */
	},
	.voltdm           = { .name = "core" },
};

static struct powerdomain dss_pwrdm = {
	.name		  = "dss_pwrdm",
	.prcm_offs	  = OMAP3430_DSS_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm           = { .name = "core" },
};

static struct powerdomain dss_am35x_pwrdm = {
	.name		  = "dss_pwrdm",
	.prcm_offs	  = OMAP3430_DSS_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_ON, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm           = { .name = "core" },
};

/*
 * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
 * possible SGX powerstate, the SGX device itself does not support
 * retention.
 */
static struct powerdomain sgx_pwrdm = {
	.name		  = "sgx_pwrdm",
	.prcm_offs	  = OMAP3430ES2_SGX_MOD,
	/* XXX This is accurate for 3430 SGX, but what about GFX? */
	.pwrsts		  = PWRSTS_OFF_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm           = { .name = "core" },
};

static struct powerdomain sgx_am35x_pwrdm = {
	.name		  = "sgx_pwrdm",
	.prcm_offs	  = OMAP3430ES2_SGX_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_ON, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm           = { .name = "core" },
};

static struct powerdomain cam_pwrdm = {
	.name		  = "cam_pwrdm",
	.prcm_offs	  = OMAP3430_CAM_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm           = { .name = "core" },
};

static struct powerdomain per_pwrdm = {
	.name		  = "per_pwrdm",
	.prcm_offs	  = OMAP3430_PER_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm           = { .name = "core" },
};

static struct powerdomain per_am35x_pwrdm = {
	.name		  = "per_pwrdm",
	.prcm_offs	  = OMAP3430_PER_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_ON, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm           = { .name = "core" },
};

static struct powerdomain emu_pwrdm = {
	.name		= "emu_pwrdm",
	.prcm_offs	= OMAP3430_EMU_MOD,
	.voltdm           = { .name = "core" },
};

static struct powerdomain neon_pwrdm = {
	.name		  = "neon_pwrdm",
	.prcm_offs	  = OMAP3430_NEON_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.voltdm           = { .name = "mpu_iva" },
};

static struct powerdomain neon_am35x_pwrdm = {
	.name		  = "neon_pwrdm",
	.prcm_offs	  = OMAP3430_NEON_MOD,
	.pwrsts		  = PWRSTS_ON,
	.pwrsts_logic_ret = PWRSTS_ON,
	.voltdm           = { .name = "mpu_iva" },
};

static struct powerdomain usbhost_pwrdm = {
	.name		  = "usbhost_pwrdm",
	.prcm_offs	  = OMAP3430ES2_USBHOST_MOD,
	.pwrsts		  = PWRSTS_OFF_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	/*
	 * REVISIT: Enabling usb host save and restore mechanism seems to
	 * leave the usb host domain permanently in ACTIVE mode after
	 * changing the usb host power domain state from OFF to active once.
	 * Disabling for now.
	 */
	/*.flags	  = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
	.banks		  = 1,
	.pwrsts_mem_ret	  = {
		[0] = PWRSTS_RET, /* MEMRETSTATE */
	},
	.pwrsts_mem_on	  = {
		[0] = PWRSTS_ON,  /* MEMONSTATE */
	},
	.voltdm           = { .name = "core" },
};

static struct powerdomain dpll1_pwrdm = {
	.name		= "dpll1_pwrdm",
	.prcm_offs	= MPU_MOD,
	.voltdm           = { .name = "mpu_iva" },
};

static struct powerdomain dpll2_pwrdm = {
	.name		= "dpll2_pwrdm",
	.prcm_offs	= OMAP3430_IVA2_MOD,
	.voltdm           = { .name = "mpu_iva" },
};

static struct powerdomain dpll3_pwrdm = {
	.name		= "dpll3_pwrdm",
	.prcm_offs	= PLL_MOD,
	.voltdm           = { .name = "core" },
};

static struct powerdomain dpll4_pwrdm = {
	.name		= "dpll4_pwrdm",
	.prcm_offs	= PLL_MOD,
	.voltdm           = { .name = "core" },
};

static struct powerdomain dpll5_pwrdm = {
	.name		= "dpll5_pwrdm",
	.prcm_offs	= PLL_MOD,
	.voltdm           = { .name = "core" },
};

/* As powerdomains are added or removed above, this list must also be changed */
static struct powerdomain *powerdomains_omap3430_common[] __initdata = {
	&wkup_omap2_pwrdm,
	&iva2_pwrdm,
	&mpu_3xxx_pwrdm,
	&neon_pwrdm,
	&cam_pwrdm,
	&dss_pwrdm,
	&per_pwrdm,
	&emu_pwrdm,
	&dpll1_pwrdm,
	&dpll2_pwrdm,
	&dpll3_pwrdm,
	&dpll4_pwrdm,
	NULL
};

static struct powerdomain *powerdomains_omap3430es1[] __initdata = {
	&gfx_omap2_pwrdm,
	&core_3xxx_pre_es3_1_pwrdm,
	NULL
};

/* also includes 3630ES1.0 */
static struct powerdomain *powerdomains_omap3430es2_es3_0[] __initdata = {
	&core_3xxx_pre_es3_1_pwrdm,
	&sgx_pwrdm,
	&usbhost_pwrdm,
	&dpll5_pwrdm,
	NULL
};

/* also includes 3630ES1.1+ */
static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = {
	&core_3xxx_es3_1_pwrdm,
	&sgx_pwrdm,
	&usbhost_pwrdm,
	&dpll5_pwrdm,
	NULL
};

static struct powerdomain *powerdomains_am35x[] __initdata = {
	&wkup_omap2_pwrdm,
	&mpu_am35x_pwrdm,
	&neon_am35x_pwrdm,
	&core_am35x_pwrdm,
	&sgx_am35x_pwrdm,
	&dss_am35x_pwrdm,
	&per_am35x_pwrdm,
	&emu_pwrdm,
	&dpll1_pwrdm,
	&dpll3_pwrdm,
	&dpll4_pwrdm,
	&dpll5_pwrdm,
	NULL
};

void __init omap3xxx_powerdomains_init(void)
{
	unsigned int rev;

	if (!cpu_is_omap34xx())
		return;

	pwrdm_register_platform_funcs(&omap3_pwrdm_operations);

	rev = omap_rev();

	if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
		pwrdm_register_pwrdms(powerdomains_am35x);
	} else {
		pwrdm_register_pwrdms(powerdomains_omap3430_common);

		switch (rev) {
		case OMAP3430_REV_ES1_0:
			pwrdm_register_pwrdms(powerdomains_omap3430es1);
			break;
		case OMAP3430_REV_ES2_0:
		case OMAP3430_REV_ES2_1:
		case OMAP3430_REV_ES3_0:
		case OMAP3630_REV_ES1_0:
			pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
			break;
		case OMAP3430_REV_ES3_1:
		case OMAP3430_REV_ES3_1_2:
		case OMAP3630_REV_ES1_1:
		case OMAP3630_REV_ES1_2:
			pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
			break;
		default:
			WARN(1, "OMAP3 powerdomain init: unknown chip type\n");
		}
	}

	pwrdm_complete_init();
}
Commit	Line	Data
ecb24aa1	1	/*
98fa3d8a	2	* OMAP3 powerdomain definitions
ecb24aa1	3	*
8179488a	4	* Copyright (C) 2007-2008, 2011 Texas Instruments, Inc.
4cb49fec	5	* Copyright (C) 2007-2011 Nokia Corporation
ecb24aa1	6	*
6e01478a	7	* Paul Walmsley, Jouni Högander
ecb24aa1 PW	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
	13
6e01478a PW	14	#include <linux/kernel.h>
6e01478a PW	15	#include <linux/init.h>
d9a5f4dd	16	#include <linux/bug.h>
ecb24aa1	17
8179488a PW	18	#include <plat/cpu.h>
8179488a PW	19
72e06d08	20	#include "powerdomain.h"
6e01478a	21	#include "powerdomains2xxx_3xxx_data.h"
ecb24aa1 PW	22
ecb24aa1 PW	23	#include "prcm-common.h"
59fb659b	24	#include "prm2xxx_3xxx.h"
ecb24aa1	25	#include "prm-regbits-34xx.h"
59fb659b	26	#include "cm2xxx_3xxx.h"
ecb24aa1 PW	27	#include "cm-regbits-34xx.h"
	28
	29	/*
	30	* 34XX-specific powerdomains, dependencies
	31	*/
	32
ecb24aa1 PW	33	/*
	34	* Powerdomains
	35	*/
	36
	37	static struct powerdomain iva2_pwrdm = {
	38	.name = "iva2_pwrdm",
	39	.prcm_offs = OMAP3430_IVA2_MOD,
ecb24aa1 PW	40	.pwrsts = PWRSTS_OFF_RET_ON,
	41	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	42	.banks = 4,
	43	.pwrsts_mem_ret = {
	44	[0] = PWRSTS_OFF_RET,
	45	[1] = PWRSTS_OFF_RET,
	46	[2] = PWRSTS_OFF_RET,
	47	[3] = PWRSTS_OFF_RET,
	48	},
	49	.pwrsts_mem_on = {
4cb49fec PW	50	[0] = PWRSTS_ON,
4cb49fec PW	51	[1] = PWRSTS_ON,
ecb24aa1	52	[2] = PWRSTS_OFF_ON,
4cb49fec	53	[3] = PWRSTS_ON,
ecb24aa1	54	},
da03ce65	55	.voltdm = { .name = "mpu_iva" },
ecb24aa1 PW	56	};
ecb24aa1 PW	57
98fa3d8a	58	static struct powerdomain mpu_3xxx_pwrdm = {
ecb24aa1 PW	59	.name = "mpu_pwrdm",
ecb24aa1 PW	60	.prcm_offs = MPU_MOD,
ecb24aa1 PW	61	.pwrsts = PWRSTS_OFF_RET_ON,
ecb24aa1 PW	62	.pwrsts_logic_ret = PWRSTS_OFF_RET,
3863c74b	63	.flags = PWRDM_HAS_MPU_QUIRK,
ecb24aa1 PW	64	.banks = 1,
	65	.pwrsts_mem_ret = {
	66	[0] = PWRSTS_OFF_RET,
	67	},
	68	.pwrsts_mem_on = {
	69	[0] = PWRSTS_OFF_ON,
	70	},
da03ce65	71	.voltdm = { .name = "mpu_iva" },
ecb24aa1 PW	72	};
ecb24aa1 PW	73
ff7ad7e4 MG	74	static struct powerdomain mpu_am35x_pwrdm = {
	75	.name = "mpu_pwrdm",
	76	.prcm_offs = MPU_MOD,
	77	.pwrsts = PWRSTS_ON,
	78	.pwrsts_logic_ret = PWRSTS_ON,
	79	.flags = PWRDM_HAS_MPU_QUIRK,
	80	.banks = 1,
	81	.pwrsts_mem_ret = {
	82	[0] = PWRSTS_ON,
	83	},
	84	.pwrsts_mem_on = {
	85	[0] = PWRSTS_ON,
	86	},
	87	.voltdm = { .name = "mpu_iva" },
	88	};
	89
58dcfb3a AG	90	/*
58dcfb3a AG	91	* The USBTLL Save-and-Restore mechanism is broken on
25985edc	92	* 3430s up to ES3.0 and 3630ES1.0. Hence this feature
58dcfb3a AG	93	* needs to be disabled on these chips.
58dcfb3a AG	94	* Refer: 3430 errata ID i459 and 3630 errata ID i579
447b8da5 JP	95	*
	96	* Note: setting the SAR flag could help for errata ID i478
	97	* which applies to 3430 <= ES3.1, but since the SAR feature
	98	* is broken, do not use it.
58dcfb3a	99	*/
98fa3d8a	100	static struct powerdomain core_3xxx_pre_es3_1_pwrdm = {
ecb24aa1 PW	101	.name = "core_pwrdm",
ecb24aa1 PW	102	.prcm_offs = CORE_MOD,
7eb1afc9	103	.pwrsts = PWRSTS_OFF_RET_ON,
4133a44e	104	.pwrsts_logic_ret = PWRSTS_OFF_RET,
7eb1afc9 PW	105	.banks = 2,
	106	.pwrsts_mem_ret = {
	107	[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
	108	[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
	109	},
	110	.pwrsts_mem_on = {
	111	[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
	112	[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	113	},
da03ce65	114	.voltdm = { .name = "core" },
7eb1afc9 PW	115	};
7eb1afc9 PW	116
98fa3d8a	117	static struct powerdomain core_3xxx_es3_1_pwrdm = {
7eb1afc9 PW	118	.name = "core_pwrdm",
7eb1afc9 PW	119	.prcm_offs = CORE_MOD,
ecb24aa1	120	.pwrsts = PWRSTS_OFF_RET_ON,
4133a44e	121	.pwrsts_logic_ret = PWRSTS_OFF_RET,
447b8da5 JP	122	/*
	123	* Setting the SAR flag for errata ID i478 which applies
	124	* to 3430 <= ES3.1
	125	*/
7eb1afc9	126	.flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */
ecb24aa1 PW	127	.banks = 2,
	128	.pwrsts_mem_ret = {
	129	[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */
	130	[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */
	131	},
	132	.pwrsts_mem_on = {
	133	[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */
	134	[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */
	135	},
da03ce65	136	.voltdm = { .name = "core" },
ecb24aa1 PW	137	};
ecb24aa1 PW	138
ff7ad7e4 MG	139	static struct powerdomain core_am35x_pwrdm = {
	140	.name = "core_pwrdm",
	141	.prcm_offs = CORE_MOD,
	142	.pwrsts = PWRSTS_ON,
	143	.pwrsts_logic_ret = PWRSTS_ON,
	144	.banks = 2,
	145	.pwrsts_mem_ret = {
	146	[0] = PWRSTS_ON, /* MEM1RETSTATE */
	147	[1] = PWRSTS_ON, /* MEM2RETSTATE */
	148	},
	149	.pwrsts_mem_on = {
	150	[0] = PWRSTS_ON, /* MEM1ONSTATE */
	151	[1] = PWRSTS_ON, /* MEM2ONSTATE */
	152	},
	153	.voltdm = { .name = "core" },
	154	};
	155
ecb24aa1 PW	156	static struct powerdomain dss_pwrdm = {
ecb24aa1 PW	157	.name = "dss_pwrdm",
ecb24aa1	158	.prcm_offs = OMAP3430_DSS_MOD,
ecb24aa1	159	.pwrsts = PWRSTS_OFF_RET_ON,
4cb49fec	160	.pwrsts_logic_ret = PWRSTS_RET,
ecb24aa1 PW	161	.banks = 1,
ecb24aa1 PW	162	.pwrsts_mem_ret = {
4cb49fec	163	[0] = PWRSTS_RET, /* MEMRETSTATE */
ecb24aa1 PW	164	},
ecb24aa1 PW	165	.pwrsts_mem_on = {
4cb49fec	166	[0] = PWRSTS_ON, /* MEMONSTATE */
ecb24aa1	167	},
da03ce65	168	.voltdm = { .name = "core" },
ecb24aa1 PW	169	};
ecb24aa1 PW	170
ff7ad7e4 MG	171	static struct powerdomain dss_am35x_pwrdm = {
	172	.name = "dss_pwrdm",
	173	.prcm_offs = OMAP3430_DSS_MOD,
	174	.pwrsts = PWRSTS_ON,
	175	.pwrsts_logic_ret = PWRSTS_ON,
	176	.banks = 1,
	177	.pwrsts_mem_ret = {
	178	[0] = PWRSTS_ON, /* MEMRETSTATE */
	179	},
	180	.pwrsts_mem_on = {
	181	[0] = PWRSTS_ON, /* MEMONSTATE */
	182	},
	183	.voltdm = { .name = "core" },
	184	};
	185
be48ea74 PW	186	/*
	187	* Although the 34XX TRM Rev K Table 4-371 notes that retention is a
	188	* possible SGX powerstate, the SGX device itself does not support
	189	* retention.
	190	*/
ecb24aa1 PW	191	static struct powerdomain sgx_pwrdm = {
	192	.name = "sgx_pwrdm",
	193	.prcm_offs = OMAP3430ES2_SGX_MOD,
ecb24aa1	194	/* XXX This is accurate for 3430 SGX, but what about GFX? */
be48ea74	195	.pwrsts = PWRSTS_OFF_ON,
4cb49fec	196	.pwrsts_logic_ret = PWRSTS_RET,
ecb24aa1 PW	197	.banks = 1,
ecb24aa1 PW	198	.pwrsts_mem_ret = {
4cb49fec	199	[0] = PWRSTS_RET, /* MEMRETSTATE */
ecb24aa1 PW	200	},
ecb24aa1 PW	201	.pwrsts_mem_on = {
4cb49fec	202	[0] = PWRSTS_ON, /* MEMONSTATE */
ecb24aa1	203	},
da03ce65	204	.voltdm = { .name = "core" },
ecb24aa1 PW	205	};
ecb24aa1 PW	206
ff7ad7e4 MG	207	static struct powerdomain sgx_am35x_pwrdm = {
	208	.name = "sgx_pwrdm",
	209	.prcm_offs = OMAP3430ES2_SGX_MOD,
	210	.pwrsts = PWRSTS_ON,
	211	.pwrsts_logic_ret = PWRSTS_ON,
	212	.banks = 1,
	213	.pwrsts_mem_ret = {
	214	[0] = PWRSTS_ON, /* MEMRETSTATE */
	215	},
	216	.pwrsts_mem_on = {
	217	[0] = PWRSTS_ON, /* MEMONSTATE */
	218	},
	219	.voltdm = { .name = "core" },
	220	};
	221
ecb24aa1 PW	222	static struct powerdomain cam_pwrdm = {
ecb24aa1 PW	223	.name = "cam_pwrdm",
ecb24aa1	224	.prcm_offs = OMAP3430_CAM_MOD,
ecb24aa1	225	.pwrsts = PWRSTS_OFF_RET_ON,
4cb49fec	226	.pwrsts_logic_ret = PWRSTS_RET,
ecb24aa1 PW	227	.banks = 1,
ecb24aa1 PW	228	.pwrsts_mem_ret = {
4cb49fec	229	[0] = PWRSTS_RET, /* MEMRETSTATE */
ecb24aa1 PW	230	},
ecb24aa1 PW	231	.pwrsts_mem_on = {
4cb49fec	232	[0] = PWRSTS_ON, /* MEMONSTATE */
ecb24aa1	233	},
da03ce65	234	.voltdm = { .name = "core" },
ecb24aa1 PW	235	};
	236
	237	static struct powerdomain per_pwrdm = {
	238	.name = "per_pwrdm",
	239	.prcm_offs = OMAP3430_PER_MOD,
ecb24aa1 PW	240	.pwrsts = PWRSTS_OFF_RET_ON,
	241	.pwrsts_logic_ret = PWRSTS_OFF_RET,
	242	.banks = 1,
	243	.pwrsts_mem_ret = {
4cb49fec	244	[0] = PWRSTS_RET, /* MEMRETSTATE */
ecb24aa1 PW	245	},
ecb24aa1 PW	246	.pwrsts_mem_on = {
4cb49fec	247	[0] = PWRSTS_ON, /* MEMONSTATE */
ecb24aa1	248	},
da03ce65	249	.voltdm = { .name = "core" },
ecb24aa1 PW	250	};
ecb24aa1 PW	251
ff7ad7e4 MG	252	static struct powerdomain per_am35x_pwrdm = {
	253	.name = "per_pwrdm",
	254	.prcm_offs = OMAP3430_PER_MOD,
	255	.pwrsts = PWRSTS_ON,
	256	.pwrsts_logic_ret = PWRSTS_ON,
	257	.banks = 1,
	258	.pwrsts_mem_ret = {
	259	[0] = PWRSTS_ON, /* MEMRETSTATE */
	260	},
	261	.pwrsts_mem_on = {
	262	[0] = PWRSTS_ON, /* MEMONSTATE */
	263	},
	264	.voltdm = { .name = "core" },
	265	};
	266
ecb24aa1 PW	267	static struct powerdomain emu_pwrdm = {
	268	.name = "emu_pwrdm",
	269	.prcm_offs = OMAP3430_EMU_MOD,
da03ce65	270	.voltdm = { .name = "core" },
ecb24aa1 PW	271	};
	272
	273	static struct powerdomain neon_pwrdm = {
	274	.name = "neon_pwrdm",
	275	.prcm_offs = OMAP3430_NEON_MOD,
ecb24aa1	276	.pwrsts = PWRSTS_OFF_RET_ON,
4cb49fec	277	.pwrsts_logic_ret = PWRSTS_RET,
da03ce65	278	.voltdm = { .name = "mpu_iva" },
ecb24aa1 PW	279	};
ecb24aa1 PW	280
ff7ad7e4 MG	281	static struct powerdomain neon_am35x_pwrdm = {
	282	.name = "neon_pwrdm",
	283	.prcm_offs = OMAP3430_NEON_MOD,
	284	.pwrsts = PWRSTS_ON,
	285	.pwrsts_logic_ret = PWRSTS_ON,
	286	.voltdm = { .name = "mpu_iva" },
	287	};
	288
ecb24aa1 PW	289	static struct powerdomain usbhost_pwrdm = {
	290	.name = "usbhost_pwrdm",
	291	.prcm_offs = OMAP3430ES2_USBHOST_MOD,
ecb24aa1	292	.pwrsts = PWRSTS_OFF_RET_ON,
4cb49fec	293	.pwrsts_logic_ret = PWRSTS_RET,
867d320b KJ	294	/*
	295	* REVISIT: Enabling usb host save and restore mechanism seems to
	296	* leave the usb host domain permanently in ACTIVE mode after
	297	* changing the usb host power domain state from OFF to active once.
	298	* Disabling for now.
	299	*/
	300	/.flags = PWRDM_HAS_HDWR_SAR,/ /* for USBHOST ctrlr only */
ecb24aa1 PW	301	.banks = 1,
ecb24aa1 PW	302	.pwrsts_mem_ret = {
4cb49fec	303	[0] = PWRSTS_RET, /* MEMRETSTATE */
ecb24aa1 PW	304	},
ecb24aa1 PW	305	.pwrsts_mem_on = {
4cb49fec	306	[0] = PWRSTS_ON, /* MEMONSTATE */
ecb24aa1	307	},
da03ce65	308	.voltdm = { .name = "core" },
ecb24aa1 PW	309	};
ecb24aa1 PW	310
46e0ccf8 PW	311	static struct powerdomain dpll1_pwrdm = {
	312	.name = "dpll1_pwrdm",
	313	.prcm_offs = MPU_MOD,
da03ce65	314	.voltdm = { .name = "mpu_iva" },
46e0ccf8 PW	315	};
	316
	317	static struct powerdomain dpll2_pwrdm = {
	318	.name = "dpll2_pwrdm",
	319	.prcm_offs = OMAP3430_IVA2_MOD,
da03ce65	320	.voltdm = { .name = "mpu_iva" },
46e0ccf8 PW	321	};
	322
	323	static struct powerdomain dpll3_pwrdm = {
	324	.name = "dpll3_pwrdm",
	325	.prcm_offs = PLL_MOD,
da03ce65	326	.voltdm = { .name = "core" },
46e0ccf8 PW	327	};
	328
	329	static struct powerdomain dpll4_pwrdm = {
	330	.name = "dpll4_pwrdm",
	331	.prcm_offs = PLL_MOD,
da03ce65	332	.voltdm = { .name = "core" },
46e0ccf8 PW	333	};
	334
	335	static struct powerdomain dpll5_pwrdm = {
	336	.name = "dpll5_pwrdm",
	337	.prcm_offs = PLL_MOD,
da03ce65	338	.voltdm = { .name = "core" },
46e0ccf8 PW	339	};
46e0ccf8 PW	340
6e01478a	341	/* As powerdomains are added or removed above, this list must also be changed */
8179488a	342	static struct powerdomain *powerdomains_omap3430_common[] __initdata = {
6e01478a	343	&wkup_omap2_pwrdm,
6e01478a PW	344	&iva2_pwrdm,
	345	&mpu_3xxx_pwrdm,
	346	&neon_pwrdm,
6e01478a PW	347	&cam_pwrdm,
	348	&dss_pwrdm,
	349	&per_pwrdm,
	350	&emu_pwrdm,
6e01478a PW	351	&dpll1_pwrdm,
	352	&dpll2_pwrdm,
	353	&dpll3_pwrdm,
	354	&dpll4_pwrdm,
8179488a PW	355	NULL
	356	};
	357
	358	static struct powerdomain *powerdomains_omap3430es1[] __initdata = {
	359	&gfx_omap2_pwrdm,
	360	&core_3xxx_pre_es3_1_pwrdm,
	361	NULL
	362	};
	363
	364	/* also includes 3630ES1.0 */
	365	static struct powerdomain *powerdomains_omap3430es2_es3_0[] __initdata = {
	366	&core_3xxx_pre_es3_1_pwrdm,
	367	&sgx_pwrdm,
	368	&usbhost_pwrdm,
6e01478a	369	&dpll5_pwrdm,
6e01478a PW	370	NULL
6e01478a PW	371	};
ecb24aa1	372
8179488a PW	373	/* also includes 3630ES1.1+ */
	374	static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = {
	375	&core_3xxx_es3_1_pwrdm,
	376	&sgx_pwrdm,
	377	&usbhost_pwrdm,
	378	&dpll5_pwrdm,
	379	NULL
	380	};
ecb24aa1	381
ff7ad7e4 MG	382	static struct powerdomain *powerdomains_am35x[] __initdata = {
	383	&wkup_omap2_pwrdm,
	384	&mpu_am35x_pwrdm,
	385	&neon_am35x_pwrdm,
	386	&core_am35x_pwrdm,
	387	&sgx_am35x_pwrdm,
	388	&dss_am35x_pwrdm,
	389	&per_am35x_pwrdm,
	390	&emu_pwrdm,
	391	&dpll1_pwrdm,
	392	&dpll3_pwrdm,
	393	&dpll4_pwrdm,
	394	&dpll5_pwrdm,
	395	NULL
	396	};
	397
6e01478a PW	398	void __init omap3xxx_powerdomains_init(void)
6e01478a PW	399	{
8179488a PW	400	unsigned int rev;
	401
	402	if (!cpu_is_omap34xx())
	403	return;
	404
129c65ee	405	pwrdm_register_platform_funcs(&omap3_pwrdm_operations);
8179488a PW	406
	407	rev = omap_rev();
	408
ff7ad7e4 MG	409	if (rev == AM35XX_REV_ES1_0 \|\| rev == AM35XX_REV_ES1_1) {
	410	pwrdm_register_pwrdms(powerdomains_am35x);
	411	} else {
	412	pwrdm_register_pwrdms(powerdomains_omap3430_common);
	413
	414	switch (rev) {
	415	case OMAP3430_REV_ES1_0:
	416	pwrdm_register_pwrdms(powerdomains_omap3430es1);
	417	break;
	418	case OMAP3430_REV_ES2_0:
	419	case OMAP3430_REV_ES2_1:
	420	case OMAP3430_REV_ES3_0:
	421	case OMAP3630_REV_ES1_0:
	422	pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
	423	break;
	424	case OMAP3430_REV_ES3_1:
	425	case OMAP3430_REV_ES3_1_2:
	426	case OMAP3630_REV_ES1_1:
	427	case OMAP3630_REV_ES1_2:
	428	pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
	429	break;
	430	default:
	431	WARN(1, "OMAP3 powerdomain init: unknown chip type\n");
	432	}
	433	}
8179488a	434
129c65ee	435	pwrdm_complete_init();
6e01478a	436	}