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TI816X: Update common OMAP machine specific sources
[deliverable/linux.git] / arch / arm / mach-omap2 / powerdomains44xx_data.c
CommitLineData
f37c6dfa
AP		 1/*
2 * OMAP4 Power domains framework
3 *
79328706
BC		 4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
f37c6dfa
AP		 6 *
7 * Abhijit Pagare (abhijitpagare@ti.com)
8 * Benoit Cousson (b-cousson@ti.com)
79328706 9 * Paul Walmsley (paul@pwsan.com)
f37c6dfa
AP		 10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
6e01478a
PW		 22#include <linux/kernel.h>
23#include <linux/init.h>
f37c6dfa 24
72e06d08 25#include "powerdomain.h"
f37c6dfa
AP		 26
27#include "prcm-common.h"
a64bb9cd 28#include "prcm44xx.h"
f37c6dfa 29#include "prm-regbits-44xx.h"
d198b514
PW		 30#include "prm44xx.h"
31#include "prcm_mpu44xx.h"
f37c6dfa 32
f37c6dfa
AP		 33/* core_44xx_pwrdm: CORE power domain */
34static struct powerdomain core_44xx_pwrdm = {
35 .name = "core_pwrdm",
cdb54c44 36 .prcm_offs = OMAP4430_PRM_CORE_INST,
a64bb9cd 37 .prcm_partition = OMAP4430_PRM_PARTITION,
f37c6dfa
AP		 38 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
39 .pwrsts = PWRSTS_RET_ON,
40 .pwrsts_logic_ret = PWRSTS_OFF_RET,
41 .banks = 5,
42 .pwrsts_mem_ret = {
43 [0] = PWRDM_POWER_OFF, /* core_nret_bank */
44 [1] = PWRSTS_OFF_RET, /* core_ocmram */
45 [2] = PWRDM_POWER_RET, /* core_other_bank */
46 [3] = PWRSTS_OFF_RET, /* ducati_l2ram */
47 [4] = PWRSTS_OFF_RET, /* ducati_unicache */
48 },
49 .pwrsts_mem_on = {
50 [0] = PWRDM_POWER_ON, /* core_nret_bank */
51 [1] = PWRSTS_OFF_RET, /* core_ocmram */
52 [2] = PWRDM_POWER_ON, /* core_other_bank */
53 [3] = PWRDM_POWER_ON, /* ducati_l2ram */
54 [4] = PWRDM_POWER_ON, /* ducati_unicache */
55 },
90dbc7b0 56 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa
AP		 57};
58
59/* gfx_44xx_pwrdm: 3D accelerator power domain */
60static struct powerdomain gfx_44xx_pwrdm = {
61 .name = "gfx_pwrdm",
cdb54c44 62 .prcm_offs = OMAP4430_PRM_GFX_INST,
a64bb9cd 63 .prcm_partition = OMAP4430_PRM_PARTITION,
f37c6dfa
AP		 64 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
65 .pwrsts = PWRSTS_OFF_ON,
66 .banks = 1,
67 .pwrsts_mem_ret = {
68 [0] = PWRDM_POWER_OFF, /* gfx_mem */
69 },
70 .pwrsts_mem_on = {
71 [0] = PWRDM_POWER_ON, /* gfx_mem */
72 },
90dbc7b0 73 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa
AP		 74};
75
76/* abe_44xx_pwrdm: Audio back end power domain */
77static struct powerdomain abe_44xx_pwrdm = {
78 .name = "abe_pwrdm",
cdb54c44 79 .prcm_offs = OMAP4430_PRM_ABE_INST,
a64bb9cd 80 .prcm_partition = OMAP4430_PRM_PARTITION,
f37c6dfa
AP		 81 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
82 .pwrsts = PWRSTS_OFF_RET_ON,
83 .pwrsts_logic_ret = PWRDM_POWER_OFF,
84 .banks = 2,
85 .pwrsts_mem_ret = {
86 [0] = PWRDM_POWER_RET, /* aessmem */
87 [1] = PWRDM_POWER_OFF, /* periphmem */
88 },
89 .pwrsts_mem_on = {
90 [0] = PWRDM_POWER_ON, /* aessmem */
91 [1] = PWRDM_POWER_ON, /* periphmem */
92 },
90dbc7b0 93 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa
AP		 94};
95
96/* dss_44xx_pwrdm: Display subsystem power domain */
97static struct powerdomain dss_44xx_pwrdm = {
98 .name = "dss_pwrdm",
cdb54c44 99 .prcm_offs = OMAP4430_PRM_DSS_INST,
a64bb9cd 100 .prcm_partition = OMAP4430_PRM_PARTITION,
f37c6dfa
AP		 101 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
102 .pwrsts = PWRSTS_OFF_RET_ON,
bb722f33 103 .pwrsts_logic_ret = PWRSTS_OFF,
f37c6dfa
AP		 104 .banks = 1,
105 .pwrsts_mem_ret = {
106 [0] = PWRDM_POWER_OFF, /* dss_mem */
107 },
108 .pwrsts_mem_on = {
109 [0] = PWRDM_POWER_ON, /* dss_mem */
110 },
90dbc7b0 111 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa
AP		 112};
113
114/* tesla_44xx_pwrdm: Tesla processor power domain */
115static struct powerdomain tesla_44xx_pwrdm = {
116 .name = "tesla_pwrdm",
cdb54c44 117 .prcm_offs = OMAP4430_PRM_TESLA_INST,
a64bb9cd 118 .prcm_partition = OMAP4430_PRM_PARTITION,
f37c6dfa
AP		 119 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
120 .pwrsts = PWRSTS_OFF_RET_ON,
121 .pwrsts_logic_ret = PWRSTS_OFF_RET,
122 .banks = 3,
123 .pwrsts_mem_ret = {
124 [0] = PWRDM_POWER_RET, /* tesla_edma */
125 [1] = PWRSTS_OFF_RET, /* tesla_l1 */
126 [2] = PWRSTS_OFF_RET, /* tesla_l2 */
127 },
128 .pwrsts_mem_on = {
129 [0] = PWRDM_POWER_ON, /* tesla_edma */
130 [1] = PWRDM_POWER_ON, /* tesla_l1 */
131 [2] = PWRDM_POWER_ON, /* tesla_l2 */
132 },
90dbc7b0 133 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa
AP		 134};
135
136/* wkup_44xx_pwrdm: Wake-up power domain */
137static struct powerdomain wkup_44xx_pwrdm = {
138 .name = "wkup_pwrdm",
cdb54c44 139 .prcm_offs = OMAP4430_PRM_WKUP_INST,
a64bb9cd 140 .prcm_partition = OMAP4430_PRM_PARTITION,
f37c6dfa 141 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
d3353e16 142 .pwrsts = PWRSTS_ON,
f37c6dfa
AP		 143 .banks = 1,
144 .pwrsts_mem_ret = {
145 [0] = PWRDM_POWER_OFF, /* wkup_bank */
146 },
147 .pwrsts_mem_on = {
148 [0] = PWRDM_POWER_ON, /* wkup_bank */
149 },
150};
151
152/* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
153static struct powerdomain cpu0_44xx_pwrdm = {
154 .name = "cpu0_pwrdm",
cdb54c44 155 .prcm_offs = OMAP4430_PRCM_MPU_CPU0_INST,
a64bb9cd 156 .prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
f37c6dfa
AP		 157 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
158 .pwrsts = PWRSTS_OFF_RET_ON,
159 .pwrsts_logic_ret = PWRSTS_OFF_RET,
160 .banks = 1,
161 .pwrsts_mem_ret = {
162 [0] = PWRSTS_OFF_RET, /* cpu0_l1 */
163 },
164 .pwrsts_mem_on = {
165 [0] = PWRDM_POWER_ON, /* cpu0_l1 */
166 },
167};
168
169/* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
170static struct powerdomain cpu1_44xx_pwrdm = {
171 .name = "cpu1_pwrdm",
cdb54c44 172 .prcm_offs = OMAP4430_PRCM_MPU_CPU1_INST,
a64bb9cd 173 .prcm_partition = OMAP4430_PRCM_MPU_PARTITION,
f37c6dfa
AP		 174 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
175 .pwrsts = PWRSTS_OFF_RET_ON,
176 .pwrsts_logic_ret = PWRSTS_OFF_RET,
177 .banks = 1,
178 .pwrsts_mem_ret = {
179 [0] = PWRSTS_OFF_RET, /* cpu1_l1 */
180 },
181 .pwrsts_mem_on = {
182 [0] = PWRDM_POWER_ON, /* cpu1_l1 */
183 },
184};
185
186/* emu_44xx_pwrdm: Emulation power domain */
187static struct powerdomain emu_44xx_pwrdm = {
188 .name = "emu_pwrdm",
cdb54c44 189 .prcm_offs = OMAP4430_PRM_EMU_INST,
a64bb9cd 190 .prcm_partition = OMAP4430_PRM_PARTITION,
f37c6dfa
AP		 191 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
192 .pwrsts = PWRSTS_OFF_ON,
193 .banks = 1,
194 .pwrsts_mem_ret = {
195 [0] = PWRDM_POWER_OFF, /* emu_bank */
196 },
197 .pwrsts_mem_on = {
198 [0] = PWRDM_POWER_ON, /* emu_bank */
199 },
200};
201
202/* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */
203static struct powerdomain mpu_44xx_pwrdm = {
204 .name = "mpu_pwrdm",
cdb54c44 205 .prcm_offs = OMAP4430_PRM_MPU_INST,
a64bb9cd 206 .prcm_partition = OMAP4430_PRM_PARTITION,
f37c6dfa
AP		 207 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
208 .pwrsts = PWRSTS_OFF_RET_ON,
209 .pwrsts_logic_ret = PWRSTS_OFF_RET,
210 .banks = 3,
211 .pwrsts_mem_ret = {
212 [0] = PWRSTS_OFF_RET, /* mpu_l1 */
213 [1] = PWRSTS_OFF_RET, /* mpu_l2 */
214 [2] = PWRDM_POWER_RET, /* mpu_ram */
215 },
216 .pwrsts_mem_on = {
217 [0] = PWRDM_POWER_ON, /* mpu_l1 */
218 [1] = PWRDM_POWER_ON, /* mpu_l2 */
219 [2] = PWRDM_POWER_ON, /* mpu_ram */
220 },
221};
222
223/* ivahd_44xx_pwrdm: IVA-HD power domain */
224static struct powerdomain ivahd_44xx_pwrdm = {
225 .name = "ivahd_pwrdm",
cdb54c44 226 .prcm_offs = OMAP4430_PRM_IVAHD_INST,
a64bb9cd 227 .prcm_partition = OMAP4430_PRM_PARTITION,
f37c6dfa
AP		 228 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
229 .pwrsts = PWRSTS_OFF_RET_ON,
230 .pwrsts_logic_ret = PWRDM_POWER_OFF,
231 .banks = 4,
232 .pwrsts_mem_ret = {
233 [0] = PWRDM_POWER_OFF, /* hwa_mem */
234 [1] = PWRSTS_OFF_RET, /* sl2_mem */
235 [2] = PWRSTS_OFF_RET, /* tcm1_mem */
236 [3] = PWRSTS_OFF_RET, /* tcm2_mem */
237 },
238 .pwrsts_mem_on = {
239 [0] = PWRDM_POWER_ON, /* hwa_mem */
240 [1] = PWRDM_POWER_ON, /* sl2_mem */
241 [2] = PWRDM_POWER_ON, /* tcm1_mem */
242 [3] = PWRDM_POWER_ON, /* tcm2_mem */
243 },
90dbc7b0 244 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa
AP		 245};
246
247/* cam_44xx_pwrdm: Camera subsystem power domain */
248static struct powerdomain cam_44xx_pwrdm = {
249 .name = "cam_pwrdm",
cdb54c44 250 .prcm_offs = OMAP4430_PRM_CAM_INST,
a64bb9cd 251 .prcm_partition = OMAP4430_PRM_PARTITION,
f37c6dfa
AP		 252 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
253 .pwrsts = PWRSTS_OFF_ON,
254 .banks = 1,
255 .pwrsts_mem_ret = {
256 [0] = PWRDM_POWER_OFF, /* cam_mem */
257 },
258 .pwrsts_mem_on = {
259 [0] = PWRDM_POWER_ON, /* cam_mem */
260 },
90dbc7b0 261 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa
AP		 262};
263
264/* l3init_44xx_pwrdm: L3 initators pheripherals power domain */
265static struct powerdomain l3init_44xx_pwrdm = {
266 .name = "l3init_pwrdm",
cdb54c44 267 .prcm_offs = OMAP4430_PRM_L3INIT_INST,
a64bb9cd 268 .prcm_partition = OMAP4430_PRM_PARTITION,
f37c6dfa 269 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
80f09365 270 .pwrsts = PWRSTS_RET_ON,
f37c6dfa
AP		 271 .pwrsts_logic_ret = PWRSTS_OFF_RET,
272 .banks = 1,
273 .pwrsts_mem_ret = {
274 [0] = PWRDM_POWER_OFF, /* l3init_bank1 */
275 },
276 .pwrsts_mem_on = {
277 [0] = PWRDM_POWER_ON, /* l3init_bank1 */
278 },
90dbc7b0 279 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa
AP		 280};
281
282/* l4per_44xx_pwrdm: Target peripherals power domain */
283static struct powerdomain l4per_44xx_pwrdm = {
284 .name = "l4per_pwrdm",
cdb54c44 285 .prcm_offs = OMAP4430_PRM_L4PER_INST,
a64bb9cd 286 .prcm_partition = OMAP4430_PRM_PARTITION,
f37c6dfa 287 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
474e7aeb 288 .pwrsts = PWRSTS_RET_ON,
f37c6dfa
AP		 289 .pwrsts_logic_ret = PWRSTS_OFF_RET,
290 .banks = 2,
291 .pwrsts_mem_ret = {
292 [0] = PWRDM_POWER_OFF, /* nonretained_bank */
293 [1] = PWRDM_POWER_RET, /* retained_bank */
294 },
295 .pwrsts_mem_on = {
296 [0] = PWRDM_POWER_ON, /* nonretained_bank */
297 [1] = PWRDM_POWER_ON, /* retained_bank */
298 },
90dbc7b0 299 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa
AP		 300};
301
302/*
303 * always_on_core_44xx_pwrdm: Always ON logic that sits in VDD_CORE voltage
304 * domain
305 */
306static struct powerdomain always_on_core_44xx_pwrdm = {
307 .name = "always_on_core_pwrdm",
cdb54c44 308 .prcm_offs = OMAP4430_PRM_ALWAYS_ON_INST,
a64bb9cd 309 .prcm_partition = OMAP4430_PRM_PARTITION,
f37c6dfa 310 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
d3353e16 311 .pwrsts = PWRSTS_ON,
f37c6dfa
AP		 312};
313
314/* cefuse_44xx_pwrdm: Customer efuse controller power domain */
315static struct powerdomain cefuse_44xx_pwrdm = {
316 .name = "cefuse_pwrdm",
cdb54c44 317 .prcm_offs = OMAP4430_PRM_CEFUSE_INST,
a64bb9cd 318 .prcm_partition = OMAP4430_PRM_PARTITION,
f37c6dfa
AP		 319 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
320 .pwrsts = PWRSTS_OFF_ON,
321};
322
323/*
324 * The following power domains are not under SW control
325 *
326 * always_on_iva
327 * always_on_mpu
328 * stdefuse
329 */
330
6e01478a
PW		 331/* As powerdomains are added or removed above, this list must also be changed */
332static struct powerdomain *powerdomains_omap44xx[] __initdata = {
333 &core_44xx_pwrdm,
334 &gfx_44xx_pwrdm,
335 &abe_44xx_pwrdm,
336 &dss_44xx_pwrdm,
337 &tesla_44xx_pwrdm,
338 &wkup_44xx_pwrdm,
339 &cpu0_44xx_pwrdm,
340 &cpu1_44xx_pwrdm,
341 &emu_44xx_pwrdm,
342 &mpu_44xx_pwrdm,
343 &ivahd_44xx_pwrdm,
344 &cam_44xx_pwrdm,
345 &l3init_44xx_pwrdm,
346 &l4per_44xx_pwrdm,
347 &always_on_core_44xx_pwrdm,
348 &cefuse_44xx_pwrdm,
349 NULL
350};
f37c6dfa 351
6e01478a
PW		 352void __init omap44xx_powerdomains_init(void)
353{
354 pwrdm_init(powerdomains_omap44xx, &omap4_pwrdm_operations);
355}
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