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OMAP4: PRCM: Add SCRM header file
[deliverable/linux.git] / arch / arm / mach-omap2 / powerdomains44xx_data.c
CommitLineData
f37c6dfa
AP		 1/*
2 * OMAP4 Power domains framework
3 *
79328706
BC		 4 * Copyright (C) 2009-2010 Texas Instruments, Inc.
5 * Copyright (C) 2009-2010 Nokia Corporation
f37c6dfa
AP		 6 *
7 * Abhijit Pagare (abhijitpagare@ti.com)
8 * Benoit Cousson (b-cousson@ti.com)
79328706 9 * Paul Walmsley (paul@pwsan.com)
f37c6dfa
AP		 10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
6e01478a
PW		 22#include <linux/kernel.h>
23#include <linux/init.h>
f37c6dfa
AP		 24
25#include <plat/powerdomain.h>
6e01478a 26#include "powerdomains.h"
f37c6dfa
AP		 27
28#include "prcm-common.h"
f37c6dfa
AP		 29#include "prm.h"
30#include "prm-regbits-44xx.h"
d198b514
PW		 31#include "prm44xx.h"
32#include "prcm_mpu44xx.h"
f37c6dfa 33
f37c6dfa
AP		 34/* core_44xx_pwrdm: CORE power domain */
35static struct powerdomain core_44xx_pwrdm = {
36 .name = "core_pwrdm",
37 .prcm_offs = OMAP4430_PRM_CORE_MOD,
38 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
39 .pwrsts = PWRSTS_RET_ON,
40 .pwrsts_logic_ret = PWRSTS_OFF_RET,
41 .banks = 5,
42 .pwrsts_mem_ret = {
43 [0] = PWRDM_POWER_OFF, /* core_nret_bank */
44 [1] = PWRSTS_OFF_RET, /* core_ocmram */
45 [2] = PWRDM_POWER_RET, /* core_other_bank */
46 [3] = PWRSTS_OFF_RET, /* ducati_l2ram */
47 [4] = PWRSTS_OFF_RET, /* ducati_unicache */
48 },
49 .pwrsts_mem_on = {
50 [0] = PWRDM_POWER_ON, /* core_nret_bank */
51 [1] = PWRSTS_OFF_RET, /* core_ocmram */
52 [2] = PWRDM_POWER_ON, /* core_other_bank */
53 [3] = PWRDM_POWER_ON, /* ducati_l2ram */
54 [4] = PWRDM_POWER_ON, /* ducati_unicache */
55 },
90dbc7b0 56 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa
AP		 57};
58
59/* gfx_44xx_pwrdm: 3D accelerator power domain */
60static struct powerdomain gfx_44xx_pwrdm = {
61 .name = "gfx_pwrdm",
62 .prcm_offs = OMAP4430_PRM_GFX_MOD,
63 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
64 .pwrsts = PWRSTS_OFF_ON,
65 .banks = 1,
66 .pwrsts_mem_ret = {
67 [0] = PWRDM_POWER_OFF, /* gfx_mem */
68 },
69 .pwrsts_mem_on = {
70 [0] = PWRDM_POWER_ON, /* gfx_mem */
71 },
90dbc7b0 72 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa
AP		 73};
74
75/* abe_44xx_pwrdm: Audio back end power domain */
76static struct powerdomain abe_44xx_pwrdm = {
77 .name = "abe_pwrdm",
78 .prcm_offs = OMAP4430_PRM_ABE_MOD,
79 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
80 .pwrsts = PWRSTS_OFF_RET_ON,
81 .pwrsts_logic_ret = PWRDM_POWER_OFF,
82 .banks = 2,
83 .pwrsts_mem_ret = {
84 [0] = PWRDM_POWER_RET, /* aessmem */
85 [1] = PWRDM_POWER_OFF, /* periphmem */
86 },
87 .pwrsts_mem_on = {
88 [0] = PWRDM_POWER_ON, /* aessmem */
89 [1] = PWRDM_POWER_ON, /* periphmem */
90 },
90dbc7b0 91 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa
AP		 92};
93
94/* dss_44xx_pwrdm: Display subsystem power domain */
95static struct powerdomain dss_44xx_pwrdm = {
96 .name = "dss_pwrdm",
97 .prcm_offs = OMAP4430_PRM_DSS_MOD,
98 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
99 .pwrsts = PWRSTS_OFF_RET_ON,
bb722f33 100 .pwrsts_logic_ret = PWRSTS_OFF,
f37c6dfa
AP		 101 .banks = 1,
102 .pwrsts_mem_ret = {
103 [0] = PWRDM_POWER_OFF, /* dss_mem */
104 },
105 .pwrsts_mem_on = {
106 [0] = PWRDM_POWER_ON, /* dss_mem */
107 },
90dbc7b0 108 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa
AP		 109};
110
111/* tesla_44xx_pwrdm: Tesla processor power domain */
112static struct powerdomain tesla_44xx_pwrdm = {
113 .name = "tesla_pwrdm",
114 .prcm_offs = OMAP4430_PRM_TESLA_MOD,
115 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
116 .pwrsts = PWRSTS_OFF_RET_ON,
117 .pwrsts_logic_ret = PWRSTS_OFF_RET,
118 .banks = 3,
119 .pwrsts_mem_ret = {
120 [0] = PWRDM_POWER_RET, /* tesla_edma */
121 [1] = PWRSTS_OFF_RET, /* tesla_l1 */
122 [2] = PWRSTS_OFF_RET, /* tesla_l2 */
123 },
124 .pwrsts_mem_on = {
125 [0] = PWRDM_POWER_ON, /* tesla_edma */
126 [1] = PWRDM_POWER_ON, /* tesla_l1 */
127 [2] = PWRDM_POWER_ON, /* tesla_l2 */
128 },
90dbc7b0 129 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa
AP		 130};
131
132/* wkup_44xx_pwrdm: Wake-up power domain */
133static struct powerdomain wkup_44xx_pwrdm = {
134 .name = "wkup_pwrdm",
135 .prcm_offs = OMAP4430_PRM_WKUP_MOD,
136 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
d3353e16 137 .pwrsts = PWRSTS_ON,
f37c6dfa
AP		 138 .banks = 1,
139 .pwrsts_mem_ret = {
140 [0] = PWRDM_POWER_OFF, /* wkup_bank */
141 },
142 .pwrsts_mem_on = {
143 [0] = PWRDM_POWER_ON, /* wkup_bank */
144 },
145};
146
147/* cpu0_44xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
148static struct powerdomain cpu0_44xx_pwrdm = {
149 .name = "cpu0_pwrdm",
79328706 150 .prcm_offs = OMAP4430_PRCM_MPU_CPU0_MOD,
f37c6dfa
AP		 151 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
152 .pwrsts = PWRSTS_OFF_RET_ON,
153 .pwrsts_logic_ret = PWRSTS_OFF_RET,
154 .banks = 1,
155 .pwrsts_mem_ret = {
156 [0] = PWRSTS_OFF_RET, /* cpu0_l1 */
157 },
158 .pwrsts_mem_on = {
159 [0] = PWRDM_POWER_ON, /* cpu0_l1 */
160 },
161};
162
163/* cpu1_44xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
164static struct powerdomain cpu1_44xx_pwrdm = {
165 .name = "cpu1_pwrdm",
79328706 166 .prcm_offs = OMAP4430_PRCM_MPU_CPU1_MOD,
f37c6dfa
AP		 167 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
168 .pwrsts = PWRSTS_OFF_RET_ON,
169 .pwrsts_logic_ret = PWRSTS_OFF_RET,
170 .banks = 1,
171 .pwrsts_mem_ret = {
172 [0] = PWRSTS_OFF_RET, /* cpu1_l1 */
173 },
174 .pwrsts_mem_on = {
175 [0] = PWRDM_POWER_ON, /* cpu1_l1 */
176 },
177};
178
179/* emu_44xx_pwrdm: Emulation power domain */
180static struct powerdomain emu_44xx_pwrdm = {
181 .name = "emu_pwrdm",
182 .prcm_offs = OMAP4430_PRM_EMU_MOD,
183 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
184 .pwrsts = PWRSTS_OFF_ON,
185 .banks = 1,
186 .pwrsts_mem_ret = {
187 [0] = PWRDM_POWER_OFF, /* emu_bank */
188 },
189 .pwrsts_mem_on = {
190 [0] = PWRDM_POWER_ON, /* emu_bank */
191 },
192};
193
194/* mpu_44xx_pwrdm: Modena processor and the Neon coprocessor power domain */
195static struct powerdomain mpu_44xx_pwrdm = {
196 .name = "mpu_pwrdm",
197 .prcm_offs = OMAP4430_PRM_MPU_MOD,
198 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
199 .pwrsts = PWRSTS_OFF_RET_ON,
200 .pwrsts_logic_ret = PWRSTS_OFF_RET,
201 .banks = 3,
202 .pwrsts_mem_ret = {
203 [0] = PWRSTS_OFF_RET, /* mpu_l1 */
204 [1] = PWRSTS_OFF_RET, /* mpu_l2 */
205 [2] = PWRDM_POWER_RET, /* mpu_ram */
206 },
207 .pwrsts_mem_on = {
208 [0] = PWRDM_POWER_ON, /* mpu_l1 */
209 [1] = PWRDM_POWER_ON, /* mpu_l2 */
210 [2] = PWRDM_POWER_ON, /* mpu_ram */
211 },
212};
213
214/* ivahd_44xx_pwrdm: IVA-HD power domain */
215static struct powerdomain ivahd_44xx_pwrdm = {
216 .name = "ivahd_pwrdm",
217 .prcm_offs = OMAP4430_PRM_IVAHD_MOD,
218 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
219 .pwrsts = PWRSTS_OFF_RET_ON,
220 .pwrsts_logic_ret = PWRDM_POWER_OFF,
221 .banks = 4,
222 .pwrsts_mem_ret = {
223 [0] = PWRDM_POWER_OFF, /* hwa_mem */
224 [1] = PWRSTS_OFF_RET, /* sl2_mem */
225 [2] = PWRSTS_OFF_RET, /* tcm1_mem */
226 [3] = PWRSTS_OFF_RET, /* tcm2_mem */
227 },
228 .pwrsts_mem_on = {
229 [0] = PWRDM_POWER_ON, /* hwa_mem */
230 [1] = PWRDM_POWER_ON, /* sl2_mem */
231 [2] = PWRDM_POWER_ON, /* tcm1_mem */
232 [3] = PWRDM_POWER_ON, /* tcm2_mem */
233 },
90dbc7b0 234 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa
AP		 235};
236
237/* cam_44xx_pwrdm: Camera subsystem power domain */
238static struct powerdomain cam_44xx_pwrdm = {
239 .name = "cam_pwrdm",
240 .prcm_offs = OMAP4430_PRM_CAM_MOD,
241 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
242 .pwrsts = PWRSTS_OFF_ON,
243 .banks = 1,
244 .pwrsts_mem_ret = {
245 [0] = PWRDM_POWER_OFF, /* cam_mem */
246 },
247 .pwrsts_mem_on = {
248 [0] = PWRDM_POWER_ON, /* cam_mem */
249 },
90dbc7b0 250 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa
AP		 251};
252
253/* l3init_44xx_pwrdm: L3 initators pheripherals power domain */
254static struct powerdomain l3init_44xx_pwrdm = {
255 .name = "l3init_pwrdm",
256 .prcm_offs = OMAP4430_PRM_L3INIT_MOD,
257 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
258 .pwrsts = PWRSTS_OFF_RET_ON,
259 .pwrsts_logic_ret = PWRSTS_OFF_RET,
260 .banks = 1,
261 .pwrsts_mem_ret = {
262 [0] = PWRDM_POWER_OFF, /* l3init_bank1 */
263 },
264 .pwrsts_mem_on = {
265 [0] = PWRDM_POWER_ON, /* l3init_bank1 */
266 },
90dbc7b0 267 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa
AP		 268};
269
270/* l4per_44xx_pwrdm: Target peripherals power domain */
271static struct powerdomain l4per_44xx_pwrdm = {
272 .name = "l4per_pwrdm",
273 .prcm_offs = OMAP4430_PRM_L4PER_MOD,
274 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
275 .pwrsts = PWRSTS_OFF_RET_ON,
276 .pwrsts_logic_ret = PWRSTS_OFF_RET,
277 .banks = 2,
278 .pwrsts_mem_ret = {
279 [0] = PWRDM_POWER_OFF, /* nonretained_bank */
280 [1] = PWRDM_POWER_RET, /* retained_bank */
281 },
282 .pwrsts_mem_on = {
283 [0] = PWRDM_POWER_ON, /* nonretained_bank */
284 [1] = PWRDM_POWER_ON, /* retained_bank */
285 },
90dbc7b0 286 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
f37c6dfa
AP		 287};
288
289/*
290 * always_on_core_44xx_pwrdm: Always ON logic that sits in VDD_CORE voltage
291 * domain
292 */
293static struct powerdomain always_on_core_44xx_pwrdm = {
294 .name = "always_on_core_pwrdm",
295 .prcm_offs = OMAP4430_PRM_ALWAYS_ON_MOD,
296 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
d3353e16 297 .pwrsts = PWRSTS_ON,
f37c6dfa
AP		 298};
299
300/* cefuse_44xx_pwrdm: Customer efuse controller power domain */
301static struct powerdomain cefuse_44xx_pwrdm = {
302 .name = "cefuse_pwrdm",
303 .prcm_offs = OMAP4430_PRM_CEFUSE_MOD,
304 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
305 .pwrsts = PWRSTS_OFF_ON,
306};
307
308/*
309 * The following power domains are not under SW control
310 *
311 * always_on_iva
312 * always_on_mpu
313 * stdefuse
314 */
315
6e01478a
PW		 316/* As powerdomains are added or removed above, this list must also be changed */
317static struct powerdomain *powerdomains_omap44xx[] __initdata = {
318 &core_44xx_pwrdm,
319 &gfx_44xx_pwrdm,
320 &abe_44xx_pwrdm,
321 &dss_44xx_pwrdm,
322 &tesla_44xx_pwrdm,
323 &wkup_44xx_pwrdm,
324 &cpu0_44xx_pwrdm,
325 &cpu1_44xx_pwrdm,
326 &emu_44xx_pwrdm,
327 &mpu_44xx_pwrdm,
328 &ivahd_44xx_pwrdm,
329 &cam_44xx_pwrdm,
330 &l3init_44xx_pwrdm,
331 &l4per_44xx_pwrdm,
332 &always_on_core_44xx_pwrdm,
333 &cefuse_44xx_pwrdm,
334 NULL
335};
f37c6dfa 336
6e01478a
PW		 337void __init omap44xx_powerdomains_init(void)
338{
339 pwrdm_init(powerdomains_omap44xx, &omap4_pwrdm_operations);
340}
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