[deliverable/linux.git] / arch / arm / mach-omap2 / powerdomains7xx_data.c

/*
 * DRA7xx Power domains framework
 *
 * Copyright (C) 2009-2013 Texas Instruments, Inc.
 * Copyright (C) 2009-2011 Nokia Corporation
 *
 * Generated by code originally written by:
 * Abhijit Pagare (abhijitpagare@ti.com)
 * Benoit Cousson (b-cousson@ti.com)
 * Paul Walmsley (paul@pwsan.com)
 *
 * This file is automatically generated from the OMAP hardware databases.
 * We respectfully ask that any modifications to this file be coordinated
 * with the public linux-omap@vger.kernel.org mailing list and the
 * authors above to ensure that the autogeneration scripts are kept
 * up-to-date with the file contents.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/init.h>

#include "powerdomain.h"

#include "prcm-common.h"
#include "prcm44xx.h"
#include "prm7xx.h"
#include "prcm_mpu7xx.h"

/* iva_7xx_pwrdm: IVA-HD power domain */
static struct powerdomain iva_7xx_pwrdm = {
	.name		  = "iva_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_IVA_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 4,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* hwa_mem */
		[1] = PWRSTS_ON,	/* sl2_mem */
		[2] = PWRSTS_ON,	/* tcm1_mem */
		[3] = PWRSTS_ON,	/* tcm2_mem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* rtc_7xx_pwrdm:  */
static struct powerdomain rtc_7xx_pwrdm = {
	.name		  = "rtc_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_RTC_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
};

/* custefuse_7xx_pwrdm: Customer efuse controller power domain */
static struct powerdomain custefuse_7xx_pwrdm = {
	.name		  = "custefuse_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_CUSTEFUSE_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* ipu_7xx_pwrdm: Audio back end power domain */
static struct powerdomain ipu_7xx_pwrdm = {
	.name		  = "ipu_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_IPU_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 2,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* aessmem */
		[1] = PWRSTS_ON,	/* periphmem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* dss_7xx_pwrdm: Display subsystem power domain */
static struct powerdomain dss_7xx_pwrdm = {
	.name		  = "dss_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_DSS_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* dss_mem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* l4per_7xx_pwrdm: Target peripherals power domain */
static struct powerdomain l4per_7xx_pwrdm = {
	.name		  = "l4per_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_L4PER_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
	.banks		  = 2,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* nonretained_bank */
		[1] = PWRSTS_ON,	/* retained_bank */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* gpu_7xx_pwrdm: 3D accelerator power domain */
static struct powerdomain gpu_7xx_pwrdm = {
	.name		  = "gpu_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_GPU_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* gpu_mem */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* wkupaon_7xx_pwrdm: Wake-up power domain */
static struct powerdomain wkupaon_7xx_pwrdm = {
	.name		  = "wkupaon_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_WKUPAON_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* wkup_bank */
	},
};

/* core_7xx_pwrdm: CORE power domain */
static struct powerdomain core_7xx_pwrdm = {
	.name		  = "core_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_CORE_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
	.banks		  = 5,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* core_nret_bank */
		[1] = PWRSTS_ON,	/* core_ocmram */
		[2] = PWRSTS_ON,	/* core_other_bank */
		[3] = PWRSTS_ON,	/* ipu_l2ram */
		[4] = PWRSTS_ON,	/* ipu_unicache */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
static struct powerdomain coreaon_7xx_pwrdm = {
	.name		  = "coreaon_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_COREAON_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
};

/* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
static struct powerdomain cpu0_7xx_pwrdm = {
	.name		  = "cpu0_pwrdm",
	.prcm_offs	  = DRA7XX_MPU_PRCM_PRM_C0_INST,
	.prcm_partition	  = DRA7XX_MPU_PRCM_PARTITION,
	.pwrsts		  = PWRSTS_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* cpu0_l1 */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* cpu0_l1 */
	},
};

/* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
static struct powerdomain cpu1_7xx_pwrdm = {
	.name		  = "cpu1_pwrdm",
	.prcm_offs	  = DRA7XX_MPU_PRCM_PRM_C1_INST,
	.prcm_partition	  = DRA7XX_MPU_PRCM_PARTITION,
	.pwrsts		  = PWRSTS_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 1,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* cpu1_l1 */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* cpu1_l1 */
	},
};

/* vpe_7xx_pwrdm:  */
static struct powerdomain vpe_7xx_pwrdm = {
	.name		  = "vpe_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_VPE_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* vpe_bank */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */
static struct powerdomain mpu_7xx_pwrdm = {
	.name		  = "mpu_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_MPU_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_RET_ON,
	.pwrsts_logic_ret = PWRSTS_RET,
	.banks		  = 2,
	.pwrsts_mem_ret	= {
		[0] = PWRSTS_OFF_RET,	/* mpu_l2 */
		[1] = PWRSTS_RET,	/* mpu_ram */
	},
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* mpu_l2 */
		[1] = PWRSTS_ON,	/* mpu_ram */
	},
};

/* l3init_7xx_pwrdm: L3 initators pheripherals power domain  */
static struct powerdomain l3init_7xx_pwrdm = {
	.name		  = "l3init_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_L3INIT_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_ON,
	.banks		  = 3,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* gmac_bank */
		[1] = PWRSTS_ON,	/* l3init_bank1 */
		[2] = PWRSTS_ON,	/* l3init_bank2 */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* eve3_7xx_pwrdm:  */
static struct powerdomain eve3_7xx_pwrdm = {
	.name		  = "eve3_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_EVE3_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* eve3_bank */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* emu_7xx_pwrdm: Emulation power domain */
static struct powerdomain emu_7xx_pwrdm = {
	.name		  = "emu_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_EMU_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* emu_bank */
	},
};

/* dsp2_7xx_pwrdm:  */
static struct powerdomain dsp2_7xx_pwrdm = {
	.name		  = "dsp2_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_DSP2_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 3,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* dsp2_edma */
		[1] = PWRSTS_ON,	/* dsp2_l1 */
		[2] = PWRSTS_ON,	/* dsp2_l2 */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* dsp1_7xx_pwrdm: Tesla processor power domain */
static struct powerdomain dsp1_7xx_pwrdm = {
	.name		  = "dsp1_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_DSP1_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 3,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* dsp1_edma */
		[1] = PWRSTS_ON,	/* dsp1_l1 */
		[2] = PWRSTS_ON,	/* dsp1_l2 */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* cam_7xx_pwrdm: Camera subsystem power domain */
static struct powerdomain cam_7xx_pwrdm = {
	.name		  = "cam_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_CAM_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* vip_bank */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* eve4_7xx_pwrdm:  */
static struct powerdomain eve4_7xx_pwrdm = {
	.name		  = "eve4_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_EVE4_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* eve4_bank */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* eve2_7xx_pwrdm:  */
static struct powerdomain eve2_7xx_pwrdm = {
	.name		  = "eve2_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_EVE2_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* eve2_bank */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/* eve1_7xx_pwrdm:  */
static struct powerdomain eve1_7xx_pwrdm = {
	.name		  = "eve1_pwrdm",
	.prcm_offs	  = DRA7XX_PRM_EVE1_INST,
	.prcm_partition	  = DRA7XX_PRM_PARTITION,
	.pwrsts		  = PWRSTS_OFF_ON,
	.banks		  = 1,
	.pwrsts_mem_on	= {
		[0] = PWRSTS_ON,	/* eve1_bank */
	},
	.flags		  = PWRDM_HAS_LOWPOWERSTATECHANGE,
};

/*
 * The following power domains are not under SW control
 *
 * mpuaon
 * mmaon
 */

/* As powerdomains are added or removed above, this list must also be changed */
static struct powerdomain *powerdomains_dra7xx[] __initdata = {
	&iva_7xx_pwrdm,
	&rtc_7xx_pwrdm,
	&custefuse_7xx_pwrdm,
	&ipu_7xx_pwrdm,
	&dss_7xx_pwrdm,
	&l4per_7xx_pwrdm,
	&gpu_7xx_pwrdm,
	&wkupaon_7xx_pwrdm,
	&core_7xx_pwrdm,
	&coreaon_7xx_pwrdm,
	&cpu0_7xx_pwrdm,
	&cpu1_7xx_pwrdm,
	&vpe_7xx_pwrdm,
	&mpu_7xx_pwrdm,
	&l3init_7xx_pwrdm,
	&eve3_7xx_pwrdm,
	&emu_7xx_pwrdm,
	&dsp2_7xx_pwrdm,
	&dsp1_7xx_pwrdm,
	&cam_7xx_pwrdm,
	&eve4_7xx_pwrdm,
	&eve2_7xx_pwrdm,
	&eve1_7xx_pwrdm,
	NULL
};

void __init dra7xx_powerdomains_init(void)
{
	pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
	pwrdm_register_pwrdms(powerdomains_dra7xx);
	pwrdm_complete_init();
}
Commit	Line	Data
97dd16b1 A	1	/*
	2	* DRA7xx Power domains framework
	3	*
	4	* Copyright (C) 2009-2013 Texas Instruments, Inc.
	5	* Copyright (C) 2009-2011 Nokia Corporation
	6	*
	7	* Generated by code originally written by:
	8	* Abhijit Pagare (abhijitpagare@ti.com)
	9	* Benoit Cousson (b-cousson@ti.com)
	10	* Paul Walmsley (paul@pwsan.com)
	11	*
	12	* This file is automatically generated from the OMAP hardware databases.
	13	* We respectfully ask that any modifications to this file be coordinated
	14	* with the public linux-omap@vger.kernel.org mailing list and the
	15	* authors above to ensure that the autogeneration scripts are kept
	16	* up-to-date with the file contents.
	17	*
	18	* This program is free software; you can redistribute it and/or modify
	19	* it under the terms of the GNU General Public License version 2 as
	20	* published by the Free Software Foundation.
	21	*/
	22
	23	#include <linux/kernel.h>
	24	#include <linux/init.h>
	25
	26	#include "powerdomain.h"
	27
	28	#include "prcm-common.h"
	29	#include "prcm44xx.h"
	30	#include "prm7xx.h"
	31	#include "prcm_mpu7xx.h"
	32
	33	/* iva_7xx_pwrdm: IVA-HD power domain */
	34	static struct powerdomain iva_7xx_pwrdm = {
	35	.name = "iva_pwrdm",
	36	.prcm_offs = DRA7XX_PRM_IVA_INST,
	37	.prcm_partition = DRA7XX_PRM_PARTITION,
dac4fba2	38	.pwrsts = PWRSTS_OFF_ON,
97dd16b1	39	.banks = 4,
97dd16b1	40	.pwrsts_mem_on = {
41feb8ef NM	41	[0] = PWRSTS_ON, /* hwa_mem */
	42	[1] = PWRSTS_ON, /* sl2_mem */
	43	[2] = PWRSTS_ON, /* tcm1_mem */
	44	[3] = PWRSTS_ON, /* tcm2_mem */
97dd16b1 A	45	},
	46	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	47	};
	48
	49	/* rtc_7xx_pwrdm: */
	50	static struct powerdomain rtc_7xx_pwrdm = {
	51	.name = "rtc_pwrdm",
	52	.prcm_offs = DRA7XX_PRM_RTC_INST,
	53	.prcm_partition = DRA7XX_PRM_PARTITION,
	54	.pwrsts = PWRSTS_ON,
	55	};
	56
	57	/* custefuse_7xx_pwrdm: Customer efuse controller power domain */
	58	static struct powerdomain custefuse_7xx_pwrdm = {
	59	.name = "custefuse_pwrdm",
	60	.prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST,
	61	.prcm_partition = DRA7XX_PRM_PARTITION,
	62	.pwrsts = PWRSTS_OFF_ON,
	63	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	64	};
	65
	66	/* ipu_7xx_pwrdm: Audio back end power domain */
	67	static struct powerdomain ipu_7xx_pwrdm = {
	68	.name = "ipu_pwrdm",
	69	.prcm_offs = DRA7XX_PRM_IPU_INST,
	70	.prcm_partition = DRA7XX_PRM_PARTITION,
dac4fba2	71	.pwrsts = PWRSTS_OFF_ON,
97dd16b1	72	.banks = 2,
97dd16b1	73	.pwrsts_mem_on = {
41feb8ef NM	74	[0] = PWRSTS_ON, /* aessmem */
41feb8ef NM	75	[1] = PWRSTS_ON, /* periphmem */
97dd16b1 A	76	},
	77	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	78	};
	79
	80	/* dss_7xx_pwrdm: Display subsystem power domain */
	81	static struct powerdomain dss_7xx_pwrdm = {
	82	.name = "dss_pwrdm",
	83	.prcm_offs = DRA7XX_PRM_DSS_INST,
	84	.prcm_partition = DRA7XX_PRM_PARTITION,
dac4fba2	85	.pwrsts = PWRSTS_OFF_ON,
97dd16b1	86	.banks = 1,
97dd16b1	87	.pwrsts_mem_on = {
41feb8ef	88	[0] = PWRSTS_ON, /* dss_mem */
97dd16b1 A	89	},
	90	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	91	};
	92
	93	/* l4per_7xx_pwrdm: Target peripherals power domain */
	94	static struct powerdomain l4per_7xx_pwrdm = {
	95	.name = "l4per_pwrdm",
	96	.prcm_offs = DRA7XX_PRM_L4PER_INST,
	97	.prcm_partition = DRA7XX_PRM_PARTITION,
d16c0d72	98	.pwrsts = PWRSTS_ON,
97dd16b1	99	.banks = 2,
97dd16b1	100	.pwrsts_mem_on = {
41feb8ef NM	101	[0] = PWRSTS_ON, /* nonretained_bank */
41feb8ef NM	102	[1] = PWRSTS_ON, /* retained_bank */
97dd16b1 A	103	},
	104	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	105	};
	106
	107	/* gpu_7xx_pwrdm: 3D accelerator power domain */
	108	static struct powerdomain gpu_7xx_pwrdm = {
	109	.name = "gpu_pwrdm",
	110	.prcm_offs = DRA7XX_PRM_GPU_INST,
	111	.prcm_partition = DRA7XX_PRM_PARTITION,
	112	.pwrsts = PWRSTS_OFF_ON,
	113	.banks = 1,
97dd16b1	114	.pwrsts_mem_on = {
41feb8ef	115	[0] = PWRSTS_ON, /* gpu_mem */
97dd16b1 A	116	},
	117	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	118	};
	119
	120	/* wkupaon_7xx_pwrdm: Wake-up power domain */
	121	static struct powerdomain wkupaon_7xx_pwrdm = {
	122	.name = "wkupaon_pwrdm",
	123	.prcm_offs = DRA7XX_PRM_WKUPAON_INST,
	124	.prcm_partition = DRA7XX_PRM_PARTITION,
	125	.pwrsts = PWRSTS_ON,
	126	.banks = 1,
97dd16b1 A	127	.pwrsts_mem_on = {
	128	[0] = PWRSTS_ON, /* wkup_bank */
	129	},
	130	};
	131
	132	/* core_7xx_pwrdm: CORE power domain */
	133	static struct powerdomain core_7xx_pwrdm = {
	134	.name = "core_pwrdm",
	135	.prcm_offs = DRA7XX_PRM_CORE_INST,
	136	.prcm_partition = DRA7XX_PRM_PARTITION,
f971512c	137	.pwrsts = PWRSTS_ON,
97dd16b1	138	.banks = 5,
97dd16b1	139	.pwrsts_mem_on = {
41feb8ef NM	140	[0] = PWRSTS_ON, /* core_nret_bank */
	141	[1] = PWRSTS_ON, /* core_ocmram */
	142	[2] = PWRSTS_ON, /* core_other_bank */
	143	[3] = PWRSTS_ON, /* ipu_l2ram */
	144	[4] = PWRSTS_ON, /* ipu_unicache */
97dd16b1 A	145	},
	146	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	147	};
	148
	149	/* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
	150	static struct powerdomain coreaon_7xx_pwrdm = {
	151	.name = "coreaon_pwrdm",
	152	.prcm_offs = DRA7XX_PRM_COREAON_INST,
	153	.prcm_partition = DRA7XX_PRM_PARTITION,
	154	.pwrsts = PWRSTS_ON,
	155	};
	156
	157	/* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
	158	static struct powerdomain cpu0_7xx_pwrdm = {
	159	.name = "cpu0_pwrdm",
	160	.prcm_offs = DRA7XX_MPU_PRCM_PRM_C0_INST,
	161	.prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
cafc8cb5 NM	162	.pwrsts = PWRSTS_RET_ON,
cafc8cb5 NM	163	.pwrsts_logic_ret = PWRSTS_RET,
97dd16b1 A	164	.banks = 1,
	165	.pwrsts_mem_ret = {
	166	[0] = PWRSTS_OFF_RET, /* cpu0_l1 */
	167	},
	168	.pwrsts_mem_on = {
	169	[0] = PWRSTS_ON, /* cpu0_l1 */
	170	},
	171	};
	172
	173	/* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
	174	static struct powerdomain cpu1_7xx_pwrdm = {
	175	.name = "cpu1_pwrdm",
	176	.prcm_offs = DRA7XX_MPU_PRCM_PRM_C1_INST,
	177	.prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
cafc8cb5 NM	178	.pwrsts = PWRSTS_RET_ON,
cafc8cb5 NM	179	.pwrsts_logic_ret = PWRSTS_RET,
97dd16b1 A	180	.banks = 1,
	181	.pwrsts_mem_ret = {
	182	[0] = PWRSTS_OFF_RET, /* cpu1_l1 */
	183	},
	184	.pwrsts_mem_on = {
	185	[0] = PWRSTS_ON, /* cpu1_l1 */
	186	},
	187	};
	188
	189	/* vpe_7xx_pwrdm: */
	190	static struct powerdomain vpe_7xx_pwrdm = {
	191	.name = "vpe_pwrdm",
	192	.prcm_offs = DRA7XX_PRM_VPE_INST,
	193	.prcm_partition = DRA7XX_PRM_PARTITION,
dac4fba2	194	.pwrsts = PWRSTS_OFF_ON,
97dd16b1	195	.banks = 1,
97dd16b1	196	.pwrsts_mem_on = {
41feb8ef	197	[0] = PWRSTS_ON, /* vpe_bank */
97dd16b1 A	198	},
	199	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	200	};
	201
	202	/* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */
	203	static struct powerdomain mpu_7xx_pwrdm = {
	204	.name = "mpu_pwrdm",
	205	.prcm_offs = DRA7XX_PRM_MPU_INST,
	206	.prcm_partition = DRA7XX_PRM_PARTITION,
	207	.pwrsts = PWRSTS_RET_ON,
cafc8cb5	208	.pwrsts_logic_ret = PWRSTS_RET,
97dd16b1 A	209	.banks = 2,
	210	.pwrsts_mem_ret = {
	211	[0] = PWRSTS_OFF_RET, /* mpu_l2 */
	212	[1] = PWRSTS_RET, /* mpu_ram */
	213	},
	214	.pwrsts_mem_on = {
41feb8ef NM	215	[0] = PWRSTS_ON, /* mpu_l2 */
41feb8ef NM	216	[1] = PWRSTS_ON, /* mpu_ram */
97dd16b1 A	217	},
	218	};
	219
	220	/* l3init_7xx_pwrdm: L3 initators pheripherals power domain */
	221	static struct powerdomain l3init_7xx_pwrdm = {
	222	.name = "l3init_pwrdm",
	223	.prcm_offs = DRA7XX_PRM_L3INIT_INST,
	224	.prcm_partition = DRA7XX_PRM_PARTITION,
d16c0d72	225	.pwrsts = PWRSTS_ON,
97dd16b1	226	.banks = 3,
97dd16b1	227	.pwrsts_mem_on = {
41feb8ef NM	228	[0] = PWRSTS_ON, /* gmac_bank */
	229	[1] = PWRSTS_ON, /* l3init_bank1 */
	230	[2] = PWRSTS_ON, /* l3init_bank2 */
97dd16b1 A	231	},
	232	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	233	};
	234
	235	/* eve3_7xx_pwrdm: */
	236	static struct powerdomain eve3_7xx_pwrdm = {
	237	.name = "eve3_pwrdm",
	238	.prcm_offs = DRA7XX_PRM_EVE3_INST,
	239	.prcm_partition = DRA7XX_PRM_PARTITION,
	240	.pwrsts = PWRSTS_OFF_ON,
	241	.banks = 1,
97dd16b1	242	.pwrsts_mem_on = {
41feb8ef	243	[0] = PWRSTS_ON, /* eve3_bank */
97dd16b1 A	244	},
	245	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	246	};
	247
	248	/* emu_7xx_pwrdm: Emulation power domain */
	249	static struct powerdomain emu_7xx_pwrdm = {
	250	.name = "emu_pwrdm",
	251	.prcm_offs = DRA7XX_PRM_EMU_INST,
	252	.prcm_partition = DRA7XX_PRM_PARTITION,
	253	.pwrsts = PWRSTS_OFF_ON,
	254	.banks = 1,
97dd16b1	255	.pwrsts_mem_on = {
41feb8ef	256	[0] = PWRSTS_ON, /* emu_bank */
97dd16b1 A	257	},
	258	};
	259
	260	/* dsp2_7xx_pwrdm: */
	261	static struct powerdomain dsp2_7xx_pwrdm = {
	262	.name = "dsp2_pwrdm",
	263	.prcm_offs = DRA7XX_PRM_DSP2_INST,
	264	.prcm_partition = DRA7XX_PRM_PARTITION,
	265	.pwrsts = PWRSTS_OFF_ON,
	266	.banks = 3,
97dd16b1	267	.pwrsts_mem_on = {
41feb8ef NM	268	[0] = PWRSTS_ON, /* dsp2_edma */
	269	[1] = PWRSTS_ON, /* dsp2_l1 */
	270	[2] = PWRSTS_ON, /* dsp2_l2 */
97dd16b1 A	271	},
	272	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	273	};
	274
	275	/* dsp1_7xx_pwrdm: Tesla processor power domain */
	276	static struct powerdomain dsp1_7xx_pwrdm = {
	277	.name = "dsp1_pwrdm",
	278	.prcm_offs = DRA7XX_PRM_DSP1_INST,
	279	.prcm_partition = DRA7XX_PRM_PARTITION,
	280	.pwrsts = PWRSTS_OFF_ON,
	281	.banks = 3,
97dd16b1	282	.pwrsts_mem_on = {
41feb8ef NM	283	[0] = PWRSTS_ON, /* dsp1_edma */
	284	[1] = PWRSTS_ON, /* dsp1_l1 */
	285	[2] = PWRSTS_ON, /* dsp1_l2 */
97dd16b1 A	286	},
	287	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	288	};
	289
	290	/* cam_7xx_pwrdm: Camera subsystem power domain */
	291	static struct powerdomain cam_7xx_pwrdm = {
	292	.name = "cam_pwrdm",
	293	.prcm_offs = DRA7XX_PRM_CAM_INST,
	294	.prcm_partition = DRA7XX_PRM_PARTITION,
	295	.pwrsts = PWRSTS_OFF_ON,
	296	.banks = 1,
97dd16b1	297	.pwrsts_mem_on = {
41feb8ef	298	[0] = PWRSTS_ON, /* vip_bank */
97dd16b1 A	299	},
	300	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	301	};
	302
	303	/* eve4_7xx_pwrdm: */
	304	static struct powerdomain eve4_7xx_pwrdm = {
	305	.name = "eve4_pwrdm",
	306	.prcm_offs = DRA7XX_PRM_EVE4_INST,
	307	.prcm_partition = DRA7XX_PRM_PARTITION,
	308	.pwrsts = PWRSTS_OFF_ON,
	309	.banks = 1,
97dd16b1	310	.pwrsts_mem_on = {
41feb8ef	311	[0] = PWRSTS_ON, /* eve4_bank */
97dd16b1 A	312	},
	313	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	314	};
	315
	316	/* eve2_7xx_pwrdm: */
	317	static struct powerdomain eve2_7xx_pwrdm = {
	318	.name = "eve2_pwrdm",
	319	.prcm_offs = DRA7XX_PRM_EVE2_INST,
	320	.prcm_partition = DRA7XX_PRM_PARTITION,
	321	.pwrsts = PWRSTS_OFF_ON,
	322	.banks = 1,
97dd16b1	323	.pwrsts_mem_on = {
41feb8ef	324	[0] = PWRSTS_ON, /* eve2_bank */
97dd16b1 A	325	},
	326	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	327	};
	328
	329	/* eve1_7xx_pwrdm: */
	330	static struct powerdomain eve1_7xx_pwrdm = {
	331	.name = "eve1_pwrdm",
	332	.prcm_offs = DRA7XX_PRM_EVE1_INST,
	333	.prcm_partition = DRA7XX_PRM_PARTITION,
	334	.pwrsts = PWRSTS_OFF_ON,
	335	.banks = 1,
97dd16b1	336	.pwrsts_mem_on = {
41feb8ef	337	[0] = PWRSTS_ON, /* eve1_bank */
97dd16b1 A	338	},
	339	.flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
	340	};
	341
	342	/*
	343	* The following power domains are not under SW control
	344	*
	345	* mpuaon
	346	* mmaon
	347	*/
	348
	349	/* As powerdomains are added or removed above, this list must also be changed */
	350	static struct powerdomain *powerdomains_dra7xx[] __initdata = {
	351	&iva_7xx_pwrdm,
	352	&rtc_7xx_pwrdm,
	353	&custefuse_7xx_pwrdm,
	354	&ipu_7xx_pwrdm,
	355	&dss_7xx_pwrdm,
	356	&l4per_7xx_pwrdm,
	357	&gpu_7xx_pwrdm,
	358	&wkupaon_7xx_pwrdm,
	359	&core_7xx_pwrdm,
	360	&coreaon_7xx_pwrdm,
	361	&cpu0_7xx_pwrdm,
	362	&cpu1_7xx_pwrdm,
	363	&vpe_7xx_pwrdm,
	364	&mpu_7xx_pwrdm,
	365	&l3init_7xx_pwrdm,
	366	&eve3_7xx_pwrdm,
	367	&emu_7xx_pwrdm,
	368	&dsp2_7xx_pwrdm,
	369	&dsp1_7xx_pwrdm,
	370	&cam_7xx_pwrdm,
	371	&eve4_7xx_pwrdm,
	372	&eve2_7xx_pwrdm,
	373	&eve1_7xx_pwrdm,
	374	NULL
	375	};
	376
	377	void __init dra7xx_powerdomains_init(void)
	378	{
	379	pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
	380	pwrdm_register_pwrdms(powerdomains_dra7xx);
	381	pwrdm_complete_init();
	382	}