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9717100f PW |
1 | /* |
2 | * OMAP2/3 common powerdomain definitions | |
3 | * | |
55ed9694 PW |
4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. |
5 | * Copyright (C) 2007-2009 Nokia Corporation | |
9717100f PW |
6 | * |
7 | * Written by Paul Walmsley | |
8 | * Debugging and integration fixes by Jouni Högander | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
38900c27 AP |
15 | /* |
16 | * To Do List | |
17 | * -> Move the Sleep/Wakeup dependencies from Power Domain framework to | |
18 | * Clock Domain Framework | |
19 | */ | |
20 | ||
9717100f PW |
21 | /* |
22 | * This file contains all of the powerdomains that have some element | |
98fa3d8a | 23 | * of software control for the OMAP24xx and OMAP34xx chips. |
9717100f | 24 | * |
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25 | * This is not an exhaustive listing of powerdomains on the chips; only |
26 | * powerdomains that can be controlled in software. | |
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27 | */ |
28 | ||
29 | /* | |
30 | * The names for the DSP/IVA2 powerdomains are confusing. | |
31 | * | |
32 | * Most OMAP chips have an on-board DSP. | |
33 | * | |
34 | * On the 2420, this is a 'C55 DSP called, simply, the DSP. Its | |
35 | * powerdomain is called the "DSP power domain." On the 2430, the | |
55ed9694 PW |
36 | * on-board DSP is a 'C64 DSP, now called (along with its hardware |
37 | * accelerators) the IVA2 or IVA2.1. Its powerdomain is still called | |
38 | * the "DSP power domain." On the 3430, the DSP is a 'C64 DSP like the | |
39 | * 2430, also known as the IVA2; but its powerdomain is now called the | |
40 | * "IVA2 power domain." | |
9717100f PW |
41 | * |
42 | * The 2420 also has something called the IVA, which is a separate ARM | |
43 | * core, and has nothing to do with the DSP/IVA2. | |
44 | * | |
45 | * Ideally the DSP/IVA2 could just be the same powerdomain, but the PRCM | |
46 | * address offset is different between the C55 and C64 DSPs. | |
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47 | */ |
48 | ||
74bea6b9 | 49 | #include <linux/init.h> |
ce491cf8 | 50 | #include <plat/powerdomain.h> |
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51 | |
52 | #include "prcm-common.h" | |
53 | #include "prm.h" | |
54 | #include "cm.h" | |
fe6a58f8 | 55 | #include "powerdomains24xx.h" |
ecb24aa1 | 56 | #include "powerdomains34xx.h" |
38900c27 | 57 | #include "powerdomains44xx.h" |
f327e07b | 58 | #include "powerdomains.h" |
fe6a58f8 | 59 | |
55ed9694 | 60 | /* OMAP2/3-common powerdomains */ |
9717100f | 61 | |
98fa3d8a | 62 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
38900c27 | 63 | |
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64 | /* |
65 | * The GFX powerdomain is not present on 3430ES2, but currently we do not | |
66 | * have a macro to filter it out at compile-time. | |
67 | */ | |
38900c27 | 68 | static struct powerdomain gfx_omap2_pwrdm = { |
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69 | .name = "gfx_pwrdm", |
70 | .prcm_offs = GFX_MOD, | |
71 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | | |
72 | CHIP_IS_OMAP3430ES1), | |
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73 | .pwrsts = PWRSTS_OFF_RET_ON, |
74 | .pwrsts_logic_ret = PWRDM_POWER_RET, | |
75 | .banks = 1, | |
76 | .pwrsts_mem_ret = { | |
77 | [0] = PWRDM_POWER_RET, /* MEMRETSTATE */ | |
78 | }, | |
79 | .pwrsts_mem_on = { | |
80 | [0] = PWRDM_POWER_ON, /* MEMONSTATE */ | |
81 | }, | |
82 | }; | |
83 | ||
38900c27 | 84 | static struct powerdomain wkup_omap2_pwrdm = { |
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85 | .name = "wkup_pwrdm", |
86 | .prcm_offs = WKUP_MOD, | |
87 | .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430), | |
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88 | }; |
89 | ||
38900c27 | 90 | #endif |
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91 | |
92 | ||
93 | /* As powerdomains are added or removed above, this list must also be changed */ | |
94 | static struct powerdomain *powerdomains_omap[] __initdata = { | |
95 | ||
98fa3d8a | 96 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
38900c27 AP |
97 | &wkup_omap2_pwrdm, |
98 | &gfx_omap2_pwrdm, | |
99 | #endif | |
9717100f | 100 | |
98fa3d8a | 101 | #ifdef CONFIG_ARCH_OMAP2 |
fe6a58f8 PW |
102 | &dsp_pwrdm, |
103 | &mpu_24xx_pwrdm, | |
104 | &core_24xx_pwrdm, | |
105 | #endif | |
106 | ||
107 | #ifdef CONFIG_ARCH_OMAP2430 | |
108 | &mdm_pwrdm, | |
109 | #endif | |
110 | ||
98fa3d8a | 111 | #ifdef CONFIG_ARCH_OMAP3 |
ecb24aa1 | 112 | &iva2_pwrdm, |
98fa3d8a | 113 | &mpu_3xxx_pwrdm, |
ecb24aa1 | 114 | &neon_pwrdm, |
98fa3d8a PW |
115 | &core_3xxx_pre_es3_1_pwrdm, |
116 | &core_3xxx_es3_1_pwrdm, | |
ecb24aa1 PW |
117 | &cam_pwrdm, |
118 | &dss_pwrdm, | |
119 | &per_pwrdm, | |
120 | &emu_pwrdm, | |
121 | &sgx_pwrdm, | |
122 | &usbhost_pwrdm, | |
46e0ccf8 PW |
123 | &dpll1_pwrdm, |
124 | &dpll2_pwrdm, | |
125 | &dpll3_pwrdm, | |
126 | &dpll4_pwrdm, | |
127 | &dpll5_pwrdm, | |
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128 | #endif |
129 | ||
38900c27 AP |
130 | #ifdef CONFIG_ARCH_OMAP4 |
131 | &core_44xx_pwrdm, | |
132 | &gfx_44xx_pwrdm, | |
133 | &abe_44xx_pwrdm, | |
134 | &dss_44xx_pwrdm, | |
135 | &tesla_44xx_pwrdm, | |
136 | &wkup_44xx_pwrdm, | |
137 | &cpu0_44xx_pwrdm, | |
138 | &cpu1_44xx_pwrdm, | |
139 | &emu_44xx_pwrdm, | |
140 | &mpu_44xx_pwrdm, | |
141 | &ivahd_44xx_pwrdm, | |
142 | &cam_44xx_pwrdm, | |
143 | &l3init_44xx_pwrdm, | |
144 | &l4per_44xx_pwrdm, | |
145 | &always_on_core_44xx_pwrdm, | |
146 | &cefuse_44xx_pwrdm, | |
147 | #endif | |
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148 | NULL |
149 | }; | |
150 | ||
74bea6b9 RN |
151 | void pwrdm_fw_init(void) |
152 | { | |
f327e07b RN |
153 | if (cpu_is_omap24xx()) |
154 | pwrdm_init(powerdomains_omap, &omap2_pwrdm_operations); | |
155 | else if (cpu_is_omap34xx()) | |
156 | pwrdm_init(powerdomains_omap, &omap3_pwrdm_operations); | |
157 | else if (cpu_is_omap44xx()) | |
158 | pwrdm_init(powerdomains_omap, &omap4_pwrdm_operations); | |
74bea6b9 | 159 | } |