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69d88a00 PW |
1 | #ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H |
2 | #define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H | |
3 | ||
4 | /* | |
5 | * OMAP2/3 PRCM base and module definitions | |
6 | * | |
0a84a91c | 7 | * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc. |
77772d5f | 8 | * Copyright (C) 2007-2009 Nokia Corporation |
69d88a00 PW |
9 | * |
10 | * Written by Paul Walmsley | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
69d88a00 PW |
17 | /* Module offsets from both CM_BASE & PRM_BASE */ |
18 | ||
19 | /* | |
20 | * Offsets that are the same on 24xx and 34xx | |
21 | * | |
22 | * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is | |
23 | * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2. | |
24 | */ | |
25 | #define OCP_MOD 0x000 | |
26 | #define MPU_MOD 0x100 | |
27 | #define CORE_MOD 0x200 | |
28 | #define GFX_MOD 0x300 | |
29 | #define WKUP_MOD 0x400 | |
30 | #define PLL_MOD 0x500 | |
31 | ||
32 | ||
33 | /* Chip-specific module offsets */ | |
c2d43e39 | 34 | #define OMAP24XX_GR_MOD OCP_MOD |
69d88a00 PW |
35 | #define OMAP24XX_DSP_MOD 0x800 |
36 | ||
37 | #define OMAP2430_MDM_MOD 0xc00 | |
38 | ||
39 | /* IVA2 module is < base on 3430 */ | |
40 | #define OMAP3430_IVA2_MOD -0x800 | |
41 | #define OMAP3430ES2_SGX_MOD GFX_MOD | |
42 | #define OMAP3430_CCR_MOD PLL_MOD | |
43 | #define OMAP3430_DSS_MOD 0x600 | |
44 | #define OMAP3430_CAM_MOD 0x700 | |
45 | #define OMAP3430_PER_MOD 0x800 | |
46 | #define OMAP3430_EMU_MOD 0x900 | |
47 | #define OMAP3430_GR_MOD 0xa00 | |
48 | #define OMAP3430_NEON_MOD 0xb00 | |
49 | #define OMAP3430ES2_USBHOST_MOD 0xc00 | |
50 | ||
c3ed359c AM |
51 | /* |
52 | * TI81XX PRM module offsets | |
53 | */ | |
54 | #define TI81XX_PRM_DEVICE_MOD 0x0000 | |
55 | #define TI816X_PRM_ACTIVE_MOD 0x0a00 | |
56 | #define TI81XX_PRM_DEFAULT_MOD 0x0b00 | |
57 | #define TI816X_PRM_IVAHD0_MOD 0x0c00 | |
58 | #define TI816X_PRM_IVAHD1_MOD 0x0d00 | |
59 | #define TI816X_PRM_IVAHD2_MOD 0x0e00 | |
60 | #define TI816X_PRM_SGX_MOD 0x0f00 | |
61 | ||
69d88a00 PW |
62 | /* 24XX register bits shared between CM & PRM registers */ |
63 | ||
64 | /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ | |
65 | #define OMAP2420_EN_MMC_SHIFT 26 | |
2fd0f75c | 66 | #define OMAP2420_EN_MMC_MASK (1 << 26) |
69d88a00 | 67 | #define OMAP24XX_EN_UART2_SHIFT 22 |
2fd0f75c | 68 | #define OMAP24XX_EN_UART2_MASK (1 << 22) |
69d88a00 | 69 | #define OMAP24XX_EN_UART1_SHIFT 21 |
2fd0f75c | 70 | #define OMAP24XX_EN_UART1_MASK (1 << 21) |
69d88a00 | 71 | #define OMAP24XX_EN_MCSPI2_SHIFT 18 |
2fd0f75c | 72 | #define OMAP24XX_EN_MCSPI2_MASK (1 << 18) |
69d88a00 | 73 | #define OMAP24XX_EN_MCSPI1_SHIFT 17 |
2fd0f75c | 74 | #define OMAP24XX_EN_MCSPI1_MASK (1 << 17) |
69d88a00 | 75 | #define OMAP24XX_EN_MCBSP2_SHIFT 16 |
2fd0f75c | 76 | #define OMAP24XX_EN_MCBSP2_MASK (1 << 16) |
69d88a00 | 77 | #define OMAP24XX_EN_MCBSP1_SHIFT 15 |
2fd0f75c | 78 | #define OMAP24XX_EN_MCBSP1_MASK (1 << 15) |
69d88a00 | 79 | #define OMAP24XX_EN_GPT12_SHIFT 14 |
2fd0f75c | 80 | #define OMAP24XX_EN_GPT12_MASK (1 << 14) |
69d88a00 | 81 | #define OMAP24XX_EN_GPT11_SHIFT 13 |
2fd0f75c | 82 | #define OMAP24XX_EN_GPT11_MASK (1 << 13) |
69d88a00 | 83 | #define OMAP24XX_EN_GPT10_SHIFT 12 |
2fd0f75c | 84 | #define OMAP24XX_EN_GPT10_MASK (1 << 12) |
69d88a00 | 85 | #define OMAP24XX_EN_GPT9_SHIFT 11 |
2fd0f75c | 86 | #define OMAP24XX_EN_GPT9_MASK (1 << 11) |
69d88a00 | 87 | #define OMAP24XX_EN_GPT8_SHIFT 10 |
2fd0f75c | 88 | #define OMAP24XX_EN_GPT8_MASK (1 << 10) |
69d88a00 | 89 | #define OMAP24XX_EN_GPT7_SHIFT 9 |
2fd0f75c | 90 | #define OMAP24XX_EN_GPT7_MASK (1 << 9) |
69d88a00 | 91 | #define OMAP24XX_EN_GPT6_SHIFT 8 |
2fd0f75c | 92 | #define OMAP24XX_EN_GPT6_MASK (1 << 8) |
69d88a00 | 93 | #define OMAP24XX_EN_GPT5_SHIFT 7 |
2fd0f75c | 94 | #define OMAP24XX_EN_GPT5_MASK (1 << 7) |
69d88a00 | 95 | #define OMAP24XX_EN_GPT4_SHIFT 6 |
2fd0f75c | 96 | #define OMAP24XX_EN_GPT4_MASK (1 << 6) |
69d88a00 | 97 | #define OMAP24XX_EN_GPT3_SHIFT 5 |
2fd0f75c | 98 | #define OMAP24XX_EN_GPT3_MASK (1 << 5) |
69d88a00 | 99 | #define OMAP24XX_EN_GPT2_SHIFT 4 |
2fd0f75c | 100 | #define OMAP24XX_EN_GPT2_MASK (1 << 4) |
69d88a00 | 101 | #define OMAP2420_EN_VLYNQ_SHIFT 3 |
2fd0f75c | 102 | #define OMAP2420_EN_VLYNQ_MASK (1 << 3) |
69d88a00 PW |
103 | |
104 | /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ | |
105 | #define OMAP2430_EN_GPIO5_SHIFT 10 | |
2fd0f75c | 106 | #define OMAP2430_EN_GPIO5_MASK (1 << 10) |
69d88a00 | 107 | #define OMAP2430_EN_MCSPI3_SHIFT 9 |
2fd0f75c | 108 | #define OMAP2430_EN_MCSPI3_MASK (1 << 9) |
69d88a00 | 109 | #define OMAP2430_EN_MMCHS2_SHIFT 8 |
2fd0f75c | 110 | #define OMAP2430_EN_MMCHS2_MASK (1 << 8) |
69d88a00 | 111 | #define OMAP2430_EN_MMCHS1_SHIFT 7 |
2fd0f75c | 112 | #define OMAP2430_EN_MMCHS1_MASK (1 << 7) |
69d88a00 | 113 | #define OMAP24XX_EN_UART3_SHIFT 2 |
2fd0f75c | 114 | #define OMAP24XX_EN_UART3_MASK (1 << 2) |
69d88a00 | 115 | #define OMAP24XX_EN_USB_SHIFT 0 |
2fd0f75c | 116 | #define OMAP24XX_EN_USB_MASK (1 << 0) |
69d88a00 PW |
117 | |
118 | /* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ | |
119 | #define OMAP2430_EN_MDM_INTC_SHIFT 11 | |
2fd0f75c | 120 | #define OMAP2430_EN_MDM_INTC_MASK (1 << 11) |
69d88a00 | 121 | #define OMAP2430_EN_USBHS_SHIFT 6 |
2fd0f75c | 122 | #define OMAP2430_EN_USBHS_MASK (1 << 6) |
49484a60 AM |
123 | #define OMAP24XX_EN_GPMC_SHIFT 1 |
124 | #define OMAP24XX_EN_GPMC_MASK (1 << 1) | |
69d88a00 PW |
125 | |
126 | /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */ | |
da0747d4 PW |
127 | #define OMAP2420_ST_MMC_SHIFT 26 |
128 | #define OMAP2420_ST_MMC_MASK (1 << 26) | |
129 | #define OMAP24XX_ST_UART2_SHIFT 22 | |
130 | #define OMAP24XX_ST_UART2_MASK (1 << 22) | |
131 | #define OMAP24XX_ST_UART1_SHIFT 21 | |
132 | #define OMAP24XX_ST_UART1_MASK (1 << 21) | |
133 | #define OMAP24XX_ST_MCSPI2_SHIFT 18 | |
134 | #define OMAP24XX_ST_MCSPI2_MASK (1 << 18) | |
135 | #define OMAP24XX_ST_MCSPI1_SHIFT 17 | |
136 | #define OMAP24XX_ST_MCSPI1_MASK (1 << 17) | |
3cb72fa4 C |
137 | #define OMAP24XX_ST_MCBSP2_SHIFT 16 |
138 | #define OMAP24XX_ST_MCBSP2_MASK (1 << 16) | |
139 | #define OMAP24XX_ST_MCBSP1_SHIFT 15 | |
140 | #define OMAP24XX_ST_MCBSP1_MASK (1 << 15) | |
da0747d4 PW |
141 | #define OMAP24XX_ST_GPT12_SHIFT 14 |
142 | #define OMAP24XX_ST_GPT12_MASK (1 << 14) | |
143 | #define OMAP24XX_ST_GPT11_SHIFT 13 | |
144 | #define OMAP24XX_ST_GPT11_MASK (1 << 13) | |
145 | #define OMAP24XX_ST_GPT10_SHIFT 12 | |
146 | #define OMAP24XX_ST_GPT10_MASK (1 << 12) | |
147 | #define OMAP24XX_ST_GPT9_SHIFT 11 | |
148 | #define OMAP24XX_ST_GPT9_MASK (1 << 11) | |
149 | #define OMAP24XX_ST_GPT8_SHIFT 10 | |
150 | #define OMAP24XX_ST_GPT8_MASK (1 << 10) | |
151 | #define OMAP24XX_ST_GPT7_SHIFT 9 | |
152 | #define OMAP24XX_ST_GPT7_MASK (1 << 9) | |
153 | #define OMAP24XX_ST_GPT6_SHIFT 8 | |
154 | #define OMAP24XX_ST_GPT6_MASK (1 << 8) | |
155 | #define OMAP24XX_ST_GPT5_SHIFT 7 | |
156 | #define OMAP24XX_ST_GPT5_MASK (1 << 7) | |
157 | #define OMAP24XX_ST_GPT4_SHIFT 6 | |
158 | #define OMAP24XX_ST_GPT4_MASK (1 << 6) | |
159 | #define OMAP24XX_ST_GPT3_SHIFT 5 | |
160 | #define OMAP24XX_ST_GPT3_MASK (1 << 5) | |
161 | #define OMAP24XX_ST_GPT2_SHIFT 4 | |
162 | #define OMAP24XX_ST_GPT2_MASK (1 << 4) | |
163 | #define OMAP2420_ST_VLYNQ_SHIFT 3 | |
164 | #define OMAP2420_ST_VLYNQ_MASK (1 << 3) | |
69d88a00 PW |
165 | |
166 | /* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */ | |
da0747d4 PW |
167 | #define OMAP2430_ST_MDM_INTC_SHIFT 11 |
168 | #define OMAP2430_ST_MDM_INTC_MASK (1 << 11) | |
169 | #define OMAP2430_ST_GPIO5_SHIFT 10 | |
170 | #define OMAP2430_ST_GPIO5_MASK (1 << 10) | |
171 | #define OMAP2430_ST_MCSPI3_SHIFT 9 | |
172 | #define OMAP2430_ST_MCSPI3_MASK (1 << 9) | |
173 | #define OMAP2430_ST_MMCHS2_SHIFT 8 | |
174 | #define OMAP2430_ST_MMCHS2_MASK (1 << 8) | |
175 | #define OMAP2430_ST_MMCHS1_SHIFT 7 | |
176 | #define OMAP2430_ST_MMCHS1_MASK (1 << 7) | |
177 | #define OMAP2430_ST_USBHS_SHIFT 6 | |
178 | #define OMAP2430_ST_USBHS_MASK (1 << 6) | |
179 | #define OMAP24XX_ST_UART3_SHIFT 2 | |
180 | #define OMAP24XX_ST_UART3_MASK (1 << 2) | |
181 | #define OMAP24XX_ST_USB_SHIFT 0 | |
182 | #define OMAP24XX_ST_USB_MASK (1 << 0) | |
69d88a00 PW |
183 | |
184 | /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ | |
185 | #define OMAP24XX_EN_GPIOS_SHIFT 2 | |
2fd0f75c | 186 | #define OMAP24XX_EN_GPIOS_MASK (1 << 2) |
69d88a00 | 187 | #define OMAP24XX_EN_GPT1_SHIFT 0 |
2fd0f75c | 188 | #define OMAP24XX_EN_GPT1_MASK (1 << 0) |
69d88a00 PW |
189 | |
190 | /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */ | |
c2015dc8 PW |
191 | #define OMAP24XX_ST_GPIOS_SHIFT 2 |
192 | #define OMAP24XX_ST_GPIOS_MASK (1 << 2) | |
444b3df6 VH |
193 | #define OMAP24XX_ST_32KSYNC_SHIFT 1 |
194 | #define OMAP24XX_ST_32KSYNC_MASK (1 << 1) | |
c2015dc8 PW |
195 | #define OMAP24XX_ST_GPT1_SHIFT 0 |
196 | #define OMAP24XX_ST_GPT1_MASK (1 << 0) | |
69d88a00 PW |
197 | |
198 | /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */ | |
c2015dc8 PW |
199 | #define OMAP2430_ST_MDM_SHIFT 0 |
200 | #define OMAP2430_ST_MDM_MASK (1 << 0) | |
69d88a00 PW |
201 | |
202 | ||
203 | /* 3430 register bits shared between CM & PRM registers */ | |
204 | ||
205 | /* CM_REVISION, PRM_REVISION shared bits */ | |
206 | #define OMAP3430_REV_SHIFT 0 | |
207 | #define OMAP3430_REV_MASK (0xff << 0) | |
208 | ||
209 | /* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */ | |
2fd0f75c | 210 | #define OMAP3430_AUTOIDLE_MASK (1 << 0) |
69d88a00 PW |
211 | |
212 | /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ | |
b163605e PW |
213 | #define OMAP3430_EN_MMC3_MASK (1 << 30) |
214 | #define OMAP3430_EN_MMC3_SHIFT 30 | |
2fd0f75c | 215 | #define OMAP3430_EN_MMC2_MASK (1 << 25) |
69d88a00 | 216 | #define OMAP3430_EN_MMC2_SHIFT 25 |
2fd0f75c | 217 | #define OMAP3430_EN_MMC1_MASK (1 << 24) |
69d88a00 | 218 | #define OMAP3430_EN_MMC1_SHIFT 24 |
bf765237 PW |
219 | #define AM35XX_EN_UART4_MASK (1 << 23) |
220 | #define AM35XX_EN_UART4_SHIFT 23 | |
2fd0f75c | 221 | #define OMAP3430_EN_MCSPI4_MASK (1 << 21) |
69d88a00 | 222 | #define OMAP3430_EN_MCSPI4_SHIFT 21 |
2fd0f75c | 223 | #define OMAP3430_EN_MCSPI3_MASK (1 << 20) |
69d88a00 | 224 | #define OMAP3430_EN_MCSPI3_SHIFT 20 |
2fd0f75c | 225 | #define OMAP3430_EN_MCSPI2_MASK (1 << 19) |
69d88a00 | 226 | #define OMAP3430_EN_MCSPI2_SHIFT 19 |
2fd0f75c | 227 | #define OMAP3430_EN_MCSPI1_MASK (1 << 18) |
69d88a00 | 228 | #define OMAP3430_EN_MCSPI1_SHIFT 18 |
2fd0f75c | 229 | #define OMAP3430_EN_I2C3_MASK (1 << 17) |
69d88a00 | 230 | #define OMAP3430_EN_I2C3_SHIFT 17 |
2fd0f75c | 231 | #define OMAP3430_EN_I2C2_MASK (1 << 16) |
69d88a00 | 232 | #define OMAP3430_EN_I2C2_SHIFT 16 |
2fd0f75c | 233 | #define OMAP3430_EN_I2C1_MASK (1 << 15) |
69d88a00 | 234 | #define OMAP3430_EN_I2C1_SHIFT 15 |
2fd0f75c | 235 | #define OMAP3430_EN_UART2_MASK (1 << 14) |
69d88a00 | 236 | #define OMAP3430_EN_UART2_SHIFT 14 |
2fd0f75c | 237 | #define OMAP3430_EN_UART1_MASK (1 << 13) |
69d88a00 | 238 | #define OMAP3430_EN_UART1_SHIFT 13 |
2fd0f75c | 239 | #define OMAP3430_EN_GPT11_MASK (1 << 12) |
69d88a00 | 240 | #define OMAP3430_EN_GPT11_SHIFT 12 |
2fd0f75c | 241 | #define OMAP3430_EN_GPT10_MASK (1 << 11) |
69d88a00 | 242 | #define OMAP3430_EN_GPT10_SHIFT 11 |
2fd0f75c | 243 | #define OMAP3430_EN_MCBSP5_MASK (1 << 10) |
69d88a00 | 244 | #define OMAP3430_EN_MCBSP5_SHIFT 10 |
2fd0f75c | 245 | #define OMAP3430_EN_MCBSP1_MASK (1 << 9) |
69d88a00 | 246 | #define OMAP3430_EN_MCBSP1_SHIFT 9 |
2fd0f75c | 247 | #define OMAP3430_EN_FSHOSTUSB_MASK (1 << 5) |
69d88a00 | 248 | #define OMAP3430_EN_FSHOSTUSB_SHIFT 5 |
2fd0f75c | 249 | #define OMAP3430_EN_D2D_MASK (1 << 3) |
69d88a00 PW |
250 | #define OMAP3430_EN_D2D_SHIFT 3 |
251 | ||
252 | /* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ | |
2fd0f75c PW |
253 | #define OMAP3430_EN_HSOTGUSB_MASK (1 << 4) |
254 | #define OMAP3430_EN_HSOTGUSB_SHIFT 4 | |
69d88a00 PW |
255 | |
256 | /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ | |
b163605e PW |
257 | #define OMAP3430_ST_MMC3_SHIFT 30 |
258 | #define OMAP3430_ST_MMC3_MASK (1 << 30) | |
da0747d4 PW |
259 | #define OMAP3430_ST_MMC2_SHIFT 25 |
260 | #define OMAP3430_ST_MMC2_MASK (1 << 25) | |
261 | #define OMAP3430_ST_MMC1_SHIFT 24 | |
262 | #define OMAP3430_ST_MMC1_MASK (1 << 24) | |
263 | #define OMAP3430_ST_MCSPI4_SHIFT 21 | |
264 | #define OMAP3430_ST_MCSPI4_MASK (1 << 21) | |
265 | #define OMAP3430_ST_MCSPI3_SHIFT 20 | |
266 | #define OMAP3430_ST_MCSPI3_MASK (1 << 20) | |
267 | #define OMAP3430_ST_MCSPI2_SHIFT 19 | |
268 | #define OMAP3430_ST_MCSPI2_MASK (1 << 19) | |
269 | #define OMAP3430_ST_MCSPI1_SHIFT 18 | |
270 | #define OMAP3430_ST_MCSPI1_MASK (1 << 18) | |
271 | #define OMAP3430_ST_I2C3_SHIFT 17 | |
272 | #define OMAP3430_ST_I2C3_MASK (1 << 17) | |
273 | #define OMAP3430_ST_I2C2_SHIFT 16 | |
274 | #define OMAP3430_ST_I2C2_MASK (1 << 16) | |
275 | #define OMAP3430_ST_I2C1_SHIFT 15 | |
276 | #define OMAP3430_ST_I2C1_MASK (1 << 15) | |
277 | #define OMAP3430_ST_UART2_SHIFT 14 | |
278 | #define OMAP3430_ST_UART2_MASK (1 << 14) | |
279 | #define OMAP3430_ST_UART1_SHIFT 13 | |
280 | #define OMAP3430_ST_UART1_MASK (1 << 13) | |
281 | #define OMAP3430_ST_GPT11_SHIFT 12 | |
282 | #define OMAP3430_ST_GPT11_MASK (1 << 12) | |
283 | #define OMAP3430_ST_GPT10_SHIFT 11 | |
284 | #define OMAP3430_ST_GPT10_MASK (1 << 11) | |
285 | #define OMAP3430_ST_MCBSP5_SHIFT 10 | |
286 | #define OMAP3430_ST_MCBSP5_MASK (1 << 10) | |
287 | #define OMAP3430_ST_MCBSP1_SHIFT 9 | |
288 | #define OMAP3430_ST_MCBSP1_MASK (1 << 9) | |
289 | #define OMAP3430ES1_ST_FSHOSTUSB_SHIFT 5 | |
290 | #define OMAP3430ES1_ST_FSHOSTUSB_MASK (1 << 5) | |
291 | #define OMAP3430ES1_ST_HSOTGUSB_SHIFT 4 | |
292 | #define OMAP3430ES1_ST_HSOTGUSB_MASK (1 << 4) | |
293 | #define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT 5 | |
294 | #define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK (1 << 5) | |
295 | #define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 4 | |
296 | #define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK (1 << 4) | |
297 | #define OMAP3430_ST_D2D_SHIFT 3 | |
298 | #define OMAP3430_ST_D2D_MASK (1 << 3) | |
69d88a00 PW |
299 | |
300 | /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ | |
2fd0f75c | 301 | #define OMAP3430_EN_GPIO1_MASK (1 << 3) |
69d88a00 | 302 | #define OMAP3430_EN_GPIO1_SHIFT 3 |
2fd0f75c | 303 | #define OMAP3430_EN_GPT12_MASK (1 << 1) |
8bd22949 | 304 | #define OMAP3430_EN_GPT12_SHIFT 1 |
2fd0f75c | 305 | #define OMAP3430_EN_GPT1_MASK (1 << 0) |
69d88a00 PW |
306 | #define OMAP3430_EN_GPT1_SHIFT 0 |
307 | ||
308 | /* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */ | |
2fd0f75c | 309 | #define OMAP3430_EN_SR2_MASK (1 << 7) |
69d88a00 | 310 | #define OMAP3430_EN_SR2_SHIFT 7 |
2fd0f75c | 311 | #define OMAP3430_EN_SR1_MASK (1 << 6) |
69d88a00 PW |
312 | #define OMAP3430_EN_SR1_SHIFT 6 |
313 | ||
314 | /* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ | |
2fd0f75c | 315 | #define OMAP3430_EN_GPT12_MASK (1 << 1) |
69d88a00 PW |
316 | #define OMAP3430_EN_GPT12_SHIFT 1 |
317 | ||
318 | /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */ | |
da0747d4 PW |
319 | #define OMAP3430_ST_SR2_SHIFT 7 |
320 | #define OMAP3430_ST_SR2_MASK (1 << 7) | |
321 | #define OMAP3430_ST_SR1_SHIFT 6 | |
322 | #define OMAP3430_ST_SR1_MASK (1 << 6) | |
323 | #define OMAP3430_ST_GPIO1_SHIFT 3 | |
324 | #define OMAP3430_ST_GPIO1_MASK (1 << 3) | |
444b3df6 VH |
325 | #define OMAP3430_ST_32KSYNC_SHIFT 2 |
326 | #define OMAP3430_ST_32KSYNC_MASK (1 << 2) | |
da0747d4 PW |
327 | #define OMAP3430_ST_GPT12_SHIFT 1 |
328 | #define OMAP3430_ST_GPT12_MASK (1 << 1) | |
329 | #define OMAP3430_ST_GPT1_SHIFT 0 | |
330 | #define OMAP3430_ST_GPT1_MASK (1 << 0) | |
69d88a00 PW |
331 | |
332 | /* | |
333 | * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM, | |
334 | * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX, | |
335 | * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits | |
336 | */ | |
2fd0f75c | 337 | #define OMAP3430_EN_MPU_MASK (1 << 1) |
69d88a00 PW |
338 | #define OMAP3430_EN_MPU_SHIFT 1 |
339 | ||
340 | /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */ | |
046465b7 KH |
341 | |
342 | #define OMAP3630_EN_UART4_MASK (1 << 18) | |
343 | #define OMAP3630_EN_UART4_SHIFT 18 | |
2fd0f75c | 344 | #define OMAP3430_EN_GPIO6_MASK (1 << 17) |
69d88a00 | 345 | #define OMAP3430_EN_GPIO6_SHIFT 17 |
2fd0f75c | 346 | #define OMAP3430_EN_GPIO5_MASK (1 << 16) |
69d88a00 | 347 | #define OMAP3430_EN_GPIO5_SHIFT 16 |
2fd0f75c | 348 | #define OMAP3430_EN_GPIO4_MASK (1 << 15) |
69d88a00 | 349 | #define OMAP3430_EN_GPIO4_SHIFT 15 |
2fd0f75c | 350 | #define OMAP3430_EN_GPIO3_MASK (1 << 14) |
69d88a00 | 351 | #define OMAP3430_EN_GPIO3_SHIFT 14 |
2fd0f75c | 352 | #define OMAP3430_EN_GPIO2_MASK (1 << 13) |
69d88a00 | 353 | #define OMAP3430_EN_GPIO2_SHIFT 13 |
2fd0f75c | 354 | #define OMAP3430_EN_UART3_MASK (1 << 11) |
69d88a00 | 355 | #define OMAP3430_EN_UART3_SHIFT 11 |
2fd0f75c | 356 | #define OMAP3430_EN_GPT9_MASK (1 << 10) |
69d88a00 | 357 | #define OMAP3430_EN_GPT9_SHIFT 10 |
2fd0f75c | 358 | #define OMAP3430_EN_GPT8_MASK (1 << 9) |
69d88a00 | 359 | #define OMAP3430_EN_GPT8_SHIFT 9 |
2fd0f75c | 360 | #define OMAP3430_EN_GPT7_MASK (1 << 8) |
69d88a00 | 361 | #define OMAP3430_EN_GPT7_SHIFT 8 |
2fd0f75c | 362 | #define OMAP3430_EN_GPT6_MASK (1 << 7) |
69d88a00 | 363 | #define OMAP3430_EN_GPT6_SHIFT 7 |
2fd0f75c | 364 | #define OMAP3430_EN_GPT5_MASK (1 << 6) |
69d88a00 | 365 | #define OMAP3430_EN_GPT5_SHIFT 6 |
2fd0f75c | 366 | #define OMAP3430_EN_GPT4_MASK (1 << 5) |
69d88a00 | 367 | #define OMAP3430_EN_GPT4_SHIFT 5 |
2fd0f75c | 368 | #define OMAP3430_EN_GPT3_MASK (1 << 4) |
69d88a00 | 369 | #define OMAP3430_EN_GPT3_SHIFT 4 |
2fd0f75c | 370 | #define OMAP3430_EN_GPT2_MASK (1 << 3) |
69d88a00 PW |
371 | #define OMAP3430_EN_GPT2_SHIFT 3 |
372 | ||
373 | /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */ | |
374 | /* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits | |
375 | * be ST_* bits instead? */ | |
2fd0f75c | 376 | #define OMAP3430_EN_MCBSP4_MASK (1 << 2) |
69d88a00 | 377 | #define OMAP3430_EN_MCBSP4_SHIFT 2 |
2fd0f75c | 378 | #define OMAP3430_EN_MCBSP3_MASK (1 << 1) |
69d88a00 | 379 | #define OMAP3430_EN_MCBSP3_SHIFT 1 |
2fd0f75c | 380 | #define OMAP3430_EN_MCBSP2_MASK (1 << 0) |
69d88a00 PW |
381 | #define OMAP3430_EN_MCBSP2_SHIFT 0 |
382 | ||
383 | /* CM_IDLEST_PER, PM_WKST_PER shared bits */ | |
e5863689 G |
384 | #define OMAP3630_ST_UART4_SHIFT 18 |
385 | #define OMAP3630_ST_UART4_MASK (1 << 18) | |
da0747d4 PW |
386 | #define OMAP3430_ST_GPIO6_SHIFT 17 |
387 | #define OMAP3430_ST_GPIO6_MASK (1 << 17) | |
388 | #define OMAP3430_ST_GPIO5_SHIFT 16 | |
389 | #define OMAP3430_ST_GPIO5_MASK (1 << 16) | |
390 | #define OMAP3430_ST_GPIO4_SHIFT 15 | |
391 | #define OMAP3430_ST_GPIO4_MASK (1 << 15) | |
392 | #define OMAP3430_ST_GPIO3_SHIFT 14 | |
393 | #define OMAP3430_ST_GPIO3_MASK (1 << 14) | |
394 | #define OMAP3430_ST_GPIO2_SHIFT 13 | |
395 | #define OMAP3430_ST_GPIO2_MASK (1 << 13) | |
396 | #define OMAP3430_ST_UART3_SHIFT 11 | |
397 | #define OMAP3430_ST_UART3_MASK (1 << 11) | |
398 | #define OMAP3430_ST_GPT9_SHIFT 10 | |
399 | #define OMAP3430_ST_GPT9_MASK (1 << 10) | |
400 | #define OMAP3430_ST_GPT8_SHIFT 9 | |
401 | #define OMAP3430_ST_GPT8_MASK (1 << 9) | |
402 | #define OMAP3430_ST_GPT7_SHIFT 8 | |
403 | #define OMAP3430_ST_GPT7_MASK (1 << 8) | |
404 | #define OMAP3430_ST_GPT6_SHIFT 7 | |
405 | #define OMAP3430_ST_GPT6_MASK (1 << 7) | |
406 | #define OMAP3430_ST_GPT5_SHIFT 6 | |
407 | #define OMAP3430_ST_GPT5_MASK (1 << 6) | |
408 | #define OMAP3430_ST_GPT4_SHIFT 5 | |
409 | #define OMAP3430_ST_GPT4_MASK (1 << 5) | |
410 | #define OMAP3430_ST_GPT3_SHIFT 4 | |
411 | #define OMAP3430_ST_GPT3_MASK (1 << 4) | |
412 | #define OMAP3430_ST_GPT2_SHIFT 3 | |
413 | #define OMAP3430_ST_GPT2_MASK (1 << 3) | |
69d88a00 PW |
414 | |
415 | /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */ | |
ecb24aa1 PW |
416 | #define OMAP3430_EN_CORE_SHIFT 0 |
417 | #define OMAP3430_EN_CORE_MASK (1 << 0) | |
69d88a00 | 418 | |
d198b514 | 419 | |
d198b514 | 420 | |
09659fa7 VB |
421 | /* |
422 | * Maximum time(us) it takes to output the signal WUCLKOUT of the last | |
423 | * pad of the I/O ring after asserting WUCLKIN high. Tero measured | |
424 | * the actual time at 7 to 8 microseconds on OMAP3 and 2 to 4 | |
425 | * microseconds on OMAP4, so this timeout may be too high. | |
426 | */ | |
427 | #define MAX_IOPAD_LATCH_TIME 100 | |
59fb659b | 428 | # ifndef __ASSEMBLER__ |
0a84a91c TK |
429 | |
430 | /** | |
431 | * struct omap_prcm_irq - describes a PRCM interrupt bit | |
432 | * @name: a short name describing the interrupt type, e.g. "wkup" or "io" | |
433 | * @offset: the bit shift of the interrupt inside the IRQ{ENABLE,STATUS} regs | |
434 | * @priority: should this interrupt be handled before @priority=false IRQs? | |
435 | * | |
436 | * Describes interrupt bits inside the PRM_IRQ{ENABLE,STATUS}_MPU* registers. | |
437 | * On systems with multiple PRM MPU IRQ registers, the bitfields read from | |
438 | * the registers are concatenated, so @offset could be > 31 on these systems - | |
439 | * see omap_prm_irq_handler() for more details. I/O ring interrupts should | |
440 | * have @priority set to true. | |
441 | */ | |
442 | struct omap_prcm_irq { | |
443 | const char *name; | |
444 | unsigned int offset; | |
445 | bool priority; | |
446 | }; | |
447 | ||
448 | /** | |
449 | * struct omap_prcm_irq_setup - PRCM interrupt controller details | |
450 | * @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register | |
451 | * @mask: PRM register offset for the first PRM_IRQENABLE_MPU register | |
452 | * @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers | |
453 | * @nr_irqs: number of entries in the @irqs array | |
454 | * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs) | |
455 | * @irq: MPU IRQ asserted when a PRCM interrupt arrives | |
456 | * @read_pending_irqs: fn ptr to determine if any PRCM IRQs are pending | |
457 | * @ocp_barrier: fn ptr to force buffered PRM writes to complete | |
91285b6f TK |
458 | * @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs |
459 | * @restore_irqen: fn ptr to save and clear IRQENABLE regs | |
460 | * @saved_mask: IRQENABLE regs are saved here during suspend | |
0a84a91c TK |
461 | * @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true |
462 | * @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init | |
91285b6f TK |
463 | * @suspended: set to true after Linux suspend code has called our ->prepare() |
464 | * @suspend_save_flag: set to true after IRQ masks have been saved and disabled | |
0a84a91c | 465 | * |
91285b6f TK |
466 | * @saved_mask, @priority_mask, @base_irq, @suspended, and |
467 | * @suspend_save_flag are populated dynamically, and are not to be | |
0a84a91c TK |
468 | * specified in static initializers. |
469 | */ | |
470 | struct omap_prcm_irq_setup { | |
471 | u16 ack; | |
472 | u16 mask; | |
473 | u8 nr_regs; | |
474 | u8 nr_irqs; | |
475 | const struct omap_prcm_irq *irqs; | |
476 | int irq; | |
477 | void (*read_pending_irqs)(unsigned long *events); | |
478 | void (*ocp_barrier)(void); | |
91285b6f TK |
479 | void (*save_and_clear_irqen)(u32 *saved_mask); |
480 | void (*restore_irqen)(u32 *saved_mask); | |
481 | u32 *saved_mask; | |
0a84a91c TK |
482 | u32 *priority_mask; |
483 | int base_irq; | |
91285b6f TK |
484 | bool suspended; |
485 | bool suspend_save_flag; | |
0a84a91c TK |
486 | }; |
487 | ||
488 | /* OMAP_PRCM_IRQ: convenience macro for creating struct omap_prcm_irq records */ | |
489 | #define OMAP_PRCM_IRQ(_name, _offset, _priority) { \ | |
490 | .name = _name, \ | |
491 | .offset = _offset, \ | |
492 | .priority = _priority \ | |
493 | } | |
494 | ||
495 | extern void omap_prcm_irq_cleanup(void); | |
496 | extern int omap_prcm_register_chain_handler( | |
497 | struct omap_prcm_irq_setup *irq_setup); | |
498 | extern int omap_prcm_event_to_irq(const char *event); | |
91285b6f TK |
499 | extern void omap_prcm_irq_prepare(void); |
500 | extern void omap_prcm_irq_complete(void); | |
0a84a91c | 501 | |
59fb659b PW |
502 | # endif |
503 | ||
69d88a00 PW |
504 | #endif |
505 |