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69d88a00 PW |
1 | #ifndef __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H |
2 | #define __ARCH_ASM_MACH_OMAP2_PRCM_COMMON_H | |
3 | ||
4 | /* | |
5 | * OMAP2/3 PRCM base and module definitions | |
6 | * | |
0a84a91c | 7 | * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc. |
77772d5f | 8 | * Copyright (C) 2007-2009 Nokia Corporation |
69d88a00 PW |
9 | * |
10 | * Written by Paul Walmsley | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License version 2 as | |
14 | * published by the Free Software Foundation. | |
15 | */ | |
16 | ||
69d88a00 PW |
17 | /* Module offsets from both CM_BASE & PRM_BASE */ |
18 | ||
19 | /* | |
20 | * Offsets that are the same on 24xx and 34xx | |
21 | * | |
22 | * Technically, in terms of the TRM, OCP_MOD is 34xx only; PLL_MOD is | |
23 | * CCR_MOD on 3430; and GFX_MOD only exists < 3430ES2. | |
24 | */ | |
25 | #define OCP_MOD 0x000 | |
26 | #define MPU_MOD 0x100 | |
27 | #define CORE_MOD 0x200 | |
28 | #define GFX_MOD 0x300 | |
29 | #define WKUP_MOD 0x400 | |
30 | #define PLL_MOD 0x500 | |
31 | ||
32 | ||
33 | /* Chip-specific module offsets */ | |
c2d43e39 | 34 | #define OMAP24XX_GR_MOD OCP_MOD |
69d88a00 PW |
35 | #define OMAP24XX_DSP_MOD 0x800 |
36 | ||
37 | #define OMAP2430_MDM_MOD 0xc00 | |
38 | ||
39 | /* IVA2 module is < base on 3430 */ | |
40 | #define OMAP3430_IVA2_MOD -0x800 | |
41 | #define OMAP3430ES2_SGX_MOD GFX_MOD | |
42 | #define OMAP3430_CCR_MOD PLL_MOD | |
43 | #define OMAP3430_DSS_MOD 0x600 | |
44 | #define OMAP3430_CAM_MOD 0x700 | |
45 | #define OMAP3430_PER_MOD 0x800 | |
46 | #define OMAP3430_EMU_MOD 0x900 | |
47 | #define OMAP3430_GR_MOD 0xa00 | |
48 | #define OMAP3430_NEON_MOD 0xb00 | |
49 | #define OMAP3430ES2_USBHOST_MOD 0xc00 | |
50 | ||
69d88a00 PW |
51 | /* 24XX register bits shared between CM & PRM registers */ |
52 | ||
53 | /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ | |
54 | #define OMAP2420_EN_MMC_SHIFT 26 | |
2fd0f75c | 55 | #define OMAP2420_EN_MMC_MASK (1 << 26) |
69d88a00 | 56 | #define OMAP24XX_EN_UART2_SHIFT 22 |
2fd0f75c | 57 | #define OMAP24XX_EN_UART2_MASK (1 << 22) |
69d88a00 | 58 | #define OMAP24XX_EN_UART1_SHIFT 21 |
2fd0f75c | 59 | #define OMAP24XX_EN_UART1_MASK (1 << 21) |
69d88a00 | 60 | #define OMAP24XX_EN_MCSPI2_SHIFT 18 |
2fd0f75c | 61 | #define OMAP24XX_EN_MCSPI2_MASK (1 << 18) |
69d88a00 | 62 | #define OMAP24XX_EN_MCSPI1_SHIFT 17 |
2fd0f75c | 63 | #define OMAP24XX_EN_MCSPI1_MASK (1 << 17) |
69d88a00 | 64 | #define OMAP24XX_EN_MCBSP2_SHIFT 16 |
2fd0f75c | 65 | #define OMAP24XX_EN_MCBSP2_MASK (1 << 16) |
69d88a00 | 66 | #define OMAP24XX_EN_MCBSP1_SHIFT 15 |
2fd0f75c | 67 | #define OMAP24XX_EN_MCBSP1_MASK (1 << 15) |
69d88a00 | 68 | #define OMAP24XX_EN_GPT12_SHIFT 14 |
2fd0f75c | 69 | #define OMAP24XX_EN_GPT12_MASK (1 << 14) |
69d88a00 | 70 | #define OMAP24XX_EN_GPT11_SHIFT 13 |
2fd0f75c | 71 | #define OMAP24XX_EN_GPT11_MASK (1 << 13) |
69d88a00 | 72 | #define OMAP24XX_EN_GPT10_SHIFT 12 |
2fd0f75c | 73 | #define OMAP24XX_EN_GPT10_MASK (1 << 12) |
69d88a00 | 74 | #define OMAP24XX_EN_GPT9_SHIFT 11 |
2fd0f75c | 75 | #define OMAP24XX_EN_GPT9_MASK (1 << 11) |
69d88a00 | 76 | #define OMAP24XX_EN_GPT8_SHIFT 10 |
2fd0f75c | 77 | #define OMAP24XX_EN_GPT8_MASK (1 << 10) |
69d88a00 | 78 | #define OMAP24XX_EN_GPT7_SHIFT 9 |
2fd0f75c | 79 | #define OMAP24XX_EN_GPT7_MASK (1 << 9) |
69d88a00 | 80 | #define OMAP24XX_EN_GPT6_SHIFT 8 |
2fd0f75c | 81 | #define OMAP24XX_EN_GPT6_MASK (1 << 8) |
69d88a00 | 82 | #define OMAP24XX_EN_GPT5_SHIFT 7 |
2fd0f75c | 83 | #define OMAP24XX_EN_GPT5_MASK (1 << 7) |
69d88a00 | 84 | #define OMAP24XX_EN_GPT4_SHIFT 6 |
2fd0f75c | 85 | #define OMAP24XX_EN_GPT4_MASK (1 << 6) |
69d88a00 | 86 | #define OMAP24XX_EN_GPT3_SHIFT 5 |
2fd0f75c | 87 | #define OMAP24XX_EN_GPT3_MASK (1 << 5) |
69d88a00 | 88 | #define OMAP24XX_EN_GPT2_SHIFT 4 |
2fd0f75c | 89 | #define OMAP24XX_EN_GPT2_MASK (1 << 4) |
69d88a00 | 90 | #define OMAP2420_EN_VLYNQ_SHIFT 3 |
2fd0f75c | 91 | #define OMAP2420_EN_VLYNQ_MASK (1 << 3) |
69d88a00 PW |
92 | |
93 | /* CM_FCLKEN2_CORE, CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ | |
94 | #define OMAP2430_EN_GPIO5_SHIFT 10 | |
2fd0f75c | 95 | #define OMAP2430_EN_GPIO5_MASK (1 << 10) |
69d88a00 | 96 | #define OMAP2430_EN_MCSPI3_SHIFT 9 |
2fd0f75c | 97 | #define OMAP2430_EN_MCSPI3_MASK (1 << 9) |
69d88a00 | 98 | #define OMAP2430_EN_MMCHS2_SHIFT 8 |
2fd0f75c | 99 | #define OMAP2430_EN_MMCHS2_MASK (1 << 8) |
69d88a00 | 100 | #define OMAP2430_EN_MMCHS1_SHIFT 7 |
2fd0f75c | 101 | #define OMAP2430_EN_MMCHS1_MASK (1 << 7) |
69d88a00 | 102 | #define OMAP24XX_EN_UART3_SHIFT 2 |
2fd0f75c | 103 | #define OMAP24XX_EN_UART3_MASK (1 << 2) |
69d88a00 | 104 | #define OMAP24XX_EN_USB_SHIFT 0 |
2fd0f75c | 105 | #define OMAP24XX_EN_USB_MASK (1 << 0) |
69d88a00 PW |
106 | |
107 | /* CM_ICLKEN2_CORE, PM_WKEN2_CORE shared bits */ | |
108 | #define OMAP2430_EN_MDM_INTC_SHIFT 11 | |
2fd0f75c | 109 | #define OMAP2430_EN_MDM_INTC_MASK (1 << 11) |
69d88a00 | 110 | #define OMAP2430_EN_USBHS_SHIFT 6 |
2fd0f75c | 111 | #define OMAP2430_EN_USBHS_MASK (1 << 6) |
69d88a00 PW |
112 | |
113 | /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */ | |
da0747d4 PW |
114 | #define OMAP2420_ST_MMC_SHIFT 26 |
115 | #define OMAP2420_ST_MMC_MASK (1 << 26) | |
116 | #define OMAP24XX_ST_UART2_SHIFT 22 | |
117 | #define OMAP24XX_ST_UART2_MASK (1 << 22) | |
118 | #define OMAP24XX_ST_UART1_SHIFT 21 | |
119 | #define OMAP24XX_ST_UART1_MASK (1 << 21) | |
120 | #define OMAP24XX_ST_MCSPI2_SHIFT 18 | |
121 | #define OMAP24XX_ST_MCSPI2_MASK (1 << 18) | |
122 | #define OMAP24XX_ST_MCSPI1_SHIFT 17 | |
123 | #define OMAP24XX_ST_MCSPI1_MASK (1 << 17) | |
3cb72fa4 C |
124 | #define OMAP24XX_ST_MCBSP2_SHIFT 16 |
125 | #define OMAP24XX_ST_MCBSP2_MASK (1 << 16) | |
126 | #define OMAP24XX_ST_MCBSP1_SHIFT 15 | |
127 | #define OMAP24XX_ST_MCBSP1_MASK (1 << 15) | |
da0747d4 PW |
128 | #define OMAP24XX_ST_GPT12_SHIFT 14 |
129 | #define OMAP24XX_ST_GPT12_MASK (1 << 14) | |
130 | #define OMAP24XX_ST_GPT11_SHIFT 13 | |
131 | #define OMAP24XX_ST_GPT11_MASK (1 << 13) | |
132 | #define OMAP24XX_ST_GPT10_SHIFT 12 | |
133 | #define OMAP24XX_ST_GPT10_MASK (1 << 12) | |
134 | #define OMAP24XX_ST_GPT9_SHIFT 11 | |
135 | #define OMAP24XX_ST_GPT9_MASK (1 << 11) | |
136 | #define OMAP24XX_ST_GPT8_SHIFT 10 | |
137 | #define OMAP24XX_ST_GPT8_MASK (1 << 10) | |
138 | #define OMAP24XX_ST_GPT7_SHIFT 9 | |
139 | #define OMAP24XX_ST_GPT7_MASK (1 << 9) | |
140 | #define OMAP24XX_ST_GPT6_SHIFT 8 | |
141 | #define OMAP24XX_ST_GPT6_MASK (1 << 8) | |
142 | #define OMAP24XX_ST_GPT5_SHIFT 7 | |
143 | #define OMAP24XX_ST_GPT5_MASK (1 << 7) | |
144 | #define OMAP24XX_ST_GPT4_SHIFT 6 | |
145 | #define OMAP24XX_ST_GPT4_MASK (1 << 6) | |
146 | #define OMAP24XX_ST_GPT3_SHIFT 5 | |
147 | #define OMAP24XX_ST_GPT3_MASK (1 << 5) | |
148 | #define OMAP24XX_ST_GPT2_SHIFT 4 | |
149 | #define OMAP24XX_ST_GPT2_MASK (1 << 4) | |
150 | #define OMAP2420_ST_VLYNQ_SHIFT 3 | |
151 | #define OMAP2420_ST_VLYNQ_MASK (1 << 3) | |
69d88a00 PW |
152 | |
153 | /* CM_IDLEST2_CORE, PM_WKST2_CORE shared bits */ | |
da0747d4 PW |
154 | #define OMAP2430_ST_MDM_INTC_SHIFT 11 |
155 | #define OMAP2430_ST_MDM_INTC_MASK (1 << 11) | |
156 | #define OMAP2430_ST_GPIO5_SHIFT 10 | |
157 | #define OMAP2430_ST_GPIO5_MASK (1 << 10) | |
158 | #define OMAP2430_ST_MCSPI3_SHIFT 9 | |
159 | #define OMAP2430_ST_MCSPI3_MASK (1 << 9) | |
160 | #define OMAP2430_ST_MMCHS2_SHIFT 8 | |
161 | #define OMAP2430_ST_MMCHS2_MASK (1 << 8) | |
162 | #define OMAP2430_ST_MMCHS1_SHIFT 7 | |
163 | #define OMAP2430_ST_MMCHS1_MASK (1 << 7) | |
164 | #define OMAP2430_ST_USBHS_SHIFT 6 | |
165 | #define OMAP2430_ST_USBHS_MASK (1 << 6) | |
166 | #define OMAP24XX_ST_UART3_SHIFT 2 | |
167 | #define OMAP24XX_ST_UART3_MASK (1 << 2) | |
168 | #define OMAP24XX_ST_USB_SHIFT 0 | |
169 | #define OMAP24XX_ST_USB_MASK (1 << 0) | |
69d88a00 PW |
170 | |
171 | /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ | |
172 | #define OMAP24XX_EN_GPIOS_SHIFT 2 | |
2fd0f75c | 173 | #define OMAP24XX_EN_GPIOS_MASK (1 << 2) |
69d88a00 | 174 | #define OMAP24XX_EN_GPT1_SHIFT 0 |
2fd0f75c | 175 | #define OMAP24XX_EN_GPT1_MASK (1 << 0) |
69d88a00 PW |
176 | |
177 | /* PM_WKST_WKUP, CM_IDLEST_WKUP shared bits */ | |
c2015dc8 PW |
178 | #define OMAP24XX_ST_GPIOS_SHIFT 2 |
179 | #define OMAP24XX_ST_GPIOS_MASK (1 << 2) | |
444b3df6 VH |
180 | #define OMAP24XX_ST_32KSYNC_SHIFT 1 |
181 | #define OMAP24XX_ST_32KSYNC_MASK (1 << 1) | |
c2015dc8 PW |
182 | #define OMAP24XX_ST_GPT1_SHIFT 0 |
183 | #define OMAP24XX_ST_GPT1_MASK (1 << 0) | |
69d88a00 PW |
184 | |
185 | /* CM_IDLEST_MDM and PM_WKST_MDM shared bits */ | |
c2015dc8 PW |
186 | #define OMAP2430_ST_MDM_SHIFT 0 |
187 | #define OMAP2430_ST_MDM_MASK (1 << 0) | |
69d88a00 PW |
188 | |
189 | ||
190 | /* 3430 register bits shared between CM & PRM registers */ | |
191 | ||
192 | /* CM_REVISION, PRM_REVISION shared bits */ | |
193 | #define OMAP3430_REV_SHIFT 0 | |
194 | #define OMAP3430_REV_MASK (0xff << 0) | |
195 | ||
196 | /* CM_SYSCONFIG, PRM_SYSCONFIG shared bits */ | |
2fd0f75c | 197 | #define OMAP3430_AUTOIDLE_MASK (1 << 0) |
69d88a00 PW |
198 | |
199 | /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ | |
b163605e PW |
200 | #define OMAP3430_EN_MMC3_MASK (1 << 30) |
201 | #define OMAP3430_EN_MMC3_SHIFT 30 | |
2fd0f75c | 202 | #define OMAP3430_EN_MMC2_MASK (1 << 25) |
69d88a00 | 203 | #define OMAP3430_EN_MMC2_SHIFT 25 |
2fd0f75c | 204 | #define OMAP3430_EN_MMC1_MASK (1 << 24) |
69d88a00 | 205 | #define OMAP3430_EN_MMC1_SHIFT 24 |
4bf90f65 KM |
206 | #define OMAP3430_EN_UART4_MASK (1 << 23) |
207 | #define OMAP3430_EN_UART4_SHIFT 23 | |
2fd0f75c | 208 | #define OMAP3430_EN_MCSPI4_MASK (1 << 21) |
69d88a00 | 209 | #define OMAP3430_EN_MCSPI4_SHIFT 21 |
2fd0f75c | 210 | #define OMAP3430_EN_MCSPI3_MASK (1 << 20) |
69d88a00 | 211 | #define OMAP3430_EN_MCSPI3_SHIFT 20 |
2fd0f75c | 212 | #define OMAP3430_EN_MCSPI2_MASK (1 << 19) |
69d88a00 | 213 | #define OMAP3430_EN_MCSPI2_SHIFT 19 |
2fd0f75c | 214 | #define OMAP3430_EN_MCSPI1_MASK (1 << 18) |
69d88a00 | 215 | #define OMAP3430_EN_MCSPI1_SHIFT 18 |
2fd0f75c | 216 | #define OMAP3430_EN_I2C3_MASK (1 << 17) |
69d88a00 | 217 | #define OMAP3430_EN_I2C3_SHIFT 17 |
2fd0f75c | 218 | #define OMAP3430_EN_I2C2_MASK (1 << 16) |
69d88a00 | 219 | #define OMAP3430_EN_I2C2_SHIFT 16 |
2fd0f75c | 220 | #define OMAP3430_EN_I2C1_MASK (1 << 15) |
69d88a00 | 221 | #define OMAP3430_EN_I2C1_SHIFT 15 |
2fd0f75c | 222 | #define OMAP3430_EN_UART2_MASK (1 << 14) |
69d88a00 | 223 | #define OMAP3430_EN_UART2_SHIFT 14 |
2fd0f75c | 224 | #define OMAP3430_EN_UART1_MASK (1 << 13) |
69d88a00 | 225 | #define OMAP3430_EN_UART1_SHIFT 13 |
2fd0f75c | 226 | #define OMAP3430_EN_GPT11_MASK (1 << 12) |
69d88a00 | 227 | #define OMAP3430_EN_GPT11_SHIFT 12 |
2fd0f75c | 228 | #define OMAP3430_EN_GPT10_MASK (1 << 11) |
69d88a00 | 229 | #define OMAP3430_EN_GPT10_SHIFT 11 |
2fd0f75c | 230 | #define OMAP3430_EN_MCBSP5_MASK (1 << 10) |
69d88a00 | 231 | #define OMAP3430_EN_MCBSP5_SHIFT 10 |
2fd0f75c | 232 | #define OMAP3430_EN_MCBSP1_MASK (1 << 9) |
69d88a00 | 233 | #define OMAP3430_EN_MCBSP1_SHIFT 9 |
2fd0f75c | 234 | #define OMAP3430_EN_FSHOSTUSB_MASK (1 << 5) |
69d88a00 | 235 | #define OMAP3430_EN_FSHOSTUSB_SHIFT 5 |
2fd0f75c | 236 | #define OMAP3430_EN_D2D_MASK (1 << 3) |
69d88a00 PW |
237 | #define OMAP3430_EN_D2D_SHIFT 3 |
238 | ||
239 | /* CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */ | |
2fd0f75c PW |
240 | #define OMAP3430_EN_HSOTGUSB_MASK (1 << 4) |
241 | #define OMAP3430_EN_HSOTGUSB_SHIFT 4 | |
69d88a00 PW |
242 | |
243 | /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */ | |
b163605e PW |
244 | #define OMAP3430_ST_MMC3_SHIFT 30 |
245 | #define OMAP3430_ST_MMC3_MASK (1 << 30) | |
da0747d4 PW |
246 | #define OMAP3430_ST_MMC2_SHIFT 25 |
247 | #define OMAP3430_ST_MMC2_MASK (1 << 25) | |
248 | #define OMAP3430_ST_MMC1_SHIFT 24 | |
249 | #define OMAP3430_ST_MMC1_MASK (1 << 24) | |
250 | #define OMAP3430_ST_MCSPI4_SHIFT 21 | |
251 | #define OMAP3430_ST_MCSPI4_MASK (1 << 21) | |
252 | #define OMAP3430_ST_MCSPI3_SHIFT 20 | |
253 | #define OMAP3430_ST_MCSPI3_MASK (1 << 20) | |
254 | #define OMAP3430_ST_MCSPI2_SHIFT 19 | |
255 | #define OMAP3430_ST_MCSPI2_MASK (1 << 19) | |
256 | #define OMAP3430_ST_MCSPI1_SHIFT 18 | |
257 | #define OMAP3430_ST_MCSPI1_MASK (1 << 18) | |
258 | #define OMAP3430_ST_I2C3_SHIFT 17 | |
259 | #define OMAP3430_ST_I2C3_MASK (1 << 17) | |
260 | #define OMAP3430_ST_I2C2_SHIFT 16 | |
261 | #define OMAP3430_ST_I2C2_MASK (1 << 16) | |
262 | #define OMAP3430_ST_I2C1_SHIFT 15 | |
263 | #define OMAP3430_ST_I2C1_MASK (1 << 15) | |
264 | #define OMAP3430_ST_UART2_SHIFT 14 | |
265 | #define OMAP3430_ST_UART2_MASK (1 << 14) | |
266 | #define OMAP3430_ST_UART1_SHIFT 13 | |
267 | #define OMAP3430_ST_UART1_MASK (1 << 13) | |
268 | #define OMAP3430_ST_GPT11_SHIFT 12 | |
269 | #define OMAP3430_ST_GPT11_MASK (1 << 12) | |
270 | #define OMAP3430_ST_GPT10_SHIFT 11 | |
271 | #define OMAP3430_ST_GPT10_MASK (1 << 11) | |
272 | #define OMAP3430_ST_MCBSP5_SHIFT 10 | |
273 | #define OMAP3430_ST_MCBSP5_MASK (1 << 10) | |
274 | #define OMAP3430_ST_MCBSP1_SHIFT 9 | |
275 | #define OMAP3430_ST_MCBSP1_MASK (1 << 9) | |
276 | #define OMAP3430ES1_ST_FSHOSTUSB_SHIFT 5 | |
277 | #define OMAP3430ES1_ST_FSHOSTUSB_MASK (1 << 5) | |
278 | #define OMAP3430ES1_ST_HSOTGUSB_SHIFT 4 | |
279 | #define OMAP3430ES1_ST_HSOTGUSB_MASK (1 << 4) | |
280 | #define OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT 5 | |
281 | #define OMAP3430ES2_ST_HSOTGUSB_IDLE_MASK (1 << 5) | |
282 | #define OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT 4 | |
283 | #define OMAP3430ES2_ST_HSOTGUSB_STDBY_MASK (1 << 4) | |
284 | #define OMAP3430_ST_D2D_SHIFT 3 | |
285 | #define OMAP3430_ST_D2D_MASK (1 << 3) | |
69d88a00 PW |
286 | |
287 | /* CM_FCLKEN_WKUP, CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ | |
2fd0f75c | 288 | #define OMAP3430_EN_GPIO1_MASK (1 << 3) |
69d88a00 | 289 | #define OMAP3430_EN_GPIO1_SHIFT 3 |
2fd0f75c | 290 | #define OMAP3430_EN_GPT12_MASK (1 << 1) |
8bd22949 | 291 | #define OMAP3430_EN_GPT12_SHIFT 1 |
2fd0f75c | 292 | #define OMAP3430_EN_GPT1_MASK (1 << 0) |
69d88a00 PW |
293 | #define OMAP3430_EN_GPT1_SHIFT 0 |
294 | ||
295 | /* CM_FCLKEN_WKUP, PM_WKEN_WKUP shared bits */ | |
2fd0f75c | 296 | #define OMAP3430_EN_SR2_MASK (1 << 7) |
69d88a00 | 297 | #define OMAP3430_EN_SR2_SHIFT 7 |
2fd0f75c | 298 | #define OMAP3430_EN_SR1_MASK (1 << 6) |
69d88a00 PW |
299 | #define OMAP3430_EN_SR1_SHIFT 6 |
300 | ||
301 | /* CM_ICLKEN_WKUP, PM_WKEN_WKUP shared bits */ | |
2fd0f75c | 302 | #define OMAP3430_EN_GPT12_MASK (1 << 1) |
69d88a00 PW |
303 | #define OMAP3430_EN_GPT12_SHIFT 1 |
304 | ||
305 | /* CM_IDLEST_WKUP, PM_WKST_WKUP shared bits */ | |
da0747d4 PW |
306 | #define OMAP3430_ST_SR2_SHIFT 7 |
307 | #define OMAP3430_ST_SR2_MASK (1 << 7) | |
308 | #define OMAP3430_ST_SR1_SHIFT 6 | |
309 | #define OMAP3430_ST_SR1_MASK (1 << 6) | |
310 | #define OMAP3430_ST_GPIO1_SHIFT 3 | |
311 | #define OMAP3430_ST_GPIO1_MASK (1 << 3) | |
444b3df6 VH |
312 | #define OMAP3430_ST_32KSYNC_SHIFT 2 |
313 | #define OMAP3430_ST_32KSYNC_MASK (1 << 2) | |
da0747d4 PW |
314 | #define OMAP3430_ST_GPT12_SHIFT 1 |
315 | #define OMAP3430_ST_GPT12_MASK (1 << 1) | |
316 | #define OMAP3430_ST_GPT1_SHIFT 0 | |
317 | #define OMAP3430_ST_GPT1_MASK (1 << 0) | |
69d88a00 PW |
318 | |
319 | /* | |
320 | * CM_SLEEPDEP_GFX, CM_SLEEPDEP_DSS, CM_SLEEPDEP_CAM, | |
321 | * CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_GFX, | |
322 | * PM_WKDEP_DSS, PM_WKDEP_CAM, PM_WKDEP_PER, PM_WKDEP_NEON shared bits | |
323 | */ | |
2fd0f75c | 324 | #define OMAP3430_EN_MPU_MASK (1 << 1) |
69d88a00 PW |
325 | #define OMAP3430_EN_MPU_SHIFT 1 |
326 | ||
327 | /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER shared bits */ | |
046465b7 KH |
328 | |
329 | #define OMAP3630_EN_UART4_MASK (1 << 18) | |
330 | #define OMAP3630_EN_UART4_SHIFT 18 | |
2fd0f75c | 331 | #define OMAP3430_EN_GPIO6_MASK (1 << 17) |
69d88a00 | 332 | #define OMAP3430_EN_GPIO6_SHIFT 17 |
2fd0f75c | 333 | #define OMAP3430_EN_GPIO5_MASK (1 << 16) |
69d88a00 | 334 | #define OMAP3430_EN_GPIO5_SHIFT 16 |
2fd0f75c | 335 | #define OMAP3430_EN_GPIO4_MASK (1 << 15) |
69d88a00 | 336 | #define OMAP3430_EN_GPIO4_SHIFT 15 |
2fd0f75c | 337 | #define OMAP3430_EN_GPIO3_MASK (1 << 14) |
69d88a00 | 338 | #define OMAP3430_EN_GPIO3_SHIFT 14 |
2fd0f75c | 339 | #define OMAP3430_EN_GPIO2_MASK (1 << 13) |
69d88a00 | 340 | #define OMAP3430_EN_GPIO2_SHIFT 13 |
2fd0f75c | 341 | #define OMAP3430_EN_UART3_MASK (1 << 11) |
69d88a00 | 342 | #define OMAP3430_EN_UART3_SHIFT 11 |
2fd0f75c | 343 | #define OMAP3430_EN_GPT9_MASK (1 << 10) |
69d88a00 | 344 | #define OMAP3430_EN_GPT9_SHIFT 10 |
2fd0f75c | 345 | #define OMAP3430_EN_GPT8_MASK (1 << 9) |
69d88a00 | 346 | #define OMAP3430_EN_GPT8_SHIFT 9 |
2fd0f75c | 347 | #define OMAP3430_EN_GPT7_MASK (1 << 8) |
69d88a00 | 348 | #define OMAP3430_EN_GPT7_SHIFT 8 |
2fd0f75c | 349 | #define OMAP3430_EN_GPT6_MASK (1 << 7) |
69d88a00 | 350 | #define OMAP3430_EN_GPT6_SHIFT 7 |
2fd0f75c | 351 | #define OMAP3430_EN_GPT5_MASK (1 << 6) |
69d88a00 | 352 | #define OMAP3430_EN_GPT5_SHIFT 6 |
2fd0f75c | 353 | #define OMAP3430_EN_GPT4_MASK (1 << 5) |
69d88a00 | 354 | #define OMAP3430_EN_GPT4_SHIFT 5 |
2fd0f75c | 355 | #define OMAP3430_EN_GPT3_MASK (1 << 4) |
69d88a00 | 356 | #define OMAP3430_EN_GPT3_SHIFT 4 |
2fd0f75c | 357 | #define OMAP3430_EN_GPT2_MASK (1 << 3) |
69d88a00 PW |
358 | #define OMAP3430_EN_GPT2_SHIFT 3 |
359 | ||
360 | /* CM_FCLKEN_PER, CM_ICLKEN_PER, PM_WKEN_PER, PM_WKST_PER shared bits */ | |
361 | /* XXX Possible TI documentation bug: should the PM_WKST_PER EN_* bits | |
362 | * be ST_* bits instead? */ | |
2fd0f75c | 363 | #define OMAP3430_EN_MCBSP4_MASK (1 << 2) |
69d88a00 | 364 | #define OMAP3430_EN_MCBSP4_SHIFT 2 |
2fd0f75c | 365 | #define OMAP3430_EN_MCBSP3_MASK (1 << 1) |
69d88a00 | 366 | #define OMAP3430_EN_MCBSP3_SHIFT 1 |
2fd0f75c | 367 | #define OMAP3430_EN_MCBSP2_MASK (1 << 0) |
69d88a00 PW |
368 | #define OMAP3430_EN_MCBSP2_SHIFT 0 |
369 | ||
370 | /* CM_IDLEST_PER, PM_WKST_PER shared bits */ | |
e5863689 G |
371 | #define OMAP3630_ST_UART4_SHIFT 18 |
372 | #define OMAP3630_ST_UART4_MASK (1 << 18) | |
da0747d4 PW |
373 | #define OMAP3430_ST_GPIO6_SHIFT 17 |
374 | #define OMAP3430_ST_GPIO6_MASK (1 << 17) | |
375 | #define OMAP3430_ST_GPIO5_SHIFT 16 | |
376 | #define OMAP3430_ST_GPIO5_MASK (1 << 16) | |
377 | #define OMAP3430_ST_GPIO4_SHIFT 15 | |
378 | #define OMAP3430_ST_GPIO4_MASK (1 << 15) | |
379 | #define OMAP3430_ST_GPIO3_SHIFT 14 | |
380 | #define OMAP3430_ST_GPIO3_MASK (1 << 14) | |
381 | #define OMAP3430_ST_GPIO2_SHIFT 13 | |
382 | #define OMAP3430_ST_GPIO2_MASK (1 << 13) | |
383 | #define OMAP3430_ST_UART3_SHIFT 11 | |
384 | #define OMAP3430_ST_UART3_MASK (1 << 11) | |
385 | #define OMAP3430_ST_GPT9_SHIFT 10 | |
386 | #define OMAP3430_ST_GPT9_MASK (1 << 10) | |
387 | #define OMAP3430_ST_GPT8_SHIFT 9 | |
388 | #define OMAP3430_ST_GPT8_MASK (1 << 9) | |
389 | #define OMAP3430_ST_GPT7_SHIFT 8 | |
390 | #define OMAP3430_ST_GPT7_MASK (1 << 8) | |
391 | #define OMAP3430_ST_GPT6_SHIFT 7 | |
392 | #define OMAP3430_ST_GPT6_MASK (1 << 7) | |
393 | #define OMAP3430_ST_GPT5_SHIFT 6 | |
394 | #define OMAP3430_ST_GPT5_MASK (1 << 6) | |
395 | #define OMAP3430_ST_GPT4_SHIFT 5 | |
396 | #define OMAP3430_ST_GPT4_MASK (1 << 5) | |
397 | #define OMAP3430_ST_GPT3_SHIFT 4 | |
398 | #define OMAP3430_ST_GPT3_MASK (1 << 4) | |
399 | #define OMAP3430_ST_GPT2_SHIFT 3 | |
400 | #define OMAP3430_ST_GPT2_MASK (1 << 3) | |
69d88a00 PW |
401 | |
402 | /* CM_SLEEPDEP_PER, PM_WKDEP_IVA2, PM_WKDEP_MPU, PM_WKDEP_PER shared bits */ | |
ecb24aa1 PW |
403 | #define OMAP3430_EN_CORE_SHIFT 0 |
404 | #define OMAP3430_EN_CORE_MASK (1 << 0) | |
69d88a00 | 405 | |
d198b514 PW |
406 | |
407 | /* | |
408 | * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP | |
409 | * submodule to exit hardreset | |
410 | */ | |
411 | #define MAX_MODULE_HARDRESET_WAIT 10000 | |
412 | ||
59fb659b PW |
413 | # ifndef __ASSEMBLER__ |
414 | extern void __iomem *prm_base; | |
415 | extern void __iomem *cm_base; | |
416 | extern void __iomem *cm2_base; | |
610eb8c2 S |
417 | extern void __iomem *prcm_mpu_base; |
418 | ||
419 | #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_ARCH_OMAP5) | |
420 | extern void omap_prm_base_init(void); | |
421 | extern void omap_cm_base_init(void); | |
422 | #else | |
423 | static inline void omap_prm_base_init(void) | |
424 | { | |
425 | } | |
426 | static inline void omap_cm_base_init(void) | |
427 | { | |
428 | } | |
429 | #endif | |
0a84a91c TK |
430 | |
431 | /** | |
432 | * struct omap_prcm_irq - describes a PRCM interrupt bit | |
433 | * @name: a short name describing the interrupt type, e.g. "wkup" or "io" | |
434 | * @offset: the bit shift of the interrupt inside the IRQ{ENABLE,STATUS} regs | |
435 | * @priority: should this interrupt be handled before @priority=false IRQs? | |
436 | * | |
437 | * Describes interrupt bits inside the PRM_IRQ{ENABLE,STATUS}_MPU* registers. | |
438 | * On systems with multiple PRM MPU IRQ registers, the bitfields read from | |
439 | * the registers are concatenated, so @offset could be > 31 on these systems - | |
440 | * see omap_prm_irq_handler() for more details. I/O ring interrupts should | |
441 | * have @priority set to true. | |
442 | */ | |
443 | struct omap_prcm_irq { | |
444 | const char *name; | |
445 | unsigned int offset; | |
446 | bool priority; | |
447 | }; | |
448 | ||
449 | /** | |
450 | * struct omap_prcm_irq_setup - PRCM interrupt controller details | |
451 | * @ack: PRM register offset for the first PRM_IRQSTATUS_MPU register | |
452 | * @mask: PRM register offset for the first PRM_IRQENABLE_MPU register | |
453 | * @nr_regs: number of PRM_IRQ{STATUS,ENABLE}_MPU* registers | |
454 | * @nr_irqs: number of entries in the @irqs array | |
455 | * @irqs: ptr to an array of PRCM interrupt bits (see @nr_irqs) | |
456 | * @irq: MPU IRQ asserted when a PRCM interrupt arrives | |
457 | * @read_pending_irqs: fn ptr to determine if any PRCM IRQs are pending | |
458 | * @ocp_barrier: fn ptr to force buffered PRM writes to complete | |
91285b6f TK |
459 | * @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs |
460 | * @restore_irqen: fn ptr to save and clear IRQENABLE regs | |
461 | * @saved_mask: IRQENABLE regs are saved here during suspend | |
0a84a91c TK |
462 | * @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true |
463 | * @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init | |
91285b6f TK |
464 | * @suspended: set to true after Linux suspend code has called our ->prepare() |
465 | * @suspend_save_flag: set to true after IRQ masks have been saved and disabled | |
0a84a91c | 466 | * |
91285b6f TK |
467 | * @saved_mask, @priority_mask, @base_irq, @suspended, and |
468 | * @suspend_save_flag are populated dynamically, and are not to be | |
0a84a91c TK |
469 | * specified in static initializers. |
470 | */ | |
471 | struct omap_prcm_irq_setup { | |
472 | u16 ack; | |
473 | u16 mask; | |
474 | u8 nr_regs; | |
475 | u8 nr_irqs; | |
476 | const struct omap_prcm_irq *irqs; | |
477 | int irq; | |
478 | void (*read_pending_irqs)(unsigned long *events); | |
479 | void (*ocp_barrier)(void); | |
91285b6f TK |
480 | void (*save_and_clear_irqen)(u32 *saved_mask); |
481 | void (*restore_irqen)(u32 *saved_mask); | |
482 | u32 *saved_mask; | |
0a84a91c TK |
483 | u32 *priority_mask; |
484 | int base_irq; | |
91285b6f TK |
485 | bool suspended; |
486 | bool suspend_save_flag; | |
0a84a91c TK |
487 | }; |
488 | ||
489 | /* OMAP_PRCM_IRQ: convenience macro for creating struct omap_prcm_irq records */ | |
490 | #define OMAP_PRCM_IRQ(_name, _offset, _priority) { \ | |
491 | .name = _name, \ | |
492 | .offset = _offset, \ | |
493 | .priority = _priority \ | |
494 | } | |
495 | ||
496 | extern void omap_prcm_irq_cleanup(void); | |
497 | extern int omap_prcm_register_chain_handler( | |
498 | struct omap_prcm_irq_setup *irq_setup); | |
499 | extern int omap_prcm_event_to_irq(const char *event); | |
91285b6f TK |
500 | extern void omap_prcm_irq_prepare(void); |
501 | extern void omap_prcm_irq_complete(void); | |
0a84a91c | 502 | |
59fb659b PW |
503 | # endif |
504 | ||
69d88a00 PW |
505 | #endif |
506 |