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OMAP: omap_device: track latency in nanoseconds
[deliverable/linux.git] / arch / arm / mach-omap2 / prcm.c
CommitLineData
b824efae
TL		 1/*
2 * linux/arch/arm/mach-omap2/prcm.c
3 *
4 * OMAP 24xx Power Reset and Clock Management (PRCM) functions
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 *
c171a258
RN		 10 * Copyright (C) 2007 Texas Instruments, Inc.
11 * Rajendra Nayak <rnayak@ti.com>
12 *
b824efae
TL		 13 * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
b824efae
TL		 19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/clk.h>
a58caad1 22#include <linux/io.h>
72350b29 23#include <linux/delay.h>
b824efae 24
ce491cf8
TL		 25#include <plat/common.h>
26#include <plat/prcm.h>
c171a258
RN		 27#include <plat/irqs.h>
28#include <plat/control.h>
44595982 29
a58caad1 30#include "clock.h"
c171a258 31#include "cm.h"
44595982
PW		 32#include "prm.h"
33#include "prm-regbits-24xx.h"
b824efae 34
a58caad1
TL		 35static void __iomem *prm_base;
36static void __iomem *cm_base;
37
72350b29
PW		 38#define MAX_MODULE_ENABLE_WAIT 100000
39
c171a258
RN		 40struct omap3_prcm_regs {
41 u32 control_padconf_sys_nirq;
133464dc 42 u32 iva2_cm_clksel1;
c171a258
RN		 43 u32 iva2_cm_clksel2;
44 u32 cm_sysconfig;
45 u32 sgx_cm_clksel;
46 u32 wkup_cm_clksel;
47 u32 dss_cm_clksel;
48 u32 cam_cm_clksel;
49 u32 per_cm_clksel;
50 u32 emu_cm_clksel;
51 u32 emu_cm_clkstctrl;
52 u32 pll_cm_autoidle2;
53 u32 pll_cm_clksel4;
54 u32 pll_cm_clksel5;
55 u32 pll_cm_clken;
56 u32 pll_cm_clken2;
57 u32 cm_polctrl;
58 u32 iva2_cm_fclken;
59 u32 iva2_cm_clken_pll;
60 u32 core_cm_fclken1;
61 u32 core_cm_fclken3;
62 u32 sgx_cm_fclken;
63 u32 wkup_cm_fclken;
64 u32 dss_cm_fclken;
65 u32 cam_cm_fclken;
66 u32 per_cm_fclken;
67 u32 usbhost_cm_fclken;
68 u32 core_cm_iclken1;
69 u32 core_cm_iclken2;
70 u32 core_cm_iclken3;
71 u32 sgx_cm_iclken;
72 u32 wkup_cm_iclken;
73 u32 dss_cm_iclken;
74 u32 cam_cm_iclken;
75 u32 per_cm_iclken;
76 u32 usbhost_cm_iclken;
77 u32 iva2_cm_autiidle2;
78 u32 mpu_cm_autoidle2;
79 u32 pll_cm_autoidle;
80 u32 iva2_cm_clkstctrl;
81 u32 mpu_cm_clkstctrl;
82 u32 core_cm_clkstctrl;
83 u32 sgx_cm_clkstctrl;
84 u32 dss_cm_clkstctrl;
85 u32 cam_cm_clkstctrl;
86 u32 per_cm_clkstctrl;
87 u32 neon_cm_clkstctrl;
88 u32 usbhost_cm_clkstctrl;
89 u32 core_cm_autoidle1;
90 u32 core_cm_autoidle2;
91 u32 core_cm_autoidle3;
92 u32 wkup_cm_autoidle;
93 u32 dss_cm_autoidle;
94 u32 cam_cm_autoidle;
95 u32 per_cm_autoidle;
96 u32 usbhost_cm_autoidle;
97 u32 sgx_cm_sleepdep;
98 u32 dss_cm_sleepdep;
99 u32 cam_cm_sleepdep;
100 u32 per_cm_sleepdep;
101 u32 usbhost_cm_sleepdep;
102 u32 cm_clkout_ctrl;
103 u32 prm_clkout_ctrl;
104 u32 sgx_pm_wkdep;
105 u32 dss_pm_wkdep;
106 u32 cam_pm_wkdep;
107 u32 per_pm_wkdep;
108 u32 neon_pm_wkdep;
109 u32 usbhost_pm_wkdep;
110 u32 core_pm_mpugrpsel1;
111 u32 iva2_pm_ivagrpsel1;
112 u32 core_pm_mpugrpsel3;
113 u32 core_pm_ivagrpsel3;
114 u32 wkup_pm_mpugrpsel;
115 u32 wkup_pm_ivagrpsel;
116 u32 per_pm_mpugrpsel;
117 u32 per_pm_ivagrpsel;
118 u32 wkup_pm_wken;
119};
120
121struct omap3_prcm_regs prcm_context;
122
b824efae
TL		 123u32 omap_prcm_get_reset_sources(void)
124{
ff00fcc9 125 /* XXX This presumably needs modification for 34XX */
44595982 126 return prm_read_mod_reg(WKUP_MOD, RM_RSTST) & 0x7f;
b824efae
TL		 127}
128EXPORT_SYMBOL(omap_prcm_get_reset_sources);
129
130/* Resets clock rates and reboots the system. Only called from system.h */
131void omap_prcm_arch_reset(char mode)
132{
ff00fcc9 133 s16 prcm_offs;
ae78dcf7 134 omap2_clk_prepare_for_reboot();
44595982 135
ff00fcc9
TL		 136 if (cpu_is_omap24xx())
137 prcm_offs = WKUP_MOD;
692ec4ab
JY		 138 else if (cpu_is_omap34xx()) {
139 u32 l;
140
ff00fcc9 141 prcm_offs = OMAP3430_GR_MOD;
692ec4ab
JY		 142 l = ('B' << 24) | ('M' << 16) | mode;
143 /* Reserve the first word in scratchpad for communicating
144 * with the boot ROM. A pointer to a data structure
145 * describing the boot process can be stored there,
146 * cf. OMAP34xx TRM, Initialization / Software Booting
147 * Configuration. */
148 omap_writel(l, OMAP343X_SCRATCHPAD + 4);
149 } else
ff00fcc9
TL		 150 WARN_ON(1);
151
152 prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL);
b824efae 153}
a58caad1
TL		 154
155static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg)
156{
157 BUG_ON(!base);
158 return __raw_readl(base + module + reg);
159}
160
161static inline void __omap_prcm_write(u32 value, void __iomem *base,
162 s16 module, u16 reg)
163{
164 BUG_ON(!base);
165 __raw_writel(value, base + module + reg);
166}
167
168/* Read a register in a PRM module */
169u32 prm_read_mod_reg(s16 module, u16 idx)
170{
171 return __omap_prcm_read(prm_base, module, idx);
172}
a58caad1
TL		 173
174/* Write into a register in a PRM module */
175void prm_write_mod_reg(u32 val, s16 module, u16 idx)
176{
177 __omap_prcm_write(val, prm_base, module, idx);
178}
a58caad1 179
ff00fcc9
TL		 180/* Read-modify-write a register in a PRM module. Caller must lock */
181u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
182{
183 u32 v;
184
185 v = prm_read_mod_reg(module, idx);
186 v &= ~mask;
187 v |= bits;
188 prm_write_mod_reg(v, module, idx);
189
190 return v;
191}
ff00fcc9 192
a58caad1
TL		 193/* Read a register in a CM module */
194u32 cm_read_mod_reg(s16 module, u16 idx)
195{
196 return __omap_prcm_read(cm_base, module, idx);
197}
a58caad1
TL		 198
199/* Write into a register in a CM module */
200void cm_write_mod_reg(u32 val, s16 module, u16 idx)
201{
202 __omap_prcm_write(val, cm_base, module, idx);
203}
a58caad1 204
ff00fcc9
TL		 205/* Read-modify-write a register in a CM module. Caller must lock */
206u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
207{
208 u32 v;
209
210 v = cm_read_mod_reg(module, idx);
211 v &= ~mask;
212 v |= bits;
213 cm_write_mod_reg(v, module, idx);
214
215 return v;
216}
ff00fcc9 217
72350b29
PW		 218/**
219 * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
220 * @reg: physical address of module IDLEST register
221 * @mask: value to mask against to determine if the module is active
222 * @name: name of the clock (for printk)
223 *
224 * Returns 1 if the module indicated readiness in time, or 0 if it
225 * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
226 */
227int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name)
228{
229 int i = 0;
230 int ena = 0;
231
232 /*
233 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
234 * 34xx reverses this, just to keep us on our toes
235 */
236 if (cpu_is_omap24xx())
237 ena = mask;
238 else if (cpu_is_omap34xx())
239 ena = 0;
240 else
241 BUG();
242
243 /* Wait for lock */
6f8b7ff5
PW		 244 omap_test_timeout(((__raw_readl(reg) & mask) == ena),
245 MAX_MODULE_ENABLE_WAIT, i);
72350b29
PW		 246
247 if (i < MAX_MODULE_ENABLE_WAIT)
248 pr_debug("cm: Module associated with clock %s ready after %d "
249 "loops\n", name, i);
250 else
251 pr_err("cm: Module associated with clock %s didn't enable in "
252 "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
253
254 return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
255};
256
a58caad1
TL		 257void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
258{
259 prm_base = omap2_globals->prm;
260 cm_base = omap2_globals->cm;
261}
c171a258
RN		 262
263#ifdef CONFIG_ARCH_OMAP3
264void omap3_prcm_save_context(void)
265{
266 prcm_context.control_padconf_sys_nirq =
267 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
133464dc
JH		 268 prcm_context.iva2_cm_clksel1 =
269 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
c171a258
RN		 270 prcm_context.iva2_cm_clksel2 =
271 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
272 prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
273 prcm_context.sgx_cm_clksel =
274 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
275 prcm_context.wkup_cm_clksel = cm_read_mod_reg(WKUP_MOD, CM_CLKSEL);
276 prcm_context.dss_cm_clksel =
277 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
278 prcm_context.cam_cm_clksel =
279 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
280 prcm_context.per_cm_clksel =
281 cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
282 prcm_context.emu_cm_clksel =
283 cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
284 prcm_context.emu_cm_clkstctrl =
285 cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSTCTRL);
286 prcm_context.pll_cm_autoidle2 =
287 cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
288 prcm_context.pll_cm_clksel4 =
289 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
290 prcm_context.pll_cm_clksel5 =
291 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
292 prcm_context.pll_cm_clken =
293 cm_read_mod_reg(PLL_MOD, CM_CLKEN);
294 prcm_context.pll_cm_clken2 =
295 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
296 prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
297 prcm_context.iva2_cm_fclken =
298 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
299 prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD,
300 OMAP3430_CM_CLKEN_PLL);
301 prcm_context.core_cm_fclken1 =
302 cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
303 prcm_context.core_cm_fclken3 =
304 cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
305 prcm_context.sgx_cm_fclken =
306 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
307 prcm_context.wkup_cm_fclken =
308 cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
309 prcm_context.dss_cm_fclken =
310 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
311 prcm_context.cam_cm_fclken =
312 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
313 prcm_context.per_cm_fclken =
314 cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
315 prcm_context.usbhost_cm_fclken =
316 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
317 prcm_context.core_cm_iclken1 =
318 cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
319 prcm_context.core_cm_iclken2 =
320 cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
321 prcm_context.core_cm_iclken3 =
322 cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
323 prcm_context.sgx_cm_iclken =
324 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
325 prcm_context.wkup_cm_iclken =
326 cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
327 prcm_context.dss_cm_iclken =
328 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
329 prcm_context.cam_cm_iclken =
330 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
331 prcm_context.per_cm_iclken =
332 cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
333 prcm_context.usbhost_cm_iclken =
334 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
335 prcm_context.iva2_cm_autiidle2 =
336 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
337 prcm_context.mpu_cm_autoidle2 =
338 cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
339 prcm_context.pll_cm_autoidle =
340 cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
341 prcm_context.iva2_cm_clkstctrl =
342 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSTCTRL);
343 prcm_context.mpu_cm_clkstctrl =
344 cm_read_mod_reg(MPU_MOD, CM_CLKSTCTRL);
345 prcm_context.core_cm_clkstctrl =
346 cm_read_mod_reg(CORE_MOD, CM_CLKSTCTRL);
347 prcm_context.sgx_cm_clkstctrl =
348 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSTCTRL);
349 prcm_context.dss_cm_clkstctrl =
350 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSTCTRL);
351 prcm_context.cam_cm_clkstctrl =
352 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSTCTRL);
353 prcm_context.per_cm_clkstctrl =
354 cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSTCTRL);
355 prcm_context.neon_cm_clkstctrl =
356 cm_read_mod_reg(OMAP3430_NEON_MOD, CM_CLKSTCTRL);
357 prcm_context.usbhost_cm_clkstctrl =
358 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
359 prcm_context.core_cm_autoidle1 =
360 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
361 prcm_context.core_cm_autoidle2 =
362 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
363 prcm_context.core_cm_autoidle3 =
364 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
365 prcm_context.wkup_cm_autoidle =
366 cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
367 prcm_context.dss_cm_autoidle =
368 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
369 prcm_context.cam_cm_autoidle =
370 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
371 prcm_context.per_cm_autoidle =
372 cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
373 prcm_context.usbhost_cm_autoidle =
374 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
375 prcm_context.sgx_cm_sleepdep =
376 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP);
377 prcm_context.dss_cm_sleepdep =
378 cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
379 prcm_context.cam_cm_sleepdep =
380 cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
381 prcm_context.per_cm_sleepdep =
382 cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
383 prcm_context.usbhost_cm_sleepdep =
384 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
385 prcm_context.cm_clkout_ctrl = cm_read_mod_reg(OMAP3430_CCR_MOD,
386 OMAP3_CM_CLKOUT_CTRL_OFFSET);
387 prcm_context.prm_clkout_ctrl = prm_read_mod_reg(OMAP3430_CCR_MOD,
388 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
389 prcm_context.sgx_pm_wkdep =
390 prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP);
391 prcm_context.dss_pm_wkdep =
392 prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP);
393 prcm_context.cam_pm_wkdep =
394 prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP);
395 prcm_context.per_pm_wkdep =
396 prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP);
397 prcm_context.neon_pm_wkdep =
398 prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP);
399 prcm_context.usbhost_pm_wkdep =
400 prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
401 prcm_context.core_pm_mpugrpsel1 =
402 prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL1);
403 prcm_context.iva2_pm_ivagrpsel1 =
404 prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1);
405 prcm_context.core_pm_mpugrpsel3 =
406 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_MPUGRPSEL3);
407 prcm_context.core_pm_ivagrpsel3 =
408 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
409 prcm_context.wkup_pm_mpugrpsel =
410 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
411 prcm_context.wkup_pm_ivagrpsel =
412 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
413 prcm_context.per_pm_mpugrpsel =
414 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
415 prcm_context.per_pm_ivagrpsel =
416 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
417 prcm_context.wkup_pm_wken = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
418 return;
419}
420
421void omap3_prcm_restore_context(void)
422{
423 omap_ctrl_writel(prcm_context.control_padconf_sys_nirq,
424 OMAP343X_CONTROL_PADCONF_SYSNIRQ);
133464dc
JH		 425 cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
426 CM_CLKSEL1);
c171a258
RN		 427 cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
428 CM_CLKSEL2);
429 __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
430 cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
431 CM_CLKSEL);
432 cm_write_mod_reg(prcm_context.wkup_cm_clksel, WKUP_MOD, CM_CLKSEL);
433 cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
434 CM_CLKSEL);
435 cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
436 CM_CLKSEL);
437 cm_write_mod_reg(prcm_context.per_cm_clksel, OMAP3430_PER_MOD,
438 CM_CLKSEL);
439 cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
440 CM_CLKSEL1);
441 cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
442 CM_CLKSTCTRL);
443 cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD,
444 CM_AUTOIDLE2);
445 cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD,
446 OMAP3430ES2_CM_CLKSEL4);
447 cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
448 OMAP3430ES2_CM_CLKSEL5);
449 cm_write_mod_reg(prcm_context.pll_cm_clken, PLL_MOD, CM_CLKEN);
450 cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
451 OMAP3430ES2_CM_CLKEN2);
452 __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
453 cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
454 CM_FCLKEN);
455 cm_write_mod_reg(prcm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
456 OMAP3430_CM_CLKEN_PLL);
457 cm_write_mod_reg(prcm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1);
458 cm_write_mod_reg(prcm_context.core_cm_fclken3, CORE_MOD,
459 OMAP3430ES2_CM_FCLKEN3);
460 cm_write_mod_reg(prcm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
461 CM_FCLKEN);
462 cm_write_mod_reg(prcm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
463 cm_write_mod_reg(prcm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
464 CM_FCLKEN);
465 cm_write_mod_reg(prcm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
466 CM_FCLKEN);
467 cm_write_mod_reg(prcm_context.per_cm_fclken, OMAP3430_PER_MOD,
468 CM_FCLKEN);
469 cm_write_mod_reg(prcm_context.usbhost_cm_fclken,
470 OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
471 cm_write_mod_reg(prcm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1);
472 cm_write_mod_reg(prcm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2);
473 cm_write_mod_reg(prcm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3);
474 cm_write_mod_reg(prcm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
475 CM_ICLKEN);
476 cm_write_mod_reg(prcm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
477 cm_write_mod_reg(prcm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
478 CM_ICLKEN);
479 cm_write_mod_reg(prcm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
480 CM_ICLKEN);
481 cm_write_mod_reg(prcm_context.per_cm_iclken, OMAP3430_PER_MOD,
482 CM_ICLKEN);
483 cm_write_mod_reg(prcm_context.usbhost_cm_iclken,
484 OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
485 cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD,
486 CM_AUTOIDLE2);
487 cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
488 cm_write_mod_reg(prcm_context.pll_cm_autoidle, PLL_MOD, CM_AUTOIDLE);
489 cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
490 CM_CLKSTCTRL);
491 cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD, CM_CLKSTCTRL);
492 cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD,
493 CM_CLKSTCTRL);
494 cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
495 CM_CLKSTCTRL);
496 cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
497 CM_CLKSTCTRL);
498 cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
499 CM_CLKSTCTRL);
500 cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
501 CM_CLKSTCTRL);
502 cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
503 CM_CLKSTCTRL);
504 cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl,
505 OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL);
506 cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD,
507 CM_AUTOIDLE1);
508 cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD,
509 CM_AUTOIDLE2);
510 cm_write_mod_reg(prcm_context.core_cm_autoidle3, CORE_MOD,
511 CM_AUTOIDLE3);
512 cm_write_mod_reg(prcm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE);
513 cm_write_mod_reg(prcm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
514 CM_AUTOIDLE);
515 cm_write_mod_reg(prcm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
516 CM_AUTOIDLE);
517 cm_write_mod_reg(prcm_context.per_cm_autoidle, OMAP3430_PER_MOD,
518 CM_AUTOIDLE);
519 cm_write_mod_reg(prcm_context.usbhost_cm_autoidle,
520 OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
521 cm_write_mod_reg(prcm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
522 OMAP3430_CM_SLEEPDEP);
523 cm_write_mod_reg(prcm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
524 OMAP3430_CM_SLEEPDEP);
525 cm_write_mod_reg(prcm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
526 OMAP3430_CM_SLEEPDEP);
527 cm_write_mod_reg(prcm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
528 OMAP3430_CM_SLEEPDEP);
529 cm_write_mod_reg(prcm_context.usbhost_cm_sleepdep,
530 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
531 cm_write_mod_reg(prcm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
532 OMAP3_CM_CLKOUT_CTRL_OFFSET);
533 prm_write_mod_reg(prcm_context.prm_clkout_ctrl, OMAP3430_CCR_MOD,
534 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
535 prm_write_mod_reg(prcm_context.sgx_pm_wkdep, OMAP3430ES2_SGX_MOD,
536 PM_WKDEP);
537 prm_write_mod_reg(prcm_context.dss_pm_wkdep, OMAP3430_DSS_MOD,
538 PM_WKDEP);
539 prm_write_mod_reg(prcm_context.cam_pm_wkdep, OMAP3430_CAM_MOD,
540 PM_WKDEP);
541 prm_write_mod_reg(prcm_context.per_pm_wkdep, OMAP3430_PER_MOD,
542 PM_WKDEP);
543 prm_write_mod_reg(prcm_context.neon_pm_wkdep, OMAP3430_NEON_MOD,
544 PM_WKDEP);
545 prm_write_mod_reg(prcm_context.usbhost_pm_wkdep,
546 OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
547 prm_write_mod_reg(prcm_context.core_pm_mpugrpsel1, CORE_MOD,
548 OMAP3430_PM_MPUGRPSEL1);
549 prm_write_mod_reg(prcm_context.iva2_pm_ivagrpsel1, OMAP3430_IVA2_MOD,
550 OMAP3430_PM_IVAGRPSEL1);
551 prm_write_mod_reg(prcm_context.core_pm_mpugrpsel3, CORE_MOD,
552 OMAP3430ES2_PM_MPUGRPSEL3);
553 prm_write_mod_reg(prcm_context.core_pm_ivagrpsel3, CORE_MOD,
554 OMAP3430ES2_PM_IVAGRPSEL3);
555 prm_write_mod_reg(prcm_context.wkup_pm_mpugrpsel, WKUP_MOD,
556 OMAP3430_PM_MPUGRPSEL);
557 prm_write_mod_reg(prcm_context.wkup_pm_ivagrpsel, WKUP_MOD,
558 OMAP3430_PM_IVAGRPSEL);
559 prm_write_mod_reg(prcm_context.per_pm_mpugrpsel, OMAP3430_PER_MOD,
560 OMAP3430_PM_MPUGRPSEL);
561 prm_write_mod_reg(prcm_context.per_pm_ivagrpsel, OMAP3430_PER_MOD,
562 OMAP3430_PM_IVAGRPSEL);
563 prm_write_mod_reg(prcm_context.wkup_pm_wken, WKUP_MOD, PM_WKEN);
564 return;
565}
566#endif
Linux kernel - Deliverables
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