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ARM: OMAP4 clock domains : Add the missing Clock Domain Structure
[deliverable/linux.git] / arch / arm / mach-omap2 / prcm.c
CommitLineData
b824efae
TL		 1/*
2 * linux/arch/arm/mach-omap2/prcm.c
3 *
4 * OMAP 24xx Power Reset and Clock Management (PRCM) functions
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 *
c171a258
RN		 10 * Copyright (C) 2007 Texas Instruments, Inc.
11 * Rajendra Nayak <rnayak@ti.com>
12 *
b824efae 13 * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
37903009 14 * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com>
b824efae
TL		 15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
b824efae
TL		 20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/clk.h>
a58caad1 23#include <linux/io.h>
72350b29 24#include <linux/delay.h>
b824efae 25
ce491cf8
TL		 26#include <plat/common.h>
27#include <plat/prcm.h>
c171a258
RN		 28#include <plat/irqs.h>
29#include <plat/control.h>
44595982 30
a58caad1 31#include "clock.h"
c171a258 32#include "cm.h"
44595982
PW		 33#include "prm.h"
34#include "prm-regbits-24xx.h"
b824efae 35
a58caad1
TL		 36static void __iomem *prm_base;
37static void __iomem *cm_base;
9ef89150 38static void __iomem *cm2_base;
a58caad1 39
72350b29
PW		 40#define MAX_MODULE_ENABLE_WAIT 100000
41
c171a258
RN		 42struct omap3_prcm_regs {
43 u32 control_padconf_sys_nirq;
133464dc 44 u32 iva2_cm_clksel1;
c171a258
RN		 45 u32 iva2_cm_clksel2;
46 u32 cm_sysconfig;
47 u32 sgx_cm_clksel;
c171a258
RN		 48 u32 dss_cm_clksel;
49 u32 cam_cm_clksel;
50 u32 per_cm_clksel;
51 u32 emu_cm_clksel;
52 u32 emu_cm_clkstctrl;
53 u32 pll_cm_autoidle2;
54 u32 pll_cm_clksel4;
55 u32 pll_cm_clksel5;
c171a258
RN		 56 u32 pll_cm_clken2;
57 u32 cm_polctrl;
58 u32 iva2_cm_fclken;
59 u32 iva2_cm_clken_pll;
60 u32 core_cm_fclken1;
61 u32 core_cm_fclken3;
62 u32 sgx_cm_fclken;
63 u32 wkup_cm_fclken;
64 u32 dss_cm_fclken;
65 u32 cam_cm_fclken;
66 u32 per_cm_fclken;
67 u32 usbhost_cm_fclken;
68 u32 core_cm_iclken1;
69 u32 core_cm_iclken2;
70 u32 core_cm_iclken3;
71 u32 sgx_cm_iclken;
72 u32 wkup_cm_iclken;
73 u32 dss_cm_iclken;
74 u32 cam_cm_iclken;
75 u32 per_cm_iclken;
76 u32 usbhost_cm_iclken;
77 u32 iva2_cm_autiidle2;
78 u32 mpu_cm_autoidle2;
c171a258
RN		 79 u32 iva2_cm_clkstctrl;
80 u32 mpu_cm_clkstctrl;
81 u32 core_cm_clkstctrl;
82 u32 sgx_cm_clkstctrl;
83 u32 dss_cm_clkstctrl;
84 u32 cam_cm_clkstctrl;
85 u32 per_cm_clkstctrl;
86 u32 neon_cm_clkstctrl;
87 u32 usbhost_cm_clkstctrl;
88 u32 core_cm_autoidle1;
89 u32 core_cm_autoidle2;
90 u32 core_cm_autoidle3;
91 u32 wkup_cm_autoidle;
92 u32 dss_cm_autoidle;
93 u32 cam_cm_autoidle;
94 u32 per_cm_autoidle;
95 u32 usbhost_cm_autoidle;
96 u32 sgx_cm_sleepdep;
97 u32 dss_cm_sleepdep;
98 u32 cam_cm_sleepdep;
99 u32 per_cm_sleepdep;
100 u32 usbhost_cm_sleepdep;
101 u32 cm_clkout_ctrl;
102 u32 prm_clkout_ctrl;
103 u32 sgx_pm_wkdep;
104 u32 dss_pm_wkdep;
105 u32 cam_pm_wkdep;
106 u32 per_pm_wkdep;
107 u32 neon_pm_wkdep;
108 u32 usbhost_pm_wkdep;
109 u32 core_pm_mpugrpsel1;
110 u32 iva2_pm_ivagrpsel1;
111 u32 core_pm_mpugrpsel3;
112 u32 core_pm_ivagrpsel3;
113 u32 wkup_pm_mpugrpsel;
114 u32 wkup_pm_ivagrpsel;
115 u32 per_pm_mpugrpsel;
116 u32 per_pm_ivagrpsel;
117 u32 wkup_pm_wken;
118};
119
120struct omap3_prcm_regs prcm_context;
121
b824efae
TL		 122u32 omap_prcm_get_reset_sources(void)
123{
ff00fcc9 124 /* XXX This presumably needs modification for 34XX */
37903009
AP		 125 if (cpu_is_omap24xx() | cpu_is_omap34xx())
126 return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
127 if (cpu_is_omap44xx())
128 return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
b824efae
TL		 129}
130EXPORT_SYMBOL(omap_prcm_get_reset_sources);
131
132/* Resets clock rates and reboots the system. Only called from system.h */
133void omap_prcm_arch_reset(char mode)
134{
ff00fcc9 135 s16 prcm_offs;
ae78dcf7 136 omap2_clk_prepare_for_reboot();
44595982 137
ff00fcc9
TL		 138 if (cpu_is_omap24xx())
139 prcm_offs = WKUP_MOD;
692ec4ab
JY		 140 else if (cpu_is_omap34xx()) {
141 u32 l;
142
ff00fcc9 143 prcm_offs = OMAP3430_GR_MOD;
692ec4ab
JY		 144 l = ('B' << 24) | ('M' << 16) | mode;
145 /* Reserve the first word in scratchpad for communicating
146 * with the boot ROM. A pointer to a data structure
147 * describing the boot process can be stored there,
148 * cf. OMAP34xx TRM, Initialization / Software Booting
149 * Configuration. */
150 omap_writel(l, OMAP343X_SCRATCHPAD + 4);
37903009
AP		 151 } else if (cpu_is_omap44xx())
152 prcm_offs = OMAP4430_PRM_DEVICE_MOD;
153 else
ff00fcc9
TL		 154 WARN_ON(1);
155
37903009
AP		 156 if (cpu_is_omap24xx() | cpu_is_omap34xx())
157 prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs,
158 OMAP2_RM_RSTCTRL);
159 if (cpu_is_omap44xx())
160 prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs,
161 OMAP4_RM_RSTCTRL);
b824efae 162}
a58caad1
TL		 163
164static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg)
165{
166 BUG_ON(!base);
167 return __raw_readl(base + module + reg);
168}
169
170static inline void __omap_prcm_write(u32 value, void __iomem *base,
171 s16 module, u16 reg)
172{
173 BUG_ON(!base);
174 __raw_writel(value, base + module + reg);
175}
176
177/* Read a register in a PRM module */
178u32 prm_read_mod_reg(s16 module, u16 idx)
179{
180 return __omap_prcm_read(prm_base, module, idx);
181}
a58caad1
TL		 182
183/* Write into a register in a PRM module */
184void prm_write_mod_reg(u32 val, s16 module, u16 idx)
185{
186 __omap_prcm_write(val, prm_base, module, idx);
187}
a58caad1 188
ff00fcc9
TL		 189/* Read-modify-write a register in a PRM module. Caller must lock */
190u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
191{
192 u32 v;
193
194 v = prm_read_mod_reg(module, idx);
195 v &= ~mask;
196 v |= bits;
197 prm_write_mod_reg(v, module, idx);
198
199 return v;
200}
ff00fcc9 201
a58caad1
TL		 202/* Read a register in a CM module */
203u32 cm_read_mod_reg(s16 module, u16 idx)
204{
205 return __omap_prcm_read(cm_base, module, idx);
206}
a58caad1
TL		 207
208/* Write into a register in a CM module */
209void cm_write_mod_reg(u32 val, s16 module, u16 idx)
210{
211 __omap_prcm_write(val, cm_base, module, idx);
212}
a58caad1 213
ff00fcc9
TL		 214/* Read-modify-write a register in a CM module. Caller must lock */
215u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
216{
217 u32 v;
218
219 v = cm_read_mod_reg(module, idx);
220 v &= ~mask;
221 v |= bits;
222 cm_write_mod_reg(v, module, idx);
223
224 return v;
225}
ff00fcc9 226
72350b29
PW		 227/**
228 * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
229 * @reg: physical address of module IDLEST register
230 * @mask: value to mask against to determine if the module is active
231 * @name: name of the clock (for printk)
232 *
233 * Returns 1 if the module indicated readiness in time, or 0 if it
234 * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
235 */
236int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, const char *name)
237{
238 int i = 0;
239 int ena = 0;
240
241 /*
242 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
243 * 34xx reverses this, just to keep us on our toes
244 */
245 if (cpu_is_omap24xx())
246 ena = mask;
247 else if (cpu_is_omap34xx())
248 ena = 0;
249 else
250 BUG();
251
252 /* Wait for lock */
6f8b7ff5
PW		 253 omap_test_timeout(((__raw_readl(reg) & mask) == ena),
254 MAX_MODULE_ENABLE_WAIT, i);
72350b29
PW		 255
256 if (i < MAX_MODULE_ENABLE_WAIT)
257 pr_debug("cm: Module associated with clock %s ready after %d "
258 "loops\n", name, i);
259 else
260 pr_err("cm: Module associated with clock %s didn't enable in "
261 "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
262
263 return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
264};
265
a58caad1
TL		 266void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
267{
268 prm_base = omap2_globals->prm;
269 cm_base = omap2_globals->cm;
9ef89150 270 cm2_base = omap2_globals->cm2;
a58caad1 271}
c171a258
RN		 272
273#ifdef CONFIG_ARCH_OMAP3
274void omap3_prcm_save_context(void)
275{
276 prcm_context.control_padconf_sys_nirq =
277 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
133464dc
JH		 278 prcm_context.iva2_cm_clksel1 =
279 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
c171a258
RN		 280 prcm_context.iva2_cm_clksel2 =
281 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
282 prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
283 prcm_context.sgx_cm_clksel =
284 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
c171a258
RN		 285 prcm_context.dss_cm_clksel =
286 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
287 prcm_context.cam_cm_clksel =
288 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
289 prcm_context.per_cm_clksel =
290 cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
291 prcm_context.emu_cm_clksel =
292 cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
293 prcm_context.emu_cm_clkstctrl =
84c0c39a 294 cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
c171a258
RN		 295 prcm_context.pll_cm_autoidle2 =
296 cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
297 prcm_context.pll_cm_clksel4 =
298 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
299 prcm_context.pll_cm_clksel5 =
300 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
c171a258
RN		 301 prcm_context.pll_cm_clken2 =
302 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
303 prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
304 prcm_context.iva2_cm_fclken =
305 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
306 prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD,
307 OMAP3430_CM_CLKEN_PLL);
308 prcm_context.core_cm_fclken1 =
309 cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
310 prcm_context.core_cm_fclken3 =
311 cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
312 prcm_context.sgx_cm_fclken =
313 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
314 prcm_context.wkup_cm_fclken =
315 cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
316 prcm_context.dss_cm_fclken =
317 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
318 prcm_context.cam_cm_fclken =
319 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
320 prcm_context.per_cm_fclken =
321 cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
322 prcm_context.usbhost_cm_fclken =
323 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
324 prcm_context.core_cm_iclken1 =
325 cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
326 prcm_context.core_cm_iclken2 =
327 cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
328 prcm_context.core_cm_iclken3 =
329 cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
330 prcm_context.sgx_cm_iclken =
331 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
332 prcm_context.wkup_cm_iclken =
333 cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
334 prcm_context.dss_cm_iclken =
335 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
336 prcm_context.cam_cm_iclken =
337 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
338 prcm_context.per_cm_iclken =
339 cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
340 prcm_context.usbhost_cm_iclken =
341 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
342 prcm_context.iva2_cm_autiidle2 =
343 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
344 prcm_context.mpu_cm_autoidle2 =
345 cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
c171a258 346 prcm_context.iva2_cm_clkstctrl =
84c0c39a 347 cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
c171a258 348 prcm_context.mpu_cm_clkstctrl =
84c0c39a 349 cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
c171a258 350 prcm_context.core_cm_clkstctrl =
84c0c39a 351 cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
c171a258 352 prcm_context.sgx_cm_clkstctrl =
84c0c39a
AP		 353 cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
354 OMAP2_CM_CLKSTCTRL);
c171a258 355 prcm_context.dss_cm_clkstctrl =
84c0c39a 356 cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
c171a258 357 prcm_context.cam_cm_clkstctrl =
84c0c39a 358 cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
c171a258 359 prcm_context.per_cm_clkstctrl =
84c0c39a 360 cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
c171a258 361 prcm_context.neon_cm_clkstctrl =
84c0c39a 362 cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
c171a258 363 prcm_context.usbhost_cm_clkstctrl =
84c0c39a
AP		 364 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
365 OMAP2_CM_CLKSTCTRL);
c171a258
RN		 366 prcm_context.core_cm_autoidle1 =
367 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
368 prcm_context.core_cm_autoidle2 =
369 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
370 prcm_context.core_cm_autoidle3 =
371 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
372 prcm_context.wkup_cm_autoidle =
373 cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
374 prcm_context.dss_cm_autoidle =
375 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
376 prcm_context.cam_cm_autoidle =
377 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
378 prcm_context.per_cm_autoidle =
379 cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
380 prcm_context.usbhost_cm_autoidle =
381 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
382 prcm_context.sgx_cm_sleepdep =
383 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP);
384 prcm_context.dss_cm_sleepdep =
385 cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
386 prcm_context.cam_cm_sleepdep =
387 cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
388 prcm_context.per_cm_sleepdep =
389 cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
390 prcm_context.usbhost_cm_sleepdep =
391 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
392 prcm_context.cm_clkout_ctrl = cm_read_mod_reg(OMAP3430_CCR_MOD,
393 OMAP3_CM_CLKOUT_CTRL_OFFSET);
394 prcm_context.prm_clkout_ctrl = prm_read_mod_reg(OMAP3430_CCR_MOD,
395 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
396 prcm_context.sgx_pm_wkdep =
397 prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP);
398 prcm_context.dss_pm_wkdep =
399 prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP);
400 prcm_context.cam_pm_wkdep =
401 prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP);
402 prcm_context.per_pm_wkdep =
403 prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP);
404 prcm_context.neon_pm_wkdep =
405 prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP);
406 prcm_context.usbhost_pm_wkdep =
407 prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
408 prcm_context.core_pm_mpugrpsel1 =
409 prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL1);
410 prcm_context.iva2_pm_ivagrpsel1 =
411 prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1);
412 prcm_context.core_pm_mpugrpsel3 =
413 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_MPUGRPSEL3);
414 prcm_context.core_pm_ivagrpsel3 =
415 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
416 prcm_context.wkup_pm_mpugrpsel =
417 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
418 prcm_context.wkup_pm_ivagrpsel =
419 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
420 prcm_context.per_pm_mpugrpsel =
421 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
422 prcm_context.per_pm_ivagrpsel =
423 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
424 prcm_context.wkup_pm_wken = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
425 return;
426}
427
428void omap3_prcm_restore_context(void)
429{
430 omap_ctrl_writel(prcm_context.control_padconf_sys_nirq,
431 OMAP343X_CONTROL_PADCONF_SYSNIRQ);
133464dc
JH		 432 cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
433 CM_CLKSEL1);
c171a258
RN		 434 cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
435 CM_CLKSEL2);
436 __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
437 cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
438 CM_CLKSEL);
c171a258
RN		 439 cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
440 CM_CLKSEL);
441 cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
442 CM_CLKSEL);
443 cm_write_mod_reg(prcm_context.per_cm_clksel, OMAP3430_PER_MOD,
444 CM_CLKSEL);
445 cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
446 CM_CLKSEL1);
447 cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
84c0c39a 448 OMAP2_CM_CLKSTCTRL);
c171a258
RN		 449 cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD,
450 CM_AUTOIDLE2);
451 cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD,
452 OMAP3430ES2_CM_CLKSEL4);
453 cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
454 OMAP3430ES2_CM_CLKSEL5);
c171a258
RN		 455 cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
456 OMAP3430ES2_CM_CLKEN2);
457 __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
458 cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
459 CM_FCLKEN);
460 cm_write_mod_reg(prcm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
461 OMAP3430_CM_CLKEN_PLL);
462 cm_write_mod_reg(prcm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1);
463 cm_write_mod_reg(prcm_context.core_cm_fclken3, CORE_MOD,
464 OMAP3430ES2_CM_FCLKEN3);
465 cm_write_mod_reg(prcm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
466 CM_FCLKEN);
467 cm_write_mod_reg(prcm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
468 cm_write_mod_reg(prcm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
469 CM_FCLKEN);
470 cm_write_mod_reg(prcm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
471 CM_FCLKEN);
472 cm_write_mod_reg(prcm_context.per_cm_fclken, OMAP3430_PER_MOD,
473 CM_FCLKEN);
474 cm_write_mod_reg(prcm_context.usbhost_cm_fclken,
475 OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
476 cm_write_mod_reg(prcm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1);
477 cm_write_mod_reg(prcm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2);
478 cm_write_mod_reg(prcm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3);
479 cm_write_mod_reg(prcm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
480 CM_ICLKEN);
481 cm_write_mod_reg(prcm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
482 cm_write_mod_reg(prcm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
483 CM_ICLKEN);
484 cm_write_mod_reg(prcm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
485 CM_ICLKEN);
486 cm_write_mod_reg(prcm_context.per_cm_iclken, OMAP3430_PER_MOD,
487 CM_ICLKEN);
488 cm_write_mod_reg(prcm_context.usbhost_cm_iclken,
489 OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
490 cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD,
491 CM_AUTOIDLE2);
492 cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
c171a258 493 cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
84c0c39a
AP		 494 OMAP2_CM_CLKSTCTRL);
495 cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD,
496 OMAP2_CM_CLKSTCTRL);
c171a258 497 cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD,
84c0c39a 498 OMAP2_CM_CLKSTCTRL);
c171a258 499 cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
84c0c39a 500 OMAP2_CM_CLKSTCTRL);
c171a258 501 cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
84c0c39a 502 OMAP2_CM_CLKSTCTRL);
c171a258 503 cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
84c0c39a 504 OMAP2_CM_CLKSTCTRL);
c171a258 505 cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
84c0c39a 506 OMAP2_CM_CLKSTCTRL);
c171a258 507 cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
84c0c39a 508 OMAP2_CM_CLKSTCTRL);
c171a258 509 cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl,
84c0c39a 510 OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
c171a258
RN		 511 cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD,
512 CM_AUTOIDLE1);
513 cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD,
514 CM_AUTOIDLE2);
515 cm_write_mod_reg(prcm_context.core_cm_autoidle3, CORE_MOD,
516 CM_AUTOIDLE3);
517 cm_write_mod_reg(prcm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE);
518 cm_write_mod_reg(prcm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
519 CM_AUTOIDLE);
520 cm_write_mod_reg(prcm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
521 CM_AUTOIDLE);
522 cm_write_mod_reg(prcm_context.per_cm_autoidle, OMAP3430_PER_MOD,
523 CM_AUTOIDLE);
524 cm_write_mod_reg(prcm_context.usbhost_cm_autoidle,
525 OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
526 cm_write_mod_reg(prcm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
527 OMAP3430_CM_SLEEPDEP);
528 cm_write_mod_reg(prcm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
529 OMAP3430_CM_SLEEPDEP);
530 cm_write_mod_reg(prcm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
531 OMAP3430_CM_SLEEPDEP);
532 cm_write_mod_reg(prcm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
533 OMAP3430_CM_SLEEPDEP);
534 cm_write_mod_reg(prcm_context.usbhost_cm_sleepdep,
535 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
536 cm_write_mod_reg(prcm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
537 OMAP3_CM_CLKOUT_CTRL_OFFSET);
538 prm_write_mod_reg(prcm_context.prm_clkout_ctrl, OMAP3430_CCR_MOD,
539 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
540 prm_write_mod_reg(prcm_context.sgx_pm_wkdep, OMAP3430ES2_SGX_MOD,
541 PM_WKDEP);
542 prm_write_mod_reg(prcm_context.dss_pm_wkdep, OMAP3430_DSS_MOD,
543 PM_WKDEP);
544 prm_write_mod_reg(prcm_context.cam_pm_wkdep, OMAP3430_CAM_MOD,
545 PM_WKDEP);
546 prm_write_mod_reg(prcm_context.per_pm_wkdep, OMAP3430_PER_MOD,
547 PM_WKDEP);
548 prm_write_mod_reg(prcm_context.neon_pm_wkdep, OMAP3430_NEON_MOD,
549 PM_WKDEP);
550 prm_write_mod_reg(prcm_context.usbhost_pm_wkdep,
551 OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
552 prm_write_mod_reg(prcm_context.core_pm_mpugrpsel1, CORE_MOD,
553 OMAP3430_PM_MPUGRPSEL1);
554 prm_write_mod_reg(prcm_context.iva2_pm_ivagrpsel1, OMAP3430_IVA2_MOD,
555 OMAP3430_PM_IVAGRPSEL1);
556 prm_write_mod_reg(prcm_context.core_pm_mpugrpsel3, CORE_MOD,
557 OMAP3430ES2_PM_MPUGRPSEL3);
558 prm_write_mod_reg(prcm_context.core_pm_ivagrpsel3, CORE_MOD,
559 OMAP3430ES2_PM_IVAGRPSEL3);
560 prm_write_mod_reg(prcm_context.wkup_pm_mpugrpsel, WKUP_MOD,
561 OMAP3430_PM_MPUGRPSEL);
562 prm_write_mod_reg(prcm_context.wkup_pm_ivagrpsel, WKUP_MOD,
563 OMAP3430_PM_IVAGRPSEL);
564 prm_write_mod_reg(prcm_context.per_pm_mpugrpsel, OMAP3430_PER_MOD,
565 OMAP3430_PM_MPUGRPSEL);
566 prm_write_mod_reg(prcm_context.per_pm_ivagrpsel, OMAP3430_PER_MOD,
567 OMAP3430_PM_IVAGRPSEL);
568 prm_write_mod_reg(prcm_context.wkup_pm_wken, WKUP_MOD, PM_WKEN);
569 return;
570}
571#endif
Linux kernel - Deliverables
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