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OMAP3 clock: Check return values for clk_get()
[deliverable/linux.git] / arch / arm / mach-omap2 / prcm.c
CommitLineData
b824efae
TL		 1/*
2 * linux/arch/arm/mach-omap2/prcm.c
3 *
4 * OMAP 24xx Power Reset and Clock Management (PRCM) functions
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 *
c171a258
RN		 10 * Copyright (C) 2007 Texas Instruments, Inc.
11 * Rajendra Nayak <rnayak@ti.com>
12 *
b824efae 13 * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
37903009 14 * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com>
b824efae
TL		 15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
b824efae
TL		 20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/clk.h>
a58caad1 23#include <linux/io.h>
72350b29 24#include <linux/delay.h>
b824efae 25
ce491cf8
TL		 26#include <plat/common.h>
27#include <plat/prcm.h>
c171a258
RN		 28#include <plat/irqs.h>
29#include <plat/control.h>
44595982 30
a58caad1 31#include "clock.h"
feec1277 32#include "clock2xxx.h"
c171a258 33#include "cm.h"
44595982
PW		 34#include "prm.h"
35#include "prm-regbits-24xx.h"
b824efae 36
a58caad1
TL		 37static void __iomem *prm_base;
38static void __iomem *cm_base;
9ef89150 39static void __iomem *cm2_base;
a58caad1 40
72350b29
PW		 41#define MAX_MODULE_ENABLE_WAIT 100000
42
c171a258
RN		 43struct omap3_prcm_regs {
44 u32 control_padconf_sys_nirq;
133464dc 45 u32 iva2_cm_clksel1;
c171a258
RN		 46 u32 iva2_cm_clksel2;
47 u32 cm_sysconfig;
48 u32 sgx_cm_clksel;
c171a258
RN		 49 u32 dss_cm_clksel;
50 u32 cam_cm_clksel;
51 u32 per_cm_clksel;
52 u32 emu_cm_clksel;
53 u32 emu_cm_clkstctrl;
54 u32 pll_cm_autoidle2;
55 u32 pll_cm_clksel4;
56 u32 pll_cm_clksel5;
c171a258
RN		 57 u32 pll_cm_clken2;
58 u32 cm_polctrl;
59 u32 iva2_cm_fclken;
60 u32 iva2_cm_clken_pll;
61 u32 core_cm_fclken1;
62 u32 core_cm_fclken3;
63 u32 sgx_cm_fclken;
64 u32 wkup_cm_fclken;
65 u32 dss_cm_fclken;
66 u32 cam_cm_fclken;
67 u32 per_cm_fclken;
68 u32 usbhost_cm_fclken;
69 u32 core_cm_iclken1;
70 u32 core_cm_iclken2;
71 u32 core_cm_iclken3;
72 u32 sgx_cm_iclken;
73 u32 wkup_cm_iclken;
74 u32 dss_cm_iclken;
75 u32 cam_cm_iclken;
76 u32 per_cm_iclken;
77 u32 usbhost_cm_iclken;
78 u32 iva2_cm_autiidle2;
79 u32 mpu_cm_autoidle2;
c171a258
RN		 80 u32 iva2_cm_clkstctrl;
81 u32 mpu_cm_clkstctrl;
82 u32 core_cm_clkstctrl;
83 u32 sgx_cm_clkstctrl;
84 u32 dss_cm_clkstctrl;
85 u32 cam_cm_clkstctrl;
86 u32 per_cm_clkstctrl;
87 u32 neon_cm_clkstctrl;
88 u32 usbhost_cm_clkstctrl;
89 u32 core_cm_autoidle1;
90 u32 core_cm_autoidle2;
91 u32 core_cm_autoidle3;
92 u32 wkup_cm_autoidle;
93 u32 dss_cm_autoidle;
94 u32 cam_cm_autoidle;
95 u32 per_cm_autoidle;
96 u32 usbhost_cm_autoidle;
97 u32 sgx_cm_sleepdep;
98 u32 dss_cm_sleepdep;
99 u32 cam_cm_sleepdep;
100 u32 per_cm_sleepdep;
101 u32 usbhost_cm_sleepdep;
102 u32 cm_clkout_ctrl;
103 u32 prm_clkout_ctrl;
104 u32 sgx_pm_wkdep;
105 u32 dss_pm_wkdep;
106 u32 cam_pm_wkdep;
107 u32 per_pm_wkdep;
108 u32 neon_pm_wkdep;
109 u32 usbhost_pm_wkdep;
110 u32 core_pm_mpugrpsel1;
111 u32 iva2_pm_ivagrpsel1;
112 u32 core_pm_mpugrpsel3;
113 u32 core_pm_ivagrpsel3;
114 u32 wkup_pm_mpugrpsel;
115 u32 wkup_pm_ivagrpsel;
116 u32 per_pm_mpugrpsel;
117 u32 per_pm_ivagrpsel;
118 u32 wkup_pm_wken;
119};
120
121struct omap3_prcm_regs prcm_context;
122
b824efae
TL		 123u32 omap_prcm_get_reset_sources(void)
124{
ff00fcc9 125 /* XXX This presumably needs modification for 34XX */
37903009
AP		 126 if (cpu_is_omap24xx() | cpu_is_omap34xx())
127 return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
128 if (cpu_is_omap44xx())
129 return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
b824efae
TL		 130}
131EXPORT_SYMBOL(omap_prcm_get_reset_sources);
132
133/* Resets clock rates and reboots the system. Only called from system.h */
134void omap_prcm_arch_reset(char mode)
135{
ff00fcc9 136 s16 prcm_offs;
44595982 137
feec1277
PW		 138 if (cpu_is_omap24xx()) {
139 omap2xxx_clk_prepare_for_reboot();
140
ff00fcc9 141 prcm_offs = WKUP_MOD;
feec1277 142 } else if (cpu_is_omap34xx()) {
692ec4ab
JY		 143 u32 l;
144
ff00fcc9 145 prcm_offs = OMAP3430_GR_MOD;
692ec4ab
JY		 146 l = ('B' << 24) | ('M' << 16) | mode;
147 /* Reserve the first word in scratchpad for communicating
148 * with the boot ROM. A pointer to a data structure
149 * describing the boot process can be stored there,
150 * cf. OMAP34xx TRM, Initialization / Software Booting
151 * Configuration. */
152 omap_writel(l, OMAP343X_SCRATCHPAD + 4);
37903009
AP		 153 } else if (cpu_is_omap44xx())
154 prcm_offs = OMAP4430_PRM_DEVICE_MOD;
155 else
ff00fcc9
TL		 156 WARN_ON(1);
157
37903009
AP		 158 if (cpu_is_omap24xx() | cpu_is_omap34xx())
159 prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs,
160 OMAP2_RM_RSTCTRL);
161 if (cpu_is_omap44xx())
162 prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs,
163 OMAP4_RM_RSTCTRL);
b824efae 164}
a58caad1
TL		 165
166static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg)
167{
168 BUG_ON(!base);
169 return __raw_readl(base + module + reg);
170}
171
172static inline void __omap_prcm_write(u32 value, void __iomem *base,
173 s16 module, u16 reg)
174{
175 BUG_ON(!base);
176 __raw_writel(value, base + module + reg);
177}
178
179/* Read a register in a PRM module */
180u32 prm_read_mod_reg(s16 module, u16 idx)
181{
182 return __omap_prcm_read(prm_base, module, idx);
183}
a58caad1
TL		 184
185/* Write into a register in a PRM module */
186void prm_write_mod_reg(u32 val, s16 module, u16 idx)
187{
188 __omap_prcm_write(val, prm_base, module, idx);
189}
a58caad1 190
ff00fcc9
TL		 191/* Read-modify-write a register in a PRM module. Caller must lock */
192u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
193{
194 u32 v;
195
196 v = prm_read_mod_reg(module, idx);
197 v &= ~mask;
198 v |= bits;
199 prm_write_mod_reg(v, module, idx);
200
201 return v;
202}
ff00fcc9 203
55ed9694
PW		 204/* Read a PRM register, AND it, and shift the result down to bit 0 */
205u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
206{
207 u32 v;
208
209 v = prm_read_mod_reg(domain, idx);
210 v &= mask;
211 v >>= __ffs(mask);
212
213 return v;
214}
215
a58caad1
TL		 216/* Read a register in a CM module */
217u32 cm_read_mod_reg(s16 module, u16 idx)
218{
219 return __omap_prcm_read(cm_base, module, idx);
220}
a58caad1
TL		 221
222/* Write into a register in a CM module */
223void cm_write_mod_reg(u32 val, s16 module, u16 idx)
224{
225 __omap_prcm_write(val, cm_base, module, idx);
226}
a58caad1 227
ff00fcc9
TL		 228/* Read-modify-write a register in a CM module. Caller must lock */
229u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
230{
231 u32 v;
232
233 v = cm_read_mod_reg(module, idx);
234 v &= ~mask;
235 v |= bits;
236 cm_write_mod_reg(v, module, idx);
237
238 return v;
239}
ff00fcc9 240
72350b29
PW		 241/**
242 * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
243 * @reg: physical address of module IDLEST register
244 * @mask: value to mask against to determine if the module is active
419cc97d 245 * @idlest: idle state indicator (0 or 1) for the clock
72350b29
PW		 246 * @name: name of the clock (for printk)
247 *
248 * Returns 1 if the module indicated readiness in time, or 0 if it
249 * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
250 */
419cc97d
RL		 251int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
252 const char *name)
72350b29
PW		 253{
254 int i = 0;
255 int ena = 0;
256
419cc97d 257 if (idlest)
72350b29
PW		 258 ena = 0;
259 else
419cc97d 260 ena = mask;
72350b29
PW		 261
262 /* Wait for lock */
6f8b7ff5
PW		 263 omap_test_timeout(((__raw_readl(reg) & mask) == ena),
264 MAX_MODULE_ENABLE_WAIT, i);
72350b29
PW		 265
266 if (i < MAX_MODULE_ENABLE_WAIT)
267 pr_debug("cm: Module associated with clock %s ready after %d "
268 "loops\n", name, i);
269 else
270 pr_err("cm: Module associated with clock %s didn't enable in "
271 "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
272
273 return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
274};
275
a58caad1
TL		 276void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
277{
278 prm_base = omap2_globals->prm;
279 cm_base = omap2_globals->cm;
9ef89150 280 cm2_base = omap2_globals->cm2;
a58caad1 281}
c171a258
RN		 282
283#ifdef CONFIG_ARCH_OMAP3
284void omap3_prcm_save_context(void)
285{
286 prcm_context.control_padconf_sys_nirq =
287 omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
133464dc
JH		 288 prcm_context.iva2_cm_clksel1 =
289 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
c171a258
RN		 290 prcm_context.iva2_cm_clksel2 =
291 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
292 prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
293 prcm_context.sgx_cm_clksel =
294 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
c171a258
RN		 295 prcm_context.dss_cm_clksel =
296 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
297 prcm_context.cam_cm_clksel =
298 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
299 prcm_context.per_cm_clksel =
300 cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
301 prcm_context.emu_cm_clksel =
302 cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
303 prcm_context.emu_cm_clkstctrl =
84c0c39a 304 cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
c171a258
RN		 305 prcm_context.pll_cm_autoidle2 =
306 cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
307 prcm_context.pll_cm_clksel4 =
308 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
309 prcm_context.pll_cm_clksel5 =
310 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
c171a258
RN		 311 prcm_context.pll_cm_clken2 =
312 cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
313 prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
314 prcm_context.iva2_cm_fclken =
315 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
316 prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD,
317 OMAP3430_CM_CLKEN_PLL);
318 prcm_context.core_cm_fclken1 =
319 cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
320 prcm_context.core_cm_fclken3 =
321 cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
322 prcm_context.sgx_cm_fclken =
323 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
324 prcm_context.wkup_cm_fclken =
325 cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
326 prcm_context.dss_cm_fclken =
327 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
328 prcm_context.cam_cm_fclken =
329 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
330 prcm_context.per_cm_fclken =
331 cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
332 prcm_context.usbhost_cm_fclken =
333 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
334 prcm_context.core_cm_iclken1 =
335 cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
336 prcm_context.core_cm_iclken2 =
337 cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
338 prcm_context.core_cm_iclken3 =
339 cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
340 prcm_context.sgx_cm_iclken =
341 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
342 prcm_context.wkup_cm_iclken =
343 cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
344 prcm_context.dss_cm_iclken =
345 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
346 prcm_context.cam_cm_iclken =
347 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
348 prcm_context.per_cm_iclken =
349 cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
350 prcm_context.usbhost_cm_iclken =
351 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
352 prcm_context.iva2_cm_autiidle2 =
353 cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
354 prcm_context.mpu_cm_autoidle2 =
355 cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
c171a258 356 prcm_context.iva2_cm_clkstctrl =
84c0c39a 357 cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
c171a258 358 prcm_context.mpu_cm_clkstctrl =
84c0c39a 359 cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
c171a258 360 prcm_context.core_cm_clkstctrl =
84c0c39a 361 cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
c171a258 362 prcm_context.sgx_cm_clkstctrl =
84c0c39a
AP		 363 cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
364 OMAP2_CM_CLKSTCTRL);
c171a258 365 prcm_context.dss_cm_clkstctrl =
84c0c39a 366 cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
c171a258 367 prcm_context.cam_cm_clkstctrl =
84c0c39a 368 cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
c171a258 369 prcm_context.per_cm_clkstctrl =
84c0c39a 370 cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
c171a258 371 prcm_context.neon_cm_clkstctrl =
84c0c39a 372 cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
c171a258 373 prcm_context.usbhost_cm_clkstctrl =
84c0c39a
AP		 374 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
375 OMAP2_CM_CLKSTCTRL);
c171a258
RN		 376 prcm_context.core_cm_autoidle1 =
377 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
378 prcm_context.core_cm_autoidle2 =
379 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
380 prcm_context.core_cm_autoidle3 =
381 cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
382 prcm_context.wkup_cm_autoidle =
383 cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
384 prcm_context.dss_cm_autoidle =
385 cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
386 prcm_context.cam_cm_autoidle =
387 cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
388 prcm_context.per_cm_autoidle =
389 cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
390 prcm_context.usbhost_cm_autoidle =
391 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
392 prcm_context.sgx_cm_sleepdep =
393 cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP);
394 prcm_context.dss_cm_sleepdep =
395 cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
396 prcm_context.cam_cm_sleepdep =
397 cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
398 prcm_context.per_cm_sleepdep =
399 cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
400 prcm_context.usbhost_cm_sleepdep =
401 cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
402 prcm_context.cm_clkout_ctrl = cm_read_mod_reg(OMAP3430_CCR_MOD,
403 OMAP3_CM_CLKOUT_CTRL_OFFSET);
404 prcm_context.prm_clkout_ctrl = prm_read_mod_reg(OMAP3430_CCR_MOD,
405 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
406 prcm_context.sgx_pm_wkdep =
407 prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP);
408 prcm_context.dss_pm_wkdep =
409 prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP);
410 prcm_context.cam_pm_wkdep =
411 prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP);
412 prcm_context.per_pm_wkdep =
413 prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP);
414 prcm_context.neon_pm_wkdep =
415 prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP);
416 prcm_context.usbhost_pm_wkdep =
417 prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
418 prcm_context.core_pm_mpugrpsel1 =
419 prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL1);
420 prcm_context.iva2_pm_ivagrpsel1 =
421 prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1);
422 prcm_context.core_pm_mpugrpsel3 =
423 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_MPUGRPSEL3);
424 prcm_context.core_pm_ivagrpsel3 =
425 prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
426 prcm_context.wkup_pm_mpugrpsel =
427 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
428 prcm_context.wkup_pm_ivagrpsel =
429 prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
430 prcm_context.per_pm_mpugrpsel =
431 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
432 prcm_context.per_pm_ivagrpsel =
433 prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
434 prcm_context.wkup_pm_wken = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
435 return;
436}
437
438void omap3_prcm_restore_context(void)
439{
440 omap_ctrl_writel(prcm_context.control_padconf_sys_nirq,
441 OMAP343X_CONTROL_PADCONF_SYSNIRQ);
133464dc
JH		 442 cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
443 CM_CLKSEL1);
c171a258
RN		 444 cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
445 CM_CLKSEL2);
446 __raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
447 cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
448 CM_CLKSEL);
c171a258
RN		 449 cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
450 CM_CLKSEL);
451 cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
452 CM_CLKSEL);
453 cm_write_mod_reg(prcm_context.per_cm_clksel, OMAP3430_PER_MOD,
454 CM_CLKSEL);
455 cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
456 CM_CLKSEL1);
457 cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
84c0c39a 458 OMAP2_CM_CLKSTCTRL);
c171a258
RN		 459 cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD,
460 CM_AUTOIDLE2);
461 cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD,
462 OMAP3430ES2_CM_CLKSEL4);
463 cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
464 OMAP3430ES2_CM_CLKSEL5);
c171a258
RN		 465 cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
466 OMAP3430ES2_CM_CLKEN2);
467 __raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
468 cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
469 CM_FCLKEN);
470 cm_write_mod_reg(prcm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
471 OMAP3430_CM_CLKEN_PLL);
472 cm_write_mod_reg(prcm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1);
473 cm_write_mod_reg(prcm_context.core_cm_fclken3, CORE_MOD,
474 OMAP3430ES2_CM_FCLKEN3);
475 cm_write_mod_reg(prcm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
476 CM_FCLKEN);
477 cm_write_mod_reg(prcm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
478 cm_write_mod_reg(prcm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
479 CM_FCLKEN);
480 cm_write_mod_reg(prcm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
481 CM_FCLKEN);
482 cm_write_mod_reg(prcm_context.per_cm_fclken, OMAP3430_PER_MOD,
483 CM_FCLKEN);
484 cm_write_mod_reg(prcm_context.usbhost_cm_fclken,
485 OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
486 cm_write_mod_reg(prcm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1);
487 cm_write_mod_reg(prcm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2);
488 cm_write_mod_reg(prcm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3);
489 cm_write_mod_reg(prcm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
490 CM_ICLKEN);
491 cm_write_mod_reg(prcm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
492 cm_write_mod_reg(prcm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
493 CM_ICLKEN);
494 cm_write_mod_reg(prcm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
495 CM_ICLKEN);
496 cm_write_mod_reg(prcm_context.per_cm_iclken, OMAP3430_PER_MOD,
497 CM_ICLKEN);
498 cm_write_mod_reg(prcm_context.usbhost_cm_iclken,
499 OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
500 cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD,
501 CM_AUTOIDLE2);
502 cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
c171a258 503 cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
84c0c39a
AP		 504 OMAP2_CM_CLKSTCTRL);
505 cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD,
506 OMAP2_CM_CLKSTCTRL);
c171a258 507 cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD,
84c0c39a 508 OMAP2_CM_CLKSTCTRL);
c171a258 509 cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
84c0c39a 510 OMAP2_CM_CLKSTCTRL);
c171a258 511 cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
84c0c39a 512 OMAP2_CM_CLKSTCTRL);
c171a258 513 cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
84c0c39a 514 OMAP2_CM_CLKSTCTRL);
c171a258 515 cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
84c0c39a 516 OMAP2_CM_CLKSTCTRL);
c171a258 517 cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
84c0c39a 518 OMAP2_CM_CLKSTCTRL);
c171a258 519 cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl,
84c0c39a 520 OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
c171a258
RN		 521 cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD,
522 CM_AUTOIDLE1);
523 cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD,
524 CM_AUTOIDLE2);
525 cm_write_mod_reg(prcm_context.core_cm_autoidle3, CORE_MOD,
526 CM_AUTOIDLE3);
527 cm_write_mod_reg(prcm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE);
528 cm_write_mod_reg(prcm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
529 CM_AUTOIDLE);
530 cm_write_mod_reg(prcm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
531 CM_AUTOIDLE);
532 cm_write_mod_reg(prcm_context.per_cm_autoidle, OMAP3430_PER_MOD,
533 CM_AUTOIDLE);
534 cm_write_mod_reg(prcm_context.usbhost_cm_autoidle,
535 OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
536 cm_write_mod_reg(prcm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
537 OMAP3430_CM_SLEEPDEP);
538 cm_write_mod_reg(prcm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
539 OMAP3430_CM_SLEEPDEP);
540 cm_write_mod_reg(prcm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
541 OMAP3430_CM_SLEEPDEP);
542 cm_write_mod_reg(prcm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
543 OMAP3430_CM_SLEEPDEP);
544 cm_write_mod_reg(prcm_context.usbhost_cm_sleepdep,
545 OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
546 cm_write_mod_reg(prcm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
547 OMAP3_CM_CLKOUT_CTRL_OFFSET);
548 prm_write_mod_reg(prcm_context.prm_clkout_ctrl, OMAP3430_CCR_MOD,
549 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
550 prm_write_mod_reg(prcm_context.sgx_pm_wkdep, OMAP3430ES2_SGX_MOD,
551 PM_WKDEP);
552 prm_write_mod_reg(prcm_context.dss_pm_wkdep, OMAP3430_DSS_MOD,
553 PM_WKDEP);
554 prm_write_mod_reg(prcm_context.cam_pm_wkdep, OMAP3430_CAM_MOD,
555 PM_WKDEP);
556 prm_write_mod_reg(prcm_context.per_pm_wkdep, OMAP3430_PER_MOD,
557 PM_WKDEP);
558 prm_write_mod_reg(prcm_context.neon_pm_wkdep, OMAP3430_NEON_MOD,
559 PM_WKDEP);
560 prm_write_mod_reg(prcm_context.usbhost_pm_wkdep,
561 OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
562 prm_write_mod_reg(prcm_context.core_pm_mpugrpsel1, CORE_MOD,
563 OMAP3430_PM_MPUGRPSEL1);
564 prm_write_mod_reg(prcm_context.iva2_pm_ivagrpsel1, OMAP3430_IVA2_MOD,
565 OMAP3430_PM_IVAGRPSEL1);
566 prm_write_mod_reg(prcm_context.core_pm_mpugrpsel3, CORE_MOD,
567 OMAP3430ES2_PM_MPUGRPSEL3);
568 prm_write_mod_reg(prcm_context.core_pm_ivagrpsel3, CORE_MOD,
569 OMAP3430ES2_PM_IVAGRPSEL3);
570 prm_write_mod_reg(prcm_context.wkup_pm_mpugrpsel, WKUP_MOD,
571 OMAP3430_PM_MPUGRPSEL);
572 prm_write_mod_reg(prcm_context.wkup_pm_ivagrpsel, WKUP_MOD,
573 OMAP3430_PM_IVAGRPSEL);
574 prm_write_mod_reg(prcm_context.per_pm_mpugrpsel, OMAP3430_PER_MOD,
575 OMAP3430_PM_MPUGRPSEL);
576 prm_write_mod_reg(prcm_context.per_pm_ivagrpsel, OMAP3430_PER_MOD,
577 OMAP3430_PM_IVAGRPSEL);
578 prm_write_mod_reg(prcm_context.wkup_pm_wken, WKUP_MOD, PM_WKEN);
579 return;
580}
581#endif
Linux kernel - Deliverables
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