projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| d198b514 PW |
1 | /* |
| 2 | * OMAP44xx PRCM MPU instance offset macros | |
| 3 | * | |
| d9a16f9a | 4 | * Copyright (C) 2010, 2012 Texas Instruments, Inc. |
| d198b514 PW |
5 | * Copyright (C) 2010 Nokia Corporation |
| 6 | * | |
| 7 | * Paul Walmsley (paul@pwsan.com) | |
| 8 | * Rajendra Nayak (rnayak@ti.com) | |
| 9 | * Benoit Cousson (b-cousson@ti.com) | |
| 10 | * | |
| 11 | * This file is automatically generated from the OMAP hardware databases. | |
| 12 | * We respectfully ask that any modifications to this file be coordinated | |
| 13 | * with the public linux-omap@vger.kernel.org mailing list and the | |
| 14 | * authors above to ensure that the autogeneration scripts are kept | |
| 15 | * up-to-date with the file contents. | |
| 16 | * | |
| 17 | * This program is free software; you can redistribute it and/or modify | |
| 18 | * it under the terms of the GNU General Public License version 2 as | |
| 19 | * published by the Free Software Foundation. | |
| 20 | * | |
| 21 | * XXX This file needs to be updated to align on one of "OMAP4", "OMAP44XX", | |
| 22 | * or "OMAP4430". | |
| 23 | */ | |
| 24 | ||
| 25 | #ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H | |
| 26 | #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H | |
| 27 | ||
| 40243ad3 | 28 | #include "prcm_mpu_44xx_54xx.h" |
| d9a16f9a PW |
29 | #include "common.h" |
| 30 | ||
| d198b514 PW |
31 | #define OMAP4430_PRCM_MPU_BASE 0x48243000 |
| 32 | ||
| cdb54c44 PW |
33 | #define OMAP44XX_PRCM_MPU_REGADDR(inst, reg) \ |
| 34 | OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg)) | |
| d198b514 PW |
35 | |
| 36 | /* PRCM_MPU instances */ | |
| cdb54c44 PW |
37 | #define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000 |
| 38 | #define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200 | |
| 39 | #define OMAP4430_PRCM_MPU_CPU0_INST 0x0400 | |
| 40 | #define OMAP4430_PRCM_MPU_CPU1_INST 0x0800 | |
| d198b514 | 41 | |
| e4156ee5 | 42 | /* PRCM_MPU clockdomain register offsets (from instance start) */ |
| 1a9f5e89 BC |
43 | #define OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS 0x0018 |
| 44 | #define OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS 0x0018 | |
| e4156ee5 PW |
45 | |
| 46 | ||
| d198b514 PW |
47 | /* |
| 48 | * PRCM_MPU | |
| 49 | * | |
| 50 | * The PRCM_MPU is a local PRCM inside the MPU subsystem. For the PRCM (global) | |
| 51 | * point of view the PRCM_MPU is a single entity. It shares the same | |
| 52 | * programming model as the global PRCM and thus can be assimilate as two new | |
| 53 | * MOD inside the PRCM | |
| 54 | */ | |
| 55 | ||
| 56 | /* PRCM_MPU.OCP_SOCKET_PRCM register offsets */ | |
| a3b90ad8 BC |
57 | #define OMAP4_REVISION_PRCM_OFFSET 0x0000 |
| 58 | #define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000) | |
| d198b514 PW |
59 | |
| 60 | /* PRCM_MPU.DEVICE_PRM register offsets */ | |
| a3b90ad8 BC |
61 | #define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000 |
| 62 | #define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000) | |
| 63 | #define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004 | |
| 64 | #define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004) | |
| d198b514 PW |
65 | |
| 66 | /* PRCM_MPU.CPU0 register offsets */ | |
| a3b90ad8 BC |
67 | #define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 |
| 68 | #define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000) | |
| 69 | #define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004 | |
| 70 | #define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004) | |
| 71 | #define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008 | |
| 72 | #define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008) | |
| 73 | #define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c | |
| 74 | #define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c) | |
| 75 | #define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010 | |
| 76 | #define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010) | |
| 77 | #define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014 | |
| 78 | #define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014) | |
| 79 | #define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018 | |
| 80 | #define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018) | |
| d198b514 PW |
81 | |
| 82 | /* PRCM_MPU.CPU1 register offsets */ | |
| a3b90ad8 BC |
83 | #define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000 |
| 84 | #define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000) | |
| 85 | #define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004 | |
| 86 | #define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004) | |
| 87 | #define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008 | |
| 88 | #define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008) | |
| 89 | #define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c | |
| 90 | #define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c) | |
| 91 | #define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010 | |
| 92 | #define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010) | |
| 93 | #define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014 | |
| 94 | #define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014) | |
| 95 | #define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018 | |
| 96 | #define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018) | |
| d198b514 PW |
97 | |
| 98 | #endif |