projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| ddd04b98 VH |
1 | /* |
| 2 | * AM33XX PRM_XXX register bits | |
| 3 | * | |
| 4 | * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/ | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or | |
| 7 | * modify it under the terms of the GNU General Public License as | |
| 8 | * published by the Free Software Foundation version 2. | |
| 9 | * | |
| 10 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
| 11 | * kind, whether express or implied; without even the implied warranty | |
| 12 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | * GNU General Public License for more details. | |
| 14 | */ | |
| 15 | ||
| 16 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H | |
| 17 | #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H | |
| 18 | ||
| 19 | #include "prm.h" | |
| 20 | ||
| ddd04b98 | 21 | #define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17) |
| ddd04b98 | 22 | #define AM33XX_GFX_MEM_RETSTATE_MASK (1 << 6) |
| ddd04b98 | 23 | #define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4) |
| ddd04b98 | 24 | #define AM33XX_GLOBAL_WARM_SW_RST_MASK (1 << 1) |
| 7323f219 | 25 | #define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0) |
| ddd04b98 | 26 | #define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5) |
| ddd04b98 | 27 | #define AM33XX_PRUSS_MEM_RETSTATE_MASK (1 << 7) |
| ddd04b98 | 28 | #define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23) |
| ddd04b98 VH |
29 | #define AM33XX_LASTPOWERSTATEENTERED_SHIFT 24 |
| 30 | #define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24) | |
| ddd04b98 | 31 | #define AM33XX_LOGICRETSTATE_MASK (1 << 2) |
| ddd04b98 | 32 | #define AM33XX_LOGICRETSTATE_3_3_MASK (1 << 3) |
| ddd04b98 VH |
33 | #define AM33XX_LOGICSTATEST_SHIFT 2 |
| 34 | #define AM33XX_LOGICSTATEST_MASK (1 << 2) | |
| ddd04b98 VH |
35 | #define AM33XX_LOWPOWERSTATECHANGE_SHIFT 4 |
| 36 | #define AM33XX_LOWPOWERSTATECHANGE_MASK (1 << 4) | |
| ddd04b98 | 37 | #define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18) |
| ddd04b98 | 38 | #define AM33XX_MPU_L1_RETSTATE_MASK (1 << 22) |
| ddd04b98 | 39 | #define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6) |
| ddd04b98 | 40 | #define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20) |
| ddd04b98 | 41 | #define AM33XX_MPU_L2_RETSTATE_MASK (1 << 23) |
| ddd04b98 | 42 | #define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8) |
| ddd04b98 | 43 | #define AM33XX_MPU_RAM_ONSTATE_MASK (0x3 << 16) |
| ddd04b98 | 44 | #define AM33XX_MPU_RAM_RETSTATE_MASK (1 << 24) |
| ddd04b98 | 45 | #define AM33XX_MPU_RAM_STATEST_MASK (0x3 << 4) |
| ddd04b98 | 46 | #define AM33XX_PER_MEM_ONSTATE_MASK (0x3 << 25) |
| ddd04b98 | 47 | #define AM33XX_PER_MEM_RETSTATE_MASK (1 << 29) |
| ddd04b98 | 48 | #define AM33XX_PER_MEM_STATEST_MASK (0x3 << 17) |
| ddd04b98 | 49 | #define AM33XX_RAM_MEM_ONSTATE_MASK (0x3 << 30) |
| ddd04b98 | 50 | #define AM33XX_RAM_MEM_RETSTATE_MASK (1 << 27) |
| ddd04b98 | 51 | #define AM33XX_RAM_MEM_STATEST_MASK (0x3 << 21) |
| ddd04b98 | 52 | #endif |