projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| c595713d TL |
1 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H |
| 2 | #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H | |
| 3 | ||
| 4 | /* | |
| 5 | * OMAP3430 Power/Reset Management register bits | |
| 6 | * | |
| 7 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | |
| 8 | * Copyright (C) 2007-2008 Nokia Corporation | |
| 9 | * | |
| 10 | * Written by Paul Walmsley | |
| 11 | * | |
| 12 | * This program is free software; you can redistribute it and/or modify | |
| 13 | * it under the terms of the GNU General Public License version 2 as | |
| 14 | * published by the Free Software Foundation. | |
| 15 | */ | |
| 16 | ||
| 17 | #include "prm.h" | |
| 18 | ||
| 19 | /* Shared register bits */ | |
| 20 | ||
| 21 | /* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */ | |
| 22 | #define OMAP3430_ON_SHIFT 24 | |
| 23 | #define OMAP3430_ON_MASK (0xff << 24) | |
| 24 | #define OMAP3430_ONLP_SHIFT 16 | |
| 25 | #define OMAP3430_ONLP_MASK (0xff << 16) | |
| 26 | #define OMAP3430_RET_SHIFT 8 | |
| 27 | #define OMAP3430_RET_MASK (0xff << 8) | |
| 28 | #define OMAP3430_OFF_SHIFT 0 | |
| 29 | #define OMAP3430_OFF_MASK (0xff << 0) | |
| 30 | ||
| 31 | /* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */ | |
| 32 | #define OMAP3430_ERROROFFSET_SHIFT 24 | |
| 33 | #define OMAP3430_ERROROFFSET_MASK (0xff << 24) | |
| 34 | #define OMAP3430_ERRORGAIN_SHIFT 16 | |
| 35 | #define OMAP3430_ERRORGAIN_MASK (0xff << 16) | |
| 36 | #define OMAP3430_INITVOLTAGE_SHIFT 8 | |
| 37 | #define OMAP3430_INITVOLTAGE_MASK (0xff << 8) | |
| 2bc4ef71 PW |
38 | #define OMAP3430_TIMEOUTEN_MASK (1 << 3) |
| 39 | #define OMAP3430_INITVDD_MASK (1 << 2) | |
| 40 | #define OMAP3430_FORCEUPDATE_MASK (1 << 1) | |
| 41 | #define OMAP3430_VPENABLE_MASK (1 << 0) | |
| c595713d TL |
42 | |
| 43 | /* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */ | |
| 44 | #define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8 | |
| 45 | #define OMAP3430_SMPSWAITTIMEMIN_MASK (0xffff << 8) | |
| 46 | #define OMAP3430_VSTEPMIN_SHIFT 0 | |
| 47 | #define OMAP3430_VSTEPMIN_MASK (0xff << 0) | |
| 48 | ||
| 49 | /* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */ | |
| 50 | #define OMAP3430_SMPSWAITTIMEMAX_SHIFT 8 | |
| 51 | #define OMAP3430_SMPSWAITTIMEMAX_MASK (0xffff << 8) | |
| 52 | #define OMAP3430_VSTEPMAX_SHIFT 0 | |
| 53 | #define OMAP3430_VSTEPMAX_MASK (0xff << 0) | |
| 54 | ||
| 55 | /* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */ | |
| 56 | #define OMAP3430_VDDMAX_SHIFT 24 | |
| 57 | #define OMAP3430_VDDMAX_MASK (0xff << 24) | |
| 58 | #define OMAP3430_VDDMIN_SHIFT 16 | |
| 59 | #define OMAP3430_VDDMIN_MASK (0xff << 16) | |
| 60 | #define OMAP3430_TIMEOUT_SHIFT 0 | |
| 61 | #define OMAP3430_TIMEOUT_MASK (0xffff << 0) | |
| 62 | ||
| 63 | /* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */ | |
| 64 | #define OMAP3430_VPVOLTAGE_SHIFT 0 | |
| 65 | #define OMAP3430_VPVOLTAGE_MASK (0xff << 0) | |
| 66 | ||
| 67 | /* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */ | |
| 2bc4ef71 | 68 | #define OMAP3430_VPINIDLE_MASK (1 << 0) |
| c595713d TL |
69 | |
| 70 | /* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */ | |
| ecb24aa1 PW |
71 | #define OMAP3430_EN_PER_SHIFT 7 |
| 72 | #define OMAP3430_EN_PER_MASK (1 << 7) | |
| c595713d TL |
73 | |
| 74 | /* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */ | |
| 2bc4ef71 | 75 | #define OMAP3430_MEMORYCHANGE_MASK (1 << 3) |
| c595713d TL |
76 | |
| 77 | /* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */ | |
| 2bc4ef71 | 78 | #define OMAP3430_LOGICSTATEST_MASK (1 << 2) |
| c595713d TL |
79 | |
| 80 | /* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */ | |
| 2bc4ef71 | 81 | #define OMAP3430_LASTLOGICSTATEENTERED_MASK (1 << 2) |
| c595713d TL |
82 | |
| 83 | /* | |
| 84 | * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE, | |
| 85 | * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM, | |
| 86 | * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits | |
| 87 | */ | |
| 2bc4ef71 PW |
88 | #define OMAP3430_LASTPOWERSTATEENTERED_SHIFT 0 |
| 89 | #define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0) | |
| c595713d TL |
90 | |
| 91 | /* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */ | |
| 2bc4ef71 | 92 | #define OMAP3430_WKUP_ST_MASK (1 << 0) |
| c595713d TL |
93 | |
| 94 | /* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */ | |
| 2bc4ef71 | 95 | #define OMAP3430_WKUP_EN_MASK (1 << 0) |
| c595713d TL |
96 | |
| 97 | /* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */ | |
| 2bc4ef71 PW |
98 | #define OMAP3430_GRPSEL_MMC2_MASK (1 << 25) |
| 99 | #define OMAP3430_GRPSEL_MMC1_MASK (1 << 24) | |
| 100 | #define OMAP3430_GRPSEL_MCSPI4_MASK (1 << 21) | |
| 101 | #define OMAP3430_GRPSEL_MCSPI3_MASK (1 << 20) | |
| 102 | #define OMAP3430_GRPSEL_MCSPI2_MASK (1 << 19) | |
| 103 | #define OMAP3430_GRPSEL_MCSPI1_MASK (1 << 18) | |
| 104 | #define OMAP3430_GRPSEL_I2C3_MASK (1 << 17) | |
| 105 | #define OMAP3430_GRPSEL_I2C2_MASK (1 << 16) | |
| 106 | #define OMAP3430_GRPSEL_I2C1_MASK (1 << 15) | |
| 107 | #define OMAP3430_GRPSEL_UART2_MASK (1 << 14) | |
| 108 | #define OMAP3430_GRPSEL_UART1_MASK (1 << 13) | |
| 109 | #define OMAP3430_GRPSEL_GPT11_MASK (1 << 12) | |
| 110 | #define OMAP3430_GRPSEL_GPT10_MASK (1 << 11) | |
| 111 | #define OMAP3430_GRPSEL_MCBSP5_MASK (1 << 10) | |
| 112 | #define OMAP3430_GRPSEL_MCBSP1_MASK (1 << 9) | |
| 113 | #define OMAP3430_GRPSEL_HSOTGUSB_MASK (1 << 4) | |
| 114 | #define OMAP3430_GRPSEL_D2D_MASK (1 << 3) | |
| c595713d TL |
115 | |
| 116 | /* | |
| 117 | * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, | |
| 118 | * PM_PWSTCTRL_PER shared bits | |
| 119 | */ | |
| 120 | #define OMAP3430_MEMONSTATE_SHIFT 16 | |
| 121 | #define OMAP3430_MEMONSTATE_MASK (0x3 << 16) | |
| 2bc4ef71 | 122 | #define OMAP3430_MEMRETSTATE_MASK (1 << 8) |
| c595713d TL |
123 | |
| 124 | /* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */ | |
| 2bc4ef71 PW |
125 | #define OMAP3430_GRPSEL_GPIO6_MASK (1 << 17) |
| 126 | #define OMAP3430_GRPSEL_GPIO5_MASK (1 << 16) | |
| 127 | #define OMAP3430_GRPSEL_GPIO4_MASK (1 << 15) | |
| 128 | #define OMAP3430_GRPSEL_GPIO3_MASK (1 << 14) | |
| 129 | #define OMAP3430_GRPSEL_GPIO2_MASK (1 << 13) | |
| 130 | #define OMAP3430_GRPSEL_UART3_MASK (1 << 11) | |
| 131 | #define OMAP3430_GRPSEL_GPT9_MASK (1 << 10) | |
| 132 | #define OMAP3430_GRPSEL_GPT8_MASK (1 << 9) | |
| 133 | #define OMAP3430_GRPSEL_GPT7_MASK (1 << 8) | |
| 134 | #define OMAP3430_GRPSEL_GPT6_MASK (1 << 7) | |
| 135 | #define OMAP3430_GRPSEL_GPT5_MASK (1 << 6) | |
| 136 | #define OMAP3430_GRPSEL_GPT4_MASK (1 << 5) | |
| 137 | #define OMAP3430_GRPSEL_GPT3_MASK (1 << 4) | |
| 138 | #define OMAP3430_GRPSEL_GPT2_MASK (1 << 3) | |
| 139 | #define OMAP3430_GRPSEL_MCBSP4_MASK (1 << 2) | |
| 140 | #define OMAP3430_GRPSEL_MCBSP3_MASK (1 << 1) | |
| 141 | #define OMAP3430_GRPSEL_MCBSP2_MASK (1 << 0) | |
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142 | |
| 143 | /* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */ | |
| 2bc4ef71 PW |
144 | #define OMAP3430_GRPSEL_IO_MASK (1 << 8) |
| 145 | #define OMAP3430_GRPSEL_SR2_MASK (1 << 7) | |
| 146 | #define OMAP3430_GRPSEL_SR1_MASK (1 << 6) | |
| 147 | #define OMAP3430_GRPSEL_GPIO1_MASK (1 << 3) | |
| 148 | #define OMAP3430_GRPSEL_GPT12_MASK (1 << 1) | |
| 149 | #define OMAP3430_GRPSEL_GPT1_MASK (1 << 0) | |
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150 | |
| 151 | /* Bits specific to each register */ | |
| 152 | ||
| 153 | /* RM_RSTCTRL_IVA2 */ | |
| 2bc4ef71 PW |
154 | #define OMAP3430_RST3_IVA2_MASK (1 << 2) |
| 155 | #define OMAP3430_RST2_IVA2_MASK (1 << 1) | |
| 156 | #define OMAP3430_RST1_IVA2_MASK (1 << 0) | |
| c595713d TL |
157 | |
| 158 | /* RM_RSTST_IVA2 specific bits */ | |
| 2bc4ef71 PW |
159 | #define OMAP3430_EMULATION_VSEQ_RST_MASK (1 << 13) |
| 160 | #define OMAP3430_EMULATION_VHWA_RST_MASK (1 << 12) | |
| 161 | #define OMAP3430_EMULATION_IVA2_RST_MASK (1 << 11) | |
| 162 | #define OMAP3430_IVA2_SW_RST3_MASK (1 << 10) | |
| 163 | #define OMAP3430_IVA2_SW_RST2_MASK (1 << 9) | |
| 164 | #define OMAP3430_IVA2_SW_RST1_MASK (1 << 8) | |
| c595713d TL |
165 | |
| 166 | /* PM_WKDEP_IVA2 specific bits */ | |
| 167 | ||
| 168 | /* PM_PWSTCTRL_IVA2 specific bits */ | |
| 169 | #define OMAP3430_L2FLATMEMONSTATE_SHIFT 22 | |
| 170 | #define OMAP3430_L2FLATMEMONSTATE_MASK (0x3 << 22) | |
| 171 | #define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT 20 | |
| 172 | #define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK (0x3 << 20) | |
| 173 | #define OMAP3430_L1FLATMEMONSTATE_SHIFT 18 | |
| 174 | #define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18) | |
| 175 | #define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT 16 | |
| 176 | #define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16) | |
| 2bc4ef71 PW |
177 | #define OMAP3430_L2FLATMEMRETSTATE_MASK (1 << 11) |
| 178 | #define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK (1 << 10) | |
| 179 | #define OMAP3430_L1FLATMEMRETSTATE_MASK (1 << 9) | |
| 180 | #define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK (1 << 8) | |
| c595713d TL |
181 | |
| 182 | /* PM_PWSTST_IVA2 specific bits */ | |
| 183 | #define OMAP3430_L2FLATMEMSTATEST_SHIFT 10 | |
| 184 | #define OMAP3430_L2FLATMEMSTATEST_MASK (0x3 << 10) | |
| 185 | #define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT 8 | |
| 186 | #define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK (0x3 << 8) | |
| 187 | #define OMAP3430_L1FLATMEMSTATEST_SHIFT 6 | |
| 188 | #define OMAP3430_L1FLATMEMSTATEST_MASK (0x3 << 6) | |
| 189 | #define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT 4 | |
| 190 | #define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK (0x3 << 4) | |
| 191 | ||
| 192 | /* PM_PREPWSTST_IVA2 specific bits */ | |
| 193 | #define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT 10 | |
| 194 | #define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK (0x3 << 10) | |
| 195 | #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT 8 | |
| 196 | #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK (0x3 << 8) | |
| 197 | #define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT 6 | |
| 198 | #define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK (0x3 << 6) | |
| 199 | #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT 4 | |
| 200 | #define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK (0x3 << 4) | |
| 201 | ||
| 202 | /* PRM_IRQSTATUS_IVA2 specific bits */ | |
| 2bc4ef71 PW |
203 | #define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST_MASK (1 << 2) |
| 204 | #define OMAP3430_FORCEWKUP_ST_MASK (1 << 1) | |
| c595713d TL |
205 | |
| 206 | /* PRM_IRQENABLE_IVA2 specific bits */ | |
| 2bc4ef71 PW |
207 | #define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN_MASK (1 << 2) |
| 208 | #define OMAP3430_FORCEWKUP_EN_MASK (1 << 1) | |
| c595713d TL |
209 | |
| 210 | /* PRM_REVISION specific bits */ | |
| 211 | ||
| 212 | /* PRM_SYSCONFIG specific bits */ | |
| 213 | ||
| 214 | /* PRM_IRQSTATUS_MPU specific bits */ | |
| 215 | #define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25 | |
| 2bc4ef71 PW |
216 | #define OMAP3430ES2_SND_PERIPH_DPLL_ST_MASK (1 << 25) |
| 217 | #define OMAP3430_VC_TIMEOUTERR_ST_MASK (1 << 24) | |
| 218 | #define OMAP3430_VC_RAERR_ST_MASK (1 << 23) | |
| 219 | #define OMAP3430_VC_SAERR_ST_MASK (1 << 22) | |
| 220 | #define OMAP3430_VP2_TRANXDONE_ST_MASK (1 << 21) | |
| 221 | #define OMAP3430_VP2_EQVALUE_ST_MASK (1 << 20) | |
| 222 | #define OMAP3430_VP2_NOSMPSACK_ST_MASK (1 << 19) | |
| 223 | #define OMAP3430_VP2_MAXVDD_ST_MASK (1 << 18) | |
| 224 | #define OMAP3430_VP2_MINVDD_ST_MASK (1 << 17) | |
| 225 | #define OMAP3430_VP2_OPPCHANGEDONE_ST_MASK (1 << 16) | |
| 226 | #define OMAP3430_VP1_TRANXDONE_ST_MASK (1 << 15) | |
| 227 | #define OMAP3430_VP1_EQVALUE_ST_MASK (1 << 14) | |
| 228 | #define OMAP3430_VP1_NOSMPSACK_ST_MASK (1 << 13) | |
| 229 | #define OMAP3430_VP1_MAXVDD_ST_MASK (1 << 12) | |
| 230 | #define OMAP3430_VP1_MINVDD_ST_MASK (1 << 11) | |
| 231 | #define OMAP3430_VP1_OPPCHANGEDONE_ST_MASK (1 << 10) | |
| 232 | #define OMAP3430_IO_ST_MASK (1 << 9) | |
| 233 | #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_MASK (1 << 8) | |
| c595713d | 234 | #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8 |
| 2bc4ef71 | 235 | #define OMAP3430_MPU_DPLL_ST_MASK (1 << 7) |
| c595713d | 236 | #define OMAP3430_MPU_DPLL_ST_SHIFT 7 |
| 2bc4ef71 | 237 | #define OMAP3430_PERIPH_DPLL_ST_MASK (1 << 6) |
| c595713d | 238 | #define OMAP3430_PERIPH_DPLL_ST_SHIFT 6 |
| 2bc4ef71 | 239 | #define OMAP3430_CORE_DPLL_ST_MASK (1 << 5) |
| c595713d | 240 | #define OMAP3430_CORE_DPLL_ST_SHIFT 5 |
| 2bc4ef71 PW |
241 | #define OMAP3430_TRANSITION_ST_MASK (1 << 4) |
| 242 | #define OMAP3430_EVGENOFF_ST_MASK (1 << 3) | |
| 243 | #define OMAP3430_EVGENON_ST_MASK (1 << 2) | |
| 244 | #define OMAP3430_FS_USB_WKUP_ST_MASK (1 << 1) | |
| c595713d TL |
245 | |
| 246 | /* PRM_IRQENABLE_MPU specific bits */ | |
| 247 | #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25 | |
| 2bc4ef71 PW |
248 | #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_MASK (1 << 25) |
| 249 | #define OMAP3430_VC_TIMEOUTERR_EN_MASK (1 << 24) | |
| 250 | #define OMAP3430_VC_RAERR_EN_MASK (1 << 23) | |
| 251 | #define OMAP3430_VC_SAERR_EN_MASK (1 << 22) | |
| 252 | #define OMAP3430_VP2_TRANXDONE_EN_MASK (1 << 21) | |
| 253 | #define OMAP3430_VP2_EQVALUE_EN_MASK (1 << 20) | |
| 254 | #define OMAP3430_VP2_NOSMPSACK_EN_MASK (1 << 19) | |
| 255 | #define OMAP3430_VP2_MAXVDD_EN_MASK (1 << 18) | |
| 256 | #define OMAP3430_VP2_MINVDD_EN_MASK (1 << 17) | |
| 257 | #define OMAP3430_VP2_OPPCHANGEDONE_EN_MASK (1 << 16) | |
| 258 | #define OMAP3430_VP1_TRANXDONE_EN_MASK (1 << 15) | |
| 259 | #define OMAP3430_VP1_EQVALUE_EN_MASK (1 << 14) | |
| 260 | #define OMAP3430_VP1_NOSMPSACK_EN_MASK (1 << 13) | |
| 261 | #define OMAP3430_VP1_MAXVDD_EN_MASK (1 << 12) | |
| 262 | #define OMAP3430_VP1_MINVDD_EN_MASK (1 << 11) | |
| 263 | #define OMAP3430_VP1_OPPCHANGEDONE_EN_MASK (1 << 10) | |
| 264 | #define OMAP3430_IO_EN_MASK (1 << 9) | |
| 265 | #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_MASK (1 << 8) | |
| c595713d | 266 | #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8 |
| 2bc4ef71 | 267 | #define OMAP3430_MPU_DPLL_RECAL_EN_MASK (1 << 7) |
| c595713d | 268 | #define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7 |
| 2bc4ef71 | 269 | #define OMAP3430_PERIPH_DPLL_RECAL_EN_MASK (1 << 6) |
| c595713d | 270 | #define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6 |
| 2bc4ef71 | 271 | #define OMAP3430_CORE_DPLL_RECAL_EN_MASK (1 << 5) |
| c595713d | 272 | #define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5 |
| 2bc4ef71 PW |
273 | #define OMAP3430_TRANSITION_EN_MASK (1 << 4) |
| 274 | #define OMAP3430_EVGENOFF_EN_MASK (1 << 3) | |
| 275 | #define OMAP3430_EVGENON_EN_MASK (1 << 2) | |
| 276 | #define OMAP3430_FS_USB_WKUP_EN_MASK (1 << 1) | |
| c595713d TL |
277 | |
| 278 | /* RM_RSTST_MPU specific bits */ | |
| 2bc4ef71 | 279 | #define OMAP3430_EMULATION_MPU_RST_MASK (1 << 11) |
| c595713d TL |
280 | |
| 281 | /* PM_WKDEP_MPU specific bits */ | |
| ecb24aa1 PW |
282 | #define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5 |
| 283 | #define OMAP3430_PM_WKDEP_MPU_EN_DSS_MASK (1 << 5) | |
| 284 | #define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT 2 | |
| 285 | #define OMAP3430_PM_WKDEP_MPU_EN_IVA2_MASK (1 << 2) | |
| c595713d TL |
286 | |
| 287 | /* PM_EVGENCTRL_MPU */ | |
| 288 | #define OMAP3430_OFFLOADMODE_SHIFT 3 | |
| 289 | #define OMAP3430_OFFLOADMODE_MASK (0x3 << 3) | |
| 290 | #define OMAP3430_ONLOADMODE_SHIFT 1 | |
| 291 | #define OMAP3430_ONLOADMODE_MASK (0x3 << 1) | |
| 2bc4ef71 | 292 | #define OMAP3430_ENABLE_MASK (1 << 0) |
| c595713d TL |
293 | |
| 294 | /* PM_EVGENONTIM_MPU */ | |
| 295 | #define OMAP3430_ONTIMEVAL_SHIFT 0 | |
| 296 | #define OMAP3430_ONTIMEVAL_MASK (0xffffffff << 0) | |
| 297 | ||
| 298 | /* PM_EVGENOFFTIM_MPU */ | |
| 299 | #define OMAP3430_OFFTIMEVAL_SHIFT 0 | |
| 300 | #define OMAP3430_OFFTIMEVAL_MASK (0xffffffff << 0) | |
| 301 | ||
| 302 | /* PM_PWSTCTRL_MPU specific bits */ | |
| 303 | #define OMAP3430_L2CACHEONSTATE_SHIFT 16 | |
| 304 | #define OMAP3430_L2CACHEONSTATE_MASK (0x3 << 16) | |
| 2bc4ef71 PW |
305 | #define OMAP3430_L2CACHERETSTATE_MASK (1 << 8) |
| 306 | #define OMAP3430_LOGICL1CACHERETSTATE_MASK (1 << 2) | |
| c595713d TL |
307 | |
| 308 | /* PM_PWSTST_MPU specific bits */ | |
| 309 | #define OMAP3430_L2CACHESTATEST_SHIFT 6 | |
| 310 | #define OMAP3430_L2CACHESTATEST_MASK (0x3 << 6) | |
| 2bc4ef71 | 311 | #define OMAP3430_LOGICL1CACHESTATEST_MASK (1 << 2) |
| c595713d TL |
312 | |
| 313 | /* PM_PREPWSTST_MPU specific bits */ | |
| 314 | #define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT 6 | |
| 315 | #define OMAP3430_LASTL2CACHESTATEENTERED_MASK (0x3 << 6) | |
| 2bc4ef71 | 316 | #define OMAP3430_LASTLOGICL1CACHESTATEENTERED_MASK (1 << 2) |
| c595713d TL |
317 | |
| 318 | /* RM_RSTCTRL_CORE */ | |
| 2bc4ef71 PW |
319 | #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK (1 << 1) |
| 320 | #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK (1 << 0) | |
| c595713d TL |
321 | |
| 322 | /* RM_RSTST_CORE specific bits */ | |
| 2bc4ef71 PW |
323 | #define OMAP3430_MODEM_SECURITY_VIOL_RST_MASK (1 << 10) |
| 324 | #define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON_MASK (1 << 9) | |
| 325 | #define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST_MASK (1 << 8) | |
| c595713d TL |
326 | |
| 327 | /* PM_WKEN1_CORE specific bits */ | |
| 328 | ||
| 329 | /* PM_MPUGRPSEL1_CORE specific bits */ | |
| 2bc4ef71 | 330 | #define OMAP3430_GRPSEL_FSHOSTUSB_MASK (1 << 5) |
| c595713d TL |
331 | |
| 332 | /* PM_IVA2GRPSEL1_CORE specific bits */ | |
| 333 | ||
| 334 | /* PM_WKST1_CORE specific bits */ | |
| 335 | ||
| 336 | /* PM_PWSTCTRL_CORE specific bits */ | |
| 337 | #define OMAP3430_MEM2ONSTATE_SHIFT 18 | |
| 338 | #define OMAP3430_MEM2ONSTATE_MASK (0x3 << 18) | |
| 339 | #define OMAP3430_MEM1ONSTATE_SHIFT 16 | |
| 340 | #define OMAP3430_MEM1ONSTATE_MASK (0x3 << 16) | |
| 2bc4ef71 PW |
341 | #define OMAP3430_MEM2RETSTATE_MASK (1 << 9) |
| 342 | #define OMAP3430_MEM1RETSTATE_MASK (1 << 8) | |
| c595713d TL |
343 | |
| 344 | /* PM_PWSTST_CORE specific bits */ | |
| 345 | #define OMAP3430_MEM2STATEST_SHIFT 6 | |
| 346 | #define OMAP3430_MEM2STATEST_MASK (0x3 << 6) | |
| 347 | #define OMAP3430_MEM1STATEST_SHIFT 4 | |
| 348 | #define OMAP3430_MEM1STATEST_MASK (0x3 << 4) | |
| 349 | ||
| 350 | /* PM_PREPWSTST_CORE specific bits */ | |
| 351 | #define OMAP3430_LASTMEM2STATEENTERED_SHIFT 6 | |
| 352 | #define OMAP3430_LASTMEM2STATEENTERED_MASK (0x3 << 6) | |
| 353 | #define OMAP3430_LASTMEM1STATEENTERED_SHIFT 4 | |
| 354 | #define OMAP3430_LASTMEM1STATEENTERED_MASK (0x3 << 4) | |
| 355 | ||
| 356 | /* RM_RSTST_GFX specific bits */ | |
| 357 | ||
| 358 | /* PM_WKDEP_GFX specific bits */ | |
| 2bc4ef71 | 359 | #define OMAP3430_PM_WKDEP_GFX_EN_IVA2_MASK (1 << 2) |
| c595713d TL |
360 | |
| 361 | /* PM_PWSTCTRL_GFX specific bits */ | |
| 362 | ||
| 363 | /* PM_PWSTST_GFX specific bits */ | |
| 364 | ||
| 365 | /* PM_PREPWSTST_GFX specific bits */ | |
| 366 | ||
| 367 | /* PM_WKEN_WKUP specific bits */ | |
| 2bc4ef71 PW |
368 | #define OMAP3430_EN_IO_CHAIN_MASK (1 << 16) |
| 369 | #define OMAP3430_EN_IO_MASK (1 << 8) | |
| 370 | #define OMAP3430_EN_GPIO1_MASK (1 << 3) | |
| c595713d TL |
371 | |
| 372 | /* PM_MPUGRPSEL_WKUP specific bits */ | |
| 373 | ||
| 374 | /* PM_IVA2GRPSEL_WKUP specific bits */ | |
| 375 | ||
| 376 | /* PM_WKST_WKUP specific bits */ | |
| 2bc4ef71 PW |
377 | #define OMAP3430_ST_IO_CHAIN_MASK (1 << 16) |
| 378 | #define OMAP3430_ST_IO_MASK (1 << 8) | |
| c595713d TL |
379 | |
| 380 | /* PRM_CLKSEL */ | |
| 381 | #define OMAP3430_SYS_CLKIN_SEL_SHIFT 0 | |
| 382 | #define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0) | |
| 383 | ||
| 384 | /* PRM_CLKOUT_CTRL */ | |
| 2bc4ef71 | 385 | #define OMAP3430_CLKOUT_EN_MASK (1 << 7) |
| c595713d TL |
386 | #define OMAP3430_CLKOUT_EN_SHIFT 7 |
| 387 | ||
| 388 | /* RM_RSTST_DSS specific bits */ | |
| 389 | ||
| 390 | /* PM_WKEN_DSS */ | |
| 2bc4ef71 | 391 | #define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK (1 << 0) |
| c595713d TL |
392 | |
| 393 | /* PM_WKDEP_DSS specific bits */ | |
| 2bc4ef71 | 394 | #define OMAP3430_PM_WKDEP_DSS_EN_IVA2_MASK (1 << 2) |
| c595713d TL |
395 | |
| 396 | /* PM_PWSTCTRL_DSS specific bits */ | |
| 397 | ||
| 398 | /* PM_PWSTST_DSS specific bits */ | |
| 399 | ||
| 400 | /* PM_PREPWSTST_DSS specific bits */ | |
| 401 | ||
| 402 | /* RM_RSTST_CAM specific bits */ | |
| 403 | ||
| 404 | /* PM_WKDEP_CAM specific bits */ | |
| 2bc4ef71 | 405 | #define OMAP3430_PM_WKDEP_CAM_EN_IVA2_MASK (1 << 2) |
| c595713d TL |
406 | |
| 407 | /* PM_PWSTCTRL_CAM specific bits */ | |
| 408 | ||
| 409 | /* PM_PWSTST_CAM specific bits */ | |
| 410 | ||
| 411 | /* PM_PREPWSTST_CAM specific bits */ | |
| 412 | ||
| 413 | /* PM_PWSTCTRL_USBHOST specific bits */ | |
| 8dbe4393 | 414 | #define OMAP3430ES2_SAVEANDRESTORE_SHIFT 4 |
| c595713d TL |
415 | |
| 416 | /* RM_RSTST_PER specific bits */ | |
| 417 | ||
| 418 | /* PM_WKEN_PER specific bits */ | |
| 419 | ||
| 420 | /* PM_MPUGRPSEL_PER specific bits */ | |
| 421 | ||
| 422 | /* PM_IVA2GRPSEL_PER specific bits */ | |
| 423 | ||
| 424 | /* PM_WKST_PER specific bits */ | |
| 425 | ||
| 426 | /* PM_WKDEP_PER specific bits */ | |
| 2bc4ef71 | 427 | #define OMAP3430_PM_WKDEP_PER_EN_IVA2_MASK (1 << 2) |
| c595713d TL |
428 | |
| 429 | /* PM_PWSTCTRL_PER specific bits */ | |
| 430 | ||
| 431 | /* PM_PWSTST_PER specific bits */ | |
| 432 | ||
| 433 | /* PM_PREPWSTST_PER specific bits */ | |
| 434 | ||
| 435 | /* RM_RSTST_EMU specific bits */ | |
| 436 | ||
| 437 | /* PM_PWSTST_EMU specific bits */ | |
| 438 | ||
| 439 | /* PRM_VC_SMPS_SA */ | |
| 440 | #define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16 | |
| 441 | #define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16) | |
| 442 | #define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0 | |
| 443 | #define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0) | |
| 444 | ||
| 445 | /* PRM_VC_SMPS_VOL_RA */ | |
| 446 | #define OMAP3430_VOLRA1_SHIFT 16 | |
| 447 | #define OMAP3430_VOLRA1_MASK (0xff << 16) | |
| 448 | #define OMAP3430_VOLRA0_SHIFT 0 | |
| 449 | #define OMAP3430_VOLRA0_MASK (0xff << 0) | |
| 450 | ||
| 451 | /* PRM_VC_SMPS_CMD_RA */ | |
| 452 | #define OMAP3430_CMDRA1_SHIFT 16 | |
| 453 | #define OMAP3430_CMDRA1_MASK (0xff << 16) | |
| 454 | #define OMAP3430_CMDRA0_SHIFT 0 | |
| 455 | #define OMAP3430_CMDRA0_MASK (0xff << 0) | |
| 456 | ||
| 457 | /* PRM_VC_CMD_VAL_0 specific bits */ | |
| 027d8ded JH |
458 | #define OMAP3430_VC_CMD_ON_SHIFT 24 |
| 459 | #define OMAP3430_VC_CMD_ON_MASK (0xFF << 24) | |
| 460 | #define OMAP3430_VC_CMD_ONLP_SHIFT 16 | |
| 461 | #define OMAP3430_VC_CMD_ONLP_MASK (0xFF << 16) | |
| 462 | #define OMAP3430_VC_CMD_RET_SHIFT 8 | |
| 463 | #define OMAP3430_VC_CMD_RET_MASK (0xFF << 8) | |
| 464 | #define OMAP3430_VC_CMD_OFF_SHIFT 0 | |
| 465 | #define OMAP3430_VC_CMD_OFF_MASK (0xFF << 0) | |
| c595713d TL |
466 | |
| 467 | /* PRM_VC_CMD_VAL_1 specific bits */ | |
| 468 | ||
| 469 | /* PRM_VC_CH_CONF */ | |
| 2bc4ef71 PW |
470 | #define OMAP3430_CMD1_MASK (1 << 20) |
| 471 | #define OMAP3430_RACEN1_MASK (1 << 19) | |
| 472 | #define OMAP3430_RAC1_MASK (1 << 18) | |
| 473 | #define OMAP3430_RAV1_MASK (1 << 17) | |
| 474 | #define OMAP3430_PRM_VC_CH_CONF_SA1_MASK (1 << 16) | |
| 475 | #define OMAP3430_CMD0_MASK (1 << 4) | |
| 476 | #define OMAP3430_RACEN0_MASK (1 << 3) | |
| 477 | #define OMAP3430_RAC0_MASK (1 << 2) | |
| 478 | #define OMAP3430_RAV0_MASK (1 << 1) | |
| 479 | #define OMAP3430_PRM_VC_CH_CONF_SA0_MASK (1 << 0) | |
| c595713d TL |
480 | |
| 481 | /* PRM_VC_I2C_CFG */ | |
| 2bc4ef71 PW |
482 | #define OMAP3430_HSMASTER_MASK (1 << 5) |
| 483 | #define OMAP3430_SREN_MASK (1 << 4) | |
| 484 | #define OMAP3430_HSEN_MASK (1 << 3) | |
| c595713d TL |
485 | #define OMAP3430_MCODE_SHIFT 0 |
| 486 | #define OMAP3430_MCODE_MASK (0x7 << 0) | |
| 487 | ||
| 488 | /* PRM_VC_BYPASS_VAL */ | |
| 2bc4ef71 | 489 | #define OMAP3430_VALID_MASK (1 << 24) |
| c595713d TL |
490 | #define OMAP3430_DATA_SHIFT 16 |
| 491 | #define OMAP3430_DATA_MASK (0xff << 16) | |
| 492 | #define OMAP3430_REGADDR_SHIFT 8 | |
| 493 | #define OMAP3430_REGADDR_MASK (0xff << 8) | |
| 494 | #define OMAP3430_SLAVEADDR_SHIFT 0 | |
| 495 | #define OMAP3430_SLAVEADDR_MASK (0x7f << 0) | |
| 496 | ||
| 497 | /* PRM_RSTCTRL */ | |
| 2bc4ef71 PW |
498 | #define OMAP3430_RST_DPLL3_MASK (1 << 2) |
| 499 | #define OMAP3430_RST_GS_MASK (1 << 1) | |
| c595713d TL |
500 | |
| 501 | /* PRM_RSTTIME */ | |
| 502 | #define OMAP3430_RSTTIME2_SHIFT 8 | |
| 503 | #define OMAP3430_RSTTIME2_MASK (0x1f << 8) | |
| 504 | #define OMAP3430_RSTTIME1_SHIFT 0 | |
| 505 | #define OMAP3430_RSTTIME1_MASK (0xff << 0) | |
| 506 | ||
| 507 | /* PRM_RSTST */ | |
| 2bc4ef71 PW |
508 | #define OMAP3430_ICECRUSHER_RST_MASK (1 << 10) |
| 509 | #define OMAP3430_ICEPICK_RST_MASK (1 << 9) | |
| 510 | #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_MASK (1 << 8) | |
| 511 | #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_MASK (1 << 7) | |
| 512 | #define OMAP3430_EXTERNAL_WARM_RST_MASK (1 << 6) | |
| 513 | #define OMAP3430_SECURE_WD_RST_MASK (1 << 5) | |
| 514 | #define OMAP3430_MPU_WD_RST_MASK (1 << 4) | |
| 515 | #define OMAP3430_SECURITY_VIOL_RST_MASK (1 << 3) | |
| 516 | #define OMAP3430_GLOBAL_SW_RST_MASK (1 << 1) | |
| 517 | #define OMAP3430_GLOBAL_COLD_RST_MASK (1 << 0) | |
| c595713d TL |
518 | |
| 519 | /* PRM_VOLTCTRL */ | |
| 2bc4ef71 PW |
520 | #define OMAP3430_SEL_VMODE_MASK (1 << 4) |
| 521 | #define OMAP3430_SEL_OFF_MASK (1 << 3) | |
| 522 | #define OMAP3430_AUTO_OFF_MASK (1 << 2) | |
| 523 | #define OMAP3430_AUTO_RET_MASK (1 << 1) | |
| 524 | #define OMAP3430_AUTO_SLEEP_MASK (1 << 0) | |
| c595713d TL |
525 | |
| 526 | /* PRM_SRAM_PCHARGE */ | |
| 527 | #define OMAP3430_PCHARGE_TIME_SHIFT 0 | |
| 528 | #define OMAP3430_PCHARGE_TIME_MASK (0xff << 0) | |
| 529 | ||
| 530 | /* PRM_CLKSRC_CTRL */ | |
| 531 | #define OMAP3430_SYSCLKDIV_SHIFT 6 | |
| 532 | #define OMAP3430_SYSCLKDIV_MASK (0x3 << 6) | |
| 533 | #define OMAP3430_AUTOEXTCLKMODE_SHIFT 3 | |
| 534 | #define OMAP3430_AUTOEXTCLKMODE_MASK (0x3 << 3) | |
| 535 | #define OMAP3430_SYSCLKSEL_SHIFT 0 | |
| 536 | #define OMAP3430_SYSCLKSEL_MASK (0x3 << 0) | |
| 537 | ||
| 538 | /* PRM_VOLTSETUP1 */ | |
| 539 | #define OMAP3430_SETUP_TIME2_SHIFT 16 | |
| 540 | #define OMAP3430_SETUP_TIME2_MASK (0xffff << 16) | |
| 541 | #define OMAP3430_SETUP_TIME1_SHIFT 0 | |
| 542 | #define OMAP3430_SETUP_TIME1_MASK (0xffff << 0) | |
| 543 | ||
| 544 | /* PRM_VOLTOFFSET */ | |
| 545 | #define OMAP3430_OFFSET_TIME_SHIFT 0 | |
| 546 | #define OMAP3430_OFFSET_TIME_MASK (0xffff << 0) | |
| 547 | ||
| 548 | /* PRM_CLKSETUP */ | |
| 549 | #define OMAP3430_SETUP_TIME_SHIFT 0 | |
| 550 | #define OMAP3430_SETUP_TIME_MASK (0xffff << 0) | |
| 551 | ||
| 552 | /* PRM_POLCTRL */ | |
| 2bc4ef71 PW |
553 | #define OMAP3430_OFFMODE_POL_MASK (1 << 3) |
| 554 | #define OMAP3430_CLKOUT_POL_MASK (1 << 2) | |
| 555 | #define OMAP3430_CLKREQ_POL_MASK (1 << 1) | |
| 556 | #define OMAP3430_EXTVOL_POL_MASK (1 << 0) | |
| c595713d TL |
557 | |
| 558 | /* PRM_VOLTSETUP2 */ | |
| 559 | #define OMAP3430_OFFMODESETUPTIME_SHIFT 0 | |
| 560 | #define OMAP3430_OFFMODESETUPTIME_MASK (0xffff << 0) | |
| 561 | ||
| 562 | /* PRM_VP1_CONFIG specific bits */ | |
| 563 | ||
| 564 | /* PRM_VP1_VSTEPMIN specific bits */ | |
| 565 | ||
| 566 | /* PRM_VP1_VSTEPMAX specific bits */ | |
| 567 | ||
| 568 | /* PRM_VP1_VLIMITTO specific bits */ | |
| 569 | ||
| 570 | /* PRM_VP1_VOLTAGE specific bits */ | |
| 571 | ||
| 572 | /* PRM_VP1_STATUS specific bits */ | |
| 573 | ||
| 574 | /* PRM_VP2_CONFIG specific bits */ | |
| 575 | ||
| 576 | /* PRM_VP2_VSTEPMIN specific bits */ | |
| 577 | ||
| 578 | /* PRM_VP2_VSTEPMAX specific bits */ | |
| 579 | ||
| 580 | /* PRM_VP2_VLIMITTO specific bits */ | |
| 581 | ||
| 582 | /* PRM_VP2_VOLTAGE specific bits */ | |
| 583 | ||
| 584 | /* PRM_VP2_STATUS specific bits */ | |
| 585 | ||
| 586 | /* RM_RSTST_NEON specific bits */ | |
| 587 | ||
| 588 | /* PM_WKDEP_NEON specific bits */ | |
| 589 | ||
| 590 | /* PM_PWSTCTRL_NEON specific bits */ | |
| 591 | ||
| 592 | /* PM_PWSTST_NEON specific bits */ | |
| 593 | ||
| 594 | /* PM_PREPWSTST_NEON specific bits */ | |
| 595 | ||
| 596 | #endif |