projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 234f0c4c RN |
1 | /* |
| 2 | * OMAP44xx Power Management register bits | |
| 3 | * | |
| 568997cf RN |
4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. |
| 5 | * Copyright (C) 2009-2010 Nokia Corporation | |
| 234f0c4c RN |
6 | * |
| 7 | * Paul Walmsley (paul@pwsan.com) | |
| 8 | * Rajendra Nayak (rnayak@ti.com) | |
| 9 | * Benoit Cousson (b-cousson@ti.com) | |
| 10 | * | |
| 11 | * This file is automatically generated from the OMAP hardware databases. | |
| 12 | * We respectfully ask that any modifications to this file be coordinated | |
| 13 | * with the public linux-omap@vger.kernel.org mailing list and the | |
| 14 | * authors above to ensure that the autogeneration scripts are kept | |
| 15 | * up-to-date with the file contents. | |
| 16 | * | |
| 17 | * This program is free software; you can redistribute it and/or modify | |
| 18 | * it under the terms of the GNU General Public License version 2 as | |
| 19 | * published by the Free Software Foundation. | |
| 20 | */ | |
| 21 | ||
| 22 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H | |
| 23 | #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H | |
| 24 | ||
| 568997cf | 25 | #define OMAP4430_C2C_RST_SHIFT 10 |
| 568997cf | 26 | #define OMAP4430_CMDRA_VDD_CORE_L_MASK (0xff << 0) |
| 568997cf | 27 | #define OMAP4430_CMDRA_VDD_IVA_L_MASK (0xff << 8) |
| 568997cf | 28 | #define OMAP4430_CMDRA_VDD_MPU_L_MASK (0xff << 16) |
| 56ef28ac | 29 | #define OMAP4430_DATA_SHIFT 16 |
| 568997cf | 30 | #define OMAP4430_ERRORGAIN_MASK (0xff << 16) |
| 568997cf | 31 | #define OMAP4430_ERROROFFSET_MASK (0xff << 24) |
| 56ef28ac | 32 | #define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5 |
| 568997cf | 33 | #define OMAP4430_FORCEUPDATE_MASK (1 << 1) |
| 56ef28ac | 34 | #define OMAP4430_GLOBAL_COLD_RST_SHIFT 0 |
| 56ef28ac | 35 | #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 |
| 568997cf | 36 | #define OMAP4430_GLOBAL_WUEN_MASK (1 << 16) |
| 568997cf | 37 | #define OMAP4430_HSMCODE_MASK (0x7 << 0) |
| 102bcb6e | 38 | #define OMAP4430_SRMODEEN_MASK (1 << 4) |
| 568997cf | 39 | #define OMAP4430_HSMODEEN_MASK (1 << 3) |
| 56ef28ac | 40 | #define OMAP4430_HSSCLL_SHIFT 24 |
| 56ef28ac | 41 | #define OMAP4430_ICEPICK_RST_SHIFT 9 |
| 568997cf | 42 | #define OMAP4430_INITVDD_MASK (1 << 2) |
| 568997cf | 43 | #define OMAP4430_INITVOLTAGE_MASK (0xff << 8) |
| 568997cf RN |
44 | #define OMAP4430_LASTPOWERSTATEENTERED_SHIFT 24 |
| 45 | #define OMAP4430_LASTPOWERSTATEENTERED_MASK (0x3 << 24) | |
| 56ef28ac | 46 | #define OMAP4430_LOGICRETSTATE_SHIFT 2 |
| 568997cf | 47 | #define OMAP4430_LOGICRETSTATE_MASK (1 << 2) |
| 56ef28ac | 48 | #define OMAP4430_LOGICSTATEST_SHIFT 2 |
| 568997cf | 49 | #define OMAP4430_LOGICSTATEST_MASK (1 << 2) |
| 568997cf | 50 | #define OMAP4430_LOSTCONTEXT_DFF_MASK (1 << 0) |
| 568997cf | 51 | #define OMAP4430_LOSTMEM_AESSMEM_MASK (1 << 8) |
| 56ef28ac | 52 | #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4 |
| 568997cf | 53 | #define OMAP4430_LOWPOWERSTATECHANGE_MASK (1 << 4) |
| 56ef28ac | 54 | #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2 |
| 56ef28ac | 55 | #define OMAP4430_MPU_WDT_RST_SHIFT 3 |
| 568997cf | 56 | #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24) |
| 568997cf | 57 | #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK (1 << 12) |
| 568997cf | 58 | #define OMAP4430_OCP_NRET_BANK_STATEST_MASK (0x3 << 12) |
| 56ef28ac | 59 | #define OMAP4430_OFF_SHIFT 0 |
| 56ef28ac | 60 | #define OMAP4430_ON_SHIFT 24 |
| 568997cf | 61 | #define OMAP4430_ON_MASK (0xff << 24) |
| 56ef28ac | 62 | #define OMAP4430_ONLP_SHIFT 16 |
| 56ef28ac | 63 | #define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16 |
| 56ef28ac | 64 | #define OMAP4430_RAMP_UP_COUNT_SHIFT 0 |
| 56ef28ac | 65 | #define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8 |
| 56ef28ac | 66 | #define OMAP4430_REGADDR_SHIFT 8 |
| 56ef28ac | 67 | #define OMAP4430_RET_SHIFT 8 |
| 568997cf | 68 | #define OMAP4430_RST_GLOBAL_WARM_SW_MASK (1 << 0) |
| 56ef28ac | 69 | #define OMAP4430_SA_VDD_CORE_L_SHIFT 0 |
| 568997cf | 70 | #define OMAP4430_SA_VDD_CORE_L_0_6_MASK (0x7f << 0) |
| 56ef28ac | 71 | #define OMAP4430_SA_VDD_IVA_L_SHIFT 8 |
| 568997cf | 72 | #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK (0x7f << 8) |
| 56ef28ac | 73 | #define OMAP4430_SA_VDD_MPU_L_SHIFT 16 |
| 568997cf | 74 | #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK (0x7f << 16) |
| 56ef28ac | 75 | #define OMAP4430_SCLH_SHIFT 0 |
| 56ef28ac | 76 | #define OMAP4430_SCLL_SHIFT 8 |
| 56ef28ac | 77 | #define OMAP4430_SECURE_WDT_RST_SHIFT 4 |
| 56ef28ac | 78 | #define OMAP4430_SLAVEADDR_SHIFT 0 |
| 56ef28ac | 79 | #define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8 |
| 56ef28ac | 80 | #define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8 |
| 56ef28ac | 81 | #define OMAP4430_TIMEOUT_SHIFT 0 |
| 568997cf | 82 | #define OMAP4430_TIMEOUTEN_MASK (1 << 3) |
| 568997cf | 83 | #define OMAP4430_VALID_MASK (1 << 24) |
| 56ef28ac | 84 | #define OMAP4430_VDDMAX_SHIFT 24 |
| 56ef28ac | 85 | #define OMAP4430_VDDMIN_SHIFT 16 |
| 56ef28ac | 86 | #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8 |
| 56ef28ac | 87 | #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7 |
| 56ef28ac | 88 | #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6 |
| 568997cf | 89 | #define OMAP4430_VOLRA_VDD_CORE_L_MASK (0xff << 0) |
| 568997cf | 90 | #define OMAP4430_VOLRA_VDD_IVA_L_MASK (0xff << 8) |
| 568997cf | 91 | #define OMAP4430_VOLRA_VDD_MPU_L_MASK (0xff << 16) |
| 568997cf | 92 | #define OMAP4430_VPENABLE_MASK (1 << 0) |
| 568997cf | 93 | #define OMAP4430_VPVOLTAGE_MASK (0xff << 0) |
| 568997cf | 94 | #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK (1 << 21) |
| 568997cf | 95 | #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK (1 << 29) |
| 568997cf | 96 | #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK (1 << 5) |
| 56ef28ac | 97 | #define OMAP4430_VSTEPMAX_SHIFT 0 |
| 56ef28ac | 98 | #define OMAP4430_VSTEPMIN_SHIFT 0 |
| 568997cf | 99 | #define OMAP4430_WUCLK_CTRL_MASK (1 << 8) |
| 56ef28ac | 100 | #define OMAP4430_WUCLK_STATUS_SHIFT 9 |
| 568997cf | 101 | #define OMAP4430_WUCLK_STATUS_MASK (1 << 9) |
| 234f0c4c | 102 | #endif |