[deliverable/linux.git] / arch / arm / mach-omap2 / prm.h

/*
 * OMAP2/3/4 Power/Reset Management (PRM) bitfield definitions
 *
 * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
 * Copyright (C) 2010 Nokia Corporation
 *
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
#define __ARCH_ARM_MACH_OMAP2_PRM_H

#include "prcm-common.h"

# ifndef __ASSEMBLER__
extern void __iomem *prm_base;
extern u16 prm_features;
extern void omap2_set_globals_prm(void __iomem *prm);
int omap_prcm_init(void);
int omap2_prm_base_init(void);
# endif

/*
 * prm_features flag values
 *
 * PRM_HAS_IO_WAKEUP: has IO wakeup capability
 * PRM_HAS_VOLTAGE: has voltage domains
 */
#define PRM_HAS_IO_WAKEUP	(1 << 0)
#define PRM_HAS_VOLTAGE		(1 << 1)

/*
 * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP
 * module to softreset
 */
#define MAX_MODULE_SOFTRESET_WAIT		10000

/*
 * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
 * submodule to exit hardreset
 */
#define MAX_MODULE_HARDRESET_WAIT		10000

/*
 * Register bitfields
 */

/*
 * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
 *
 * 2430: PM_PWSTST_MDM
 *
 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
 *	 PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
 *	 PM_PWSTST_NEON
 */
#define OMAP_INTRANSITION_MASK				(1 << 20)


/*
 * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
 *
 * 2430: PM_PWSTST_MDM
 *
 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
 *	 PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
 *	 PM_PWSTST_NEON
 */
#define OMAP_POWERSTATEST_SHIFT				0
#define OMAP_POWERSTATEST_MASK				(0x3 << 0)

/*
 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
 *       PM_PWSTCTRL_DSP, PM_PWSTST_MPU
 *
 * 2430: PM_PWSTCTRL_MDM shared bits
 *
 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
 *	 PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
 *	 PM_PWSTCTRL_NEON shared bits
 */
#define OMAP_POWERSTATE_SHIFT				0
#define OMAP_POWERSTATE_MASK				(0x3 << 0)

/*
 * Standardized OMAP reset source bits
 *
 * To the extent these happen to match the hardware register bit
 * shifts, it's purely coincidental.  Used by omap-wdt.c.
 * OMAP_UNKNOWN_RST_SRC_ID_SHIFT is a special value, used whenever
 * there are any bits remaining in the global PRM_RSTST register that
 * haven't been identified, or when the PRM code for the current SoC
 * doesn't know how to interpret the register.
 */
#define OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT			0
#define OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT			1
#define OMAP_SECU_VIOL_RST_SRC_ID_SHIFT				2
#define OMAP_MPU_WD_RST_SRC_ID_SHIFT				3
#define OMAP_SECU_WD_RST_SRC_ID_SHIFT				4
#define OMAP_EXTWARM_RST_SRC_ID_SHIFT				5
#define OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT			6
#define OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT			7
#define OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT			8
#define OMAP_ICEPICK_RST_SRC_ID_SHIFT				9
#define OMAP_ICECRUSHER_RST_SRC_ID_SHIFT			10
#define OMAP_C2C_RST_SRC_ID_SHIFT				11
#define OMAP_UNKNOWN_RST_SRC_ID_SHIFT				12

#ifndef __ASSEMBLER__

/**
 * struct prm_reset_src_map - map register bitshifts to standard bitshifts
 * @reg_shift: bitshift in the PRM reset source register
 * @std_shift: bitshift equivalent in the standard reset source list
 *
 * The fields are signed because -1 is used as a terminator.
 */
struct prm_reset_src_map {
	s8 reg_shift;
	s8 std_shift;
};

/**
 * struct prm_ll_data - fn ptrs to per-SoC PRM function implementations
 * @read_reset_sources: ptr to the SoC PRM-specific get_reset_source impl
 * @was_any_context_lost_old: ptr to the SoC PRM context loss test fn
 * @clear_context_loss_flags_old: ptr to the SoC PRM context loss flag clear fn
 * @late_init: ptr to the late init function
 * @assert_hardreset: ptr to the SoC PRM hardreset assert impl
 * @deassert_hardreset: ptr to the SoC PRM hardreset deassert impl
 *
 * XXX @was_any_context_lost_old and @clear_context_loss_flags_old are
 * deprecated.
 */
struct prm_ll_data {
	u32 (*read_reset_sources)(void);
	bool (*was_any_context_lost_old)(u8 part, s16 inst, u16 idx);
	void (*clear_context_loss_flags_old)(u8 part, s16 inst, u16 idx);
	int (*late_init)(void);
	int (*assert_hardreset)(u8 shift, u8 part, s16 prm_mod, u16 offset);
	int (*deassert_hardreset)(u8 shift, u8 st_shift, u8 part, s16 prm_mod,
				  u16 offset, u16 st_offset);
	int (*is_hardreset_asserted)(u8 shift, u8 part, s16 prm_mod,
				     u16 offset);
	void (*reset_system)(void);
	int (*clear_mod_irqs)(s16 module, u8 regs, u32 wkst_mask);
	u32 (*vp_check_txdone)(u8 vp_id);
	void (*vp_clear_txdone)(u8 vp_id);
};

extern int prm_register(struct prm_ll_data *pld);
extern int prm_unregister(struct prm_ll_data *pld);

int omap_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, u16 offset);
int omap_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 prm_mod,
				u16 offset, u16 st_offset);
int omap_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset);
extern u32 prm_read_reset_sources(void);
extern bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx);
extern void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx);
void omap_prm_reset_system(void);

void omap_prm_reconfigure_io_chain(void);
int omap_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);

/*
 * Voltage Processor (VP) identifiers
 */
#define OMAP3_VP_VDD_MPU_ID	0
#define OMAP3_VP_VDD_CORE_ID	1
#define OMAP4_VP_VDD_CORE_ID	0
#define OMAP4_VP_VDD_IVA_ID	1
#define OMAP4_VP_VDD_MPU_ID	2

u32 omap_prm_vp_check_txdone(u8 vp_id);
void omap_prm_vp_clear_txdone(u8 vp_id);

#endif


#endif
Commit	Line	Data
69d88a00	1	/*
59fb659b	2	* OMAP2/3/4 Power/Reset Management (PRM) bitfield definitions
69d88a00	3	*
d9a16f9a	4	* Copyright (C) 2007-2009, 2012 Texas Instruments, Inc.
0be1621a	5	* Copyright (C) 2010 Nokia Corporation
69d88a00	6	*
59fb659b	7	* Paul Walmsley
69d88a00 PW	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*/
59fb659b PW	13	#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
59fb659b PW	14	#define __ARCH_ARM_MACH_OMAP2_PRM_H
69d88a00 PW	15
	16	#include "prcm-common.h"
	17
d9a16f9a PW	18	# ifndef __ASSEMBLER__
d9a16f9a PW	19	extern void __iomem *prm_base;
2541d15f	20	extern u16 prm_features;
d9a16f9a	21	extern void omap2_set_globals_prm(void __iomem *prm);
3a1a388e	22	int omap_prcm_init(void);
ae521d4d	23	int omap2_prm_base_init(void);
d9a16f9a PW	24	# endif
d9a16f9a PW	25
2541d15f TK	26	/*
	27	* prm_features flag values
	28	*
	29	* PRM_HAS_IO_WAKEUP: has IO wakeup capability
	30	* PRM_HAS_VOLTAGE: has voltage domains
	31	*/
	32	#define PRM_HAS_IO_WAKEUP (1 << 0)
3381eb47	33	#define PRM_HAS_VOLTAGE (1 << 1)
b13159af PW	34
	35	/*
	36	* MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP
	37	* module to softreset
	38	*/
	39	#define MAX_MODULE_SOFTRESET_WAIT 10000
	40
	41	/*
	42	* MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP
	43	* submodule to exit hardreset
	44	*/
	45	#define MAX_MODULE_HARDRESET_WAIT 10000
	46
	47	/*
	48	* Register bitfields
	49	*/
	50
69d88a00 PW	51	/*
	52	* 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
	53	*
	54	* 2430: PM_PWSTST_MDM
	55	*
	56	* 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
	57	* PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
	58	* PM_PWSTST_NEON
	59	*/
2fd0f75c	60	#define OMAP_INTRANSITION_MASK (1 << 20)
69d88a00 PW	61
	62
	63	/*
	64	* 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
	65	*
	66	* 2430: PM_PWSTST_MDM
	67	*
	68	* 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
	69	* PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
	70	* PM_PWSTST_NEON
	71	*/
	72	#define OMAP_POWERSTATEST_SHIFT 0
	73	#define OMAP_POWERSTATEST_MASK (0x3 << 0)
	74
69d88a00 PW	75	/*
	76	* 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
	77	* PM_PWSTCTRL_DSP, PM_PWSTST_MPU
	78	*
	79	* 2430: PM_PWSTCTRL_MDM shared bits
	80	*
	81	* 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
	82	* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
	83	* PM_PWSTCTRL_NEON shared bits
	84	*/
	85	#define OMAP_POWERSTATE_SHIFT 0
	86	#define OMAP_POWERSTATE_MASK (0x3 << 0)
	87
2bb2a5d3 PW	88	/*
	89	* Standardized OMAP reset source bits
	90	*
	91	* To the extent these happen to match the hardware register bit
	92	* shifts, it's purely coincidental. Used by omap-wdt.c.
	93	* OMAP_UNKNOWN_RST_SRC_ID_SHIFT is a special value, used whenever
	94	* there are any bits remaining in the global PRM_RSTST register that
	95	* haven't been identified, or when the PRM code for the current SoC
	96	* doesn't know how to interpret the register.
	97	*/
	98	#define OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT 0
	99	#define OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT 1
	100	#define OMAP_SECU_VIOL_RST_SRC_ID_SHIFT 2
	101	#define OMAP_MPU_WD_RST_SRC_ID_SHIFT 3
	102	#define OMAP_SECU_WD_RST_SRC_ID_SHIFT 4
	103	#define OMAP_EXTWARM_RST_SRC_ID_SHIFT 5
	104	#define OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT 6
	105	#define OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT 7
	106	#define OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT 8
	107	#define OMAP_ICEPICK_RST_SRC_ID_SHIFT 9
	108	#define OMAP_ICECRUSHER_RST_SRC_ID_SHIFT 10
	109	#define OMAP_C2C_RST_SRC_ID_SHIFT 11
	110	#define OMAP_UNKNOWN_RST_SRC_ID_SHIFT 12
	111
e24c3573 PW	112	#ifndef __ASSEMBLER__
e24c3573 PW	113
2bb2a5d3 PW	114	/**
	115	* struct prm_reset_src_map - map register bitshifts to standard bitshifts
	116	* @reg_shift: bitshift in the PRM reset source register
	117	* @std_shift: bitshift equivalent in the standard reset source list
	118	*
	119	* The fields are signed because -1 is used as a terminator.
	120	*/
	121	struct prm_reset_src_map {
	122	s8 reg_shift;
	123	s8 std_shift;
	124	};
	125
e24c3573 PW	126	/**
e24c3573 PW	127	* struct prm_ll_data - fn ptrs to per-SoC PRM function implementations
e6d3a8b0 RN	128	* @read_reset_sources: ptr to the SoC PRM-specific get_reset_source impl
	129	* @was_any_context_lost_old: ptr to the SoC PRM context loss test fn
	130	* @clear_context_loss_flags_old: ptr to the SoC PRM context loss flag clear fn
b550e47f	131	* @late_init: ptr to the late init function
efd44dc3	132	* @assert_hardreset: ptr to the SoC PRM hardreset assert impl
37fb59d7	133	* @deassert_hardreset: ptr to the SoC PRM hardreset deassert impl
e6d3a8b0 RN	134	*
	135	* XXX @was_any_context_lost_old and @clear_context_loss_flags_old are
	136	* deprecated.
e24c3573	137	*/
2bb2a5d3 PW	138	struct prm_ll_data {
2bb2a5d3 PW	139	u32 (*read_reset_sources)(void);
e6d3a8b0 RN	140	bool (*was_any_context_lost_old)(u8 part, s16 inst, u16 idx);
e6d3a8b0 RN	141	void (*clear_context_loss_flags_old)(u8 part, s16 inst, u16 idx);
b550e47f	142	int (*late_init)(void);
efd44dc3	143	int (*assert_hardreset)(u8 shift, u8 part, s16 prm_mod, u16 offset);
37fb59d7 TK	144	int (*deassert_hardreset)(u8 shift, u8 st_shift, u8 part, s16 prm_mod,
	145	u16 offset, u16 st_offset);
	146	int (*is_hardreset_asserted)(u8 shift, u8 part, s16 prm_mod,
	147	u16 offset);
61c8621e	148	void (*reset_system)(void);
9cb6d363	149	int (*clear_mod_irqs)(s16 module, u8 regs, u32 wkst_mask);
e9f1ddcd TK	150	u32 (*vp_check_txdone)(u8 vp_id);
e9f1ddcd TK	151	void (*vp_clear_txdone)(u8 vp_id);
2bb2a5d3	152	};
e24c3573 PW	153
	154	extern int prm_register(struct prm_ll_data *pld);
	155	extern int prm_unregister(struct prm_ll_data *pld);
	156
efd44dc3	157	int omap_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, u16 offset);
37fb59d7 TK	158	int omap_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 prm_mod,
37fb59d7 TK	159	u16 offset, u16 st_offset);
1bc28b34	160	int omap_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset);
2bb2a5d3	161	extern u32 prm_read_reset_sources(void);
e6d3a8b0 RN	162	extern bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx);
e6d3a8b0 RN	163	extern void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx);
61c8621e	164	void omap_prm_reset_system(void);
2bb2a5d3	165
4984eeaf	166	void omap_prm_reconfigure_io_chain(void);
9cb6d363	167	int omap_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask);
4984eeaf	168
e9f1ddcd TK	169	/*
	170	* Voltage Processor (VP) identifiers
	171	*/
	172	#define OMAP3_VP_VDD_MPU_ID 0
	173	#define OMAP3_VP_VDD_CORE_ID 1
	174	#define OMAP4_VP_VDD_CORE_ID 0
	175	#define OMAP4_VP_VDD_IVA_ID 1
	176	#define OMAP4_VP_VDD_MPU_ID 2
	177
	178	u32 omap_prm_vp_check_txdone(u8 vp_id);
	179	void omap_prm_vp_clear_txdone(u8 vp_id);
	180
e24c3573	181	#endif
69d88a00	182
2bb2a5d3	183
69d88a00	184	#endif