Commit | Line | Data |
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69d88a00 | 1 | /* |
59fb659b | 2 | * OMAP2/3/4 Power/Reset Management (PRM) bitfield definitions |
69d88a00 | 3 | * |
d9a16f9a | 4 | * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc. |
0be1621a | 5 | * Copyright (C) 2010 Nokia Corporation |
69d88a00 | 6 | * |
59fb659b | 7 | * Paul Walmsley |
69d88a00 PW |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
59fb659b PW |
13 | #ifndef __ARCH_ARM_MACH_OMAP2_PRM_H |
14 | #define __ARCH_ARM_MACH_OMAP2_PRM_H | |
69d88a00 PW |
15 | |
16 | #include "prcm-common.h" | |
17 | ||
d9a16f9a PW |
18 | # ifndef __ASSEMBLER__ |
19 | extern void __iomem *prm_base; | |
2541d15f | 20 | extern u16 prm_features; |
d9a16f9a | 21 | extern void omap2_set_globals_prm(void __iomem *prm); |
943a63a4 | 22 | int of_prcm_init(void); |
d9a16f9a PW |
23 | # endif |
24 | ||
2541d15f TK |
25 | /* |
26 | * prm_features flag values | |
27 | * | |
28 | * PRM_HAS_IO_WAKEUP: has IO wakeup capability | |
29 | * PRM_HAS_VOLTAGE: has voltage domains | |
30 | */ | |
31 | #define PRM_HAS_IO_WAKEUP (1 << 0) | |
3381eb47 | 32 | #define PRM_HAS_VOLTAGE (1 << 1) |
b13159af PW |
33 | |
34 | /* | |
35 | * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP | |
36 | * module to softreset | |
37 | */ | |
38 | #define MAX_MODULE_SOFTRESET_WAIT 10000 | |
39 | ||
40 | /* | |
41 | * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP | |
42 | * submodule to exit hardreset | |
43 | */ | |
44 | #define MAX_MODULE_HARDRESET_WAIT 10000 | |
45 | ||
46 | /* | |
47 | * Register bitfields | |
48 | */ | |
49 | ||
69d88a00 PW |
50 | /* |
51 | * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP | |
52 | * | |
53 | * 2430: PM_PWSTST_MDM | |
54 | * | |
55 | * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX, | |
56 | * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU, | |
57 | * PM_PWSTST_NEON | |
58 | */ | |
2fd0f75c | 59 | #define OMAP_INTRANSITION_MASK (1 << 20) |
69d88a00 PW |
60 | |
61 | ||
62 | /* | |
63 | * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP | |
64 | * | |
65 | * 2430: PM_PWSTST_MDM | |
66 | * | |
67 | * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX, | |
68 | * PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU, | |
69 | * PM_PWSTST_NEON | |
70 | */ | |
71 | #define OMAP_POWERSTATEST_SHIFT 0 | |
72 | #define OMAP_POWERSTATEST_MASK (0x3 << 0) | |
73 | ||
69d88a00 PW |
74 | /* |
75 | * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, | |
76 | * PM_PWSTCTRL_DSP, PM_PWSTST_MPU | |
77 | * | |
78 | * 2430: PM_PWSTCTRL_MDM shared bits | |
79 | * | |
80 | * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, | |
81 | * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER, | |
82 | * PM_PWSTCTRL_NEON shared bits | |
83 | */ | |
84 | #define OMAP_POWERSTATE_SHIFT 0 | |
85 | #define OMAP_POWERSTATE_MASK (0x3 << 0) | |
86 | ||
2bb2a5d3 PW |
87 | /* |
88 | * Standardized OMAP reset source bits | |
89 | * | |
90 | * To the extent these happen to match the hardware register bit | |
91 | * shifts, it's purely coincidental. Used by omap-wdt.c. | |
92 | * OMAP_UNKNOWN_RST_SRC_ID_SHIFT is a special value, used whenever | |
93 | * there are any bits remaining in the global PRM_RSTST register that | |
94 | * haven't been identified, or when the PRM code for the current SoC | |
95 | * doesn't know how to interpret the register. | |
96 | */ | |
97 | #define OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT 0 | |
98 | #define OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT 1 | |
99 | #define OMAP_SECU_VIOL_RST_SRC_ID_SHIFT 2 | |
100 | #define OMAP_MPU_WD_RST_SRC_ID_SHIFT 3 | |
101 | #define OMAP_SECU_WD_RST_SRC_ID_SHIFT 4 | |
102 | #define OMAP_EXTWARM_RST_SRC_ID_SHIFT 5 | |
103 | #define OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT 6 | |
104 | #define OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT 7 | |
105 | #define OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT 8 | |
106 | #define OMAP_ICEPICK_RST_SRC_ID_SHIFT 9 | |
107 | #define OMAP_ICECRUSHER_RST_SRC_ID_SHIFT 10 | |
108 | #define OMAP_C2C_RST_SRC_ID_SHIFT 11 | |
109 | #define OMAP_UNKNOWN_RST_SRC_ID_SHIFT 12 | |
110 | ||
e24c3573 PW |
111 | #ifndef __ASSEMBLER__ |
112 | ||
2bb2a5d3 PW |
113 | /** |
114 | * struct prm_reset_src_map - map register bitshifts to standard bitshifts | |
115 | * @reg_shift: bitshift in the PRM reset source register | |
116 | * @std_shift: bitshift equivalent in the standard reset source list | |
117 | * | |
118 | * The fields are signed because -1 is used as a terminator. | |
119 | */ | |
120 | struct prm_reset_src_map { | |
121 | s8 reg_shift; | |
122 | s8 std_shift; | |
123 | }; | |
124 | ||
e24c3573 PW |
125 | /** |
126 | * struct prm_ll_data - fn ptrs to per-SoC PRM function implementations | |
e6d3a8b0 RN |
127 | * @read_reset_sources: ptr to the SoC PRM-specific get_reset_source impl |
128 | * @was_any_context_lost_old: ptr to the SoC PRM context loss test fn | |
129 | * @clear_context_loss_flags_old: ptr to the SoC PRM context loss flag clear fn | |
b550e47f | 130 | * @late_init: ptr to the late init function |
efd44dc3 | 131 | * @assert_hardreset: ptr to the SoC PRM hardreset assert impl |
37fb59d7 | 132 | * @deassert_hardreset: ptr to the SoC PRM hardreset deassert impl |
e6d3a8b0 RN |
133 | * |
134 | * XXX @was_any_context_lost_old and @clear_context_loss_flags_old are | |
135 | * deprecated. | |
e24c3573 | 136 | */ |
2bb2a5d3 PW |
137 | struct prm_ll_data { |
138 | u32 (*read_reset_sources)(void); | |
e6d3a8b0 RN |
139 | bool (*was_any_context_lost_old)(u8 part, s16 inst, u16 idx); |
140 | void (*clear_context_loss_flags_old)(u8 part, s16 inst, u16 idx); | |
b550e47f | 141 | int (*late_init)(void); |
efd44dc3 | 142 | int (*assert_hardreset)(u8 shift, u8 part, s16 prm_mod, u16 offset); |
37fb59d7 TK |
143 | int (*deassert_hardreset)(u8 shift, u8 st_shift, u8 part, s16 prm_mod, |
144 | u16 offset, u16 st_offset); | |
145 | int (*is_hardreset_asserted)(u8 shift, u8 part, s16 prm_mod, | |
146 | u16 offset); | |
2bb2a5d3 | 147 | }; |
e24c3573 PW |
148 | |
149 | extern int prm_register(struct prm_ll_data *pld); | |
150 | extern int prm_unregister(struct prm_ll_data *pld); | |
151 | ||
efd44dc3 | 152 | int omap_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, u16 offset); |
37fb59d7 TK |
153 | int omap_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 prm_mod, |
154 | u16 offset, u16 st_offset); | |
1bc28b34 | 155 | int omap_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset); |
2bb2a5d3 | 156 | extern u32 prm_read_reset_sources(void); |
e6d3a8b0 RN |
157 | extern bool prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx); |
158 | extern void prm_clear_context_loss_flags_old(u8 part, s16 inst, u16 idx); | |
2bb2a5d3 | 159 | |
e24c3573 | 160 | #endif |
69d88a00 | 161 | |
2bb2a5d3 | 162 | |
69d88a00 | 163 | #endif |