[deliverable/linux.git] / arch / arm / mach-omap2 / prm2xxx.c

/*
 * OMAP2xxx PRM module functions
 *
 * Copyright (C) 2010-2012 Texas Instruments, Inc.
 * Copyright (C) 2010 Nokia Corporation
 * Benoît Cousson
 * Paul Walmsley
 * Rajendra Nayak <rnayak@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/irq.h>

#include "common.h"
#include <plat/cpu.h>

#include "vp.h"
#include "powerdomain.h"
#include "clockdomain.h"
#include "prm2xxx.h"
#include "cm2xxx_3xxx.h"
#include "prm-regbits-24xx.h"

/*
 * omap2xxx_prm_reset_src_map - map from bits in the PRM_RSTST_WKUP
 *   hardware register (which are specific to the OMAP2xxx SoCs) to
 *   reset source ID bit shifts (which is an OMAP SoC-independent
 *   enumeration)
 */
static struct prm_reset_src_map omap2xxx_prm_reset_src_map[] = {
	{ OMAP_GLOBALCOLD_RST_SHIFT, OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
	{ OMAP_GLOBALWARM_RST_SHIFT, OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
	{ OMAP24XX_SECU_VIOL_RST_SHIFT, OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
	{ OMAP24XX_MPU_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
	{ OMAP24XX_SECU_WD_RST_SHIFT, OMAP_SECU_WD_RST_SRC_ID_SHIFT },
	{ OMAP24XX_EXTWMPU_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT },
	{ -1, -1 },
};

/**
 * omap2xxx_prm_read_reset_sources - return the last SoC reset source
 *
 * Return a u32 representing the last reset sources of the SoC.  The
 * returned reset source bits are standardized across OMAP SoCs.
 */
static u32 omap2xxx_prm_read_reset_sources(void)
{
	struct prm_reset_src_map *p;
	u32 r = 0;
	u32 v;

	v = omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST);

	p = omap2xxx_prm_reset_src_map;
	while (p->reg_shift >= 0 && p->std_shift >= 0) {
		if (v & (1 << p->reg_shift))
			r |= 1 << p->std_shift;
		p++;
	}

	return r;
}

/**
 * omap2xxx_prm_dpll_reset - use DPLL reset to reboot the OMAP SoC
 *
 * Set the DPLL reset bit, which should reboot the SoC.  This is the
 * recommended way to restart the SoC.  No return value.
 */
void omap2xxx_prm_dpll_reset(void)
{
	omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, WKUP_MOD,
				   OMAP2_RM_RSTCTRL);
	/* OCP barrier */
	omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTCTRL);
}

int omap2xxx_clkdm_sleep(struct clockdomain *clkdm)
{
	omap2_prm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
				   clkdm->pwrdm.ptr->prcm_offs,
				   OMAP2_PM_PWSTCTRL);
	return 0;
}

int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm)
{
	omap2_prm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
				     clkdm->pwrdm.ptr->prcm_offs,
				     OMAP2_PM_PWSTCTRL);
	return 0;
}

struct pwrdm_ops omap2_pwrdm_operations = {
	.pwrdm_set_next_pwrst	= omap2_pwrdm_set_next_pwrst,
	.pwrdm_read_next_pwrst	= omap2_pwrdm_read_next_pwrst,
	.pwrdm_read_pwrst	= omap2_pwrdm_read_pwrst,
	.pwrdm_set_logic_retst	= omap2_pwrdm_set_logic_retst,
	.pwrdm_set_mem_onst	= omap2_pwrdm_set_mem_onst,
	.pwrdm_set_mem_retst	= omap2_pwrdm_set_mem_retst,
	.pwrdm_read_mem_pwrst	= omap2_pwrdm_read_mem_pwrst,
	.pwrdm_read_mem_retst	= omap2_pwrdm_read_mem_retst,
	.pwrdm_wait_transition	= omap2_pwrdm_wait_transition,
};

/*
 *
 */

static struct prm_ll_data omap2xxx_prm_ll_data = {
	.read_reset_sources = &omap2xxx_prm_read_reset_sources,
};

int __init omap2xxx_prm_init(void)
{
	if (!cpu_is_omap24xx())
		return 0;

	return prm_register(&omap2xxx_prm_ll_data);
}

static void __exit omap2xxx_prm_exit(void)
{
	if (!cpu_is_omap24xx())
		return;

	/* Should never happen */
	WARN(prm_unregister(&omap2xxx_prm_ll_data),
	     "%s: prm_ll_data function pointer mismatch\n", __func__);
}
__exitcall(omap2xxx_prm_exit);
Commit	Line	Data
49815399 PW	1	/*
	2	* OMAP2xxx PRM module functions
	3	*
	4	* Copyright (C) 2010-2012 Texas Instruments, Inc.
	5	* Copyright (C) 2010 Nokia Corporation
	6	* Benoît Cousson
	7	* Paul Walmsley
	8	* Rajendra Nayak <rnayak@ti.com>
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
	14
	15	#include <linux/kernel.h>
	16	#include <linux/errno.h>
	17	#include <linux/err.h>
	18	#include <linux/io.h>
	19	#include <linux/irq.h>
	20
	21	#include "common.h"
	22	#include <plat/cpu.h>
49815399 PW	23
	24	#include "vp.h"
	25	#include "powerdomain.h"
4bd5259e	26	#include "clockdomain.h"
49815399 PW	27	#include "prm2xxx.h"
	28	#include "cm2xxx_3xxx.h"
	29	#include "prm-regbits-24xx.h"
	30
2bb2a5d3 PW	31	/*
	32	* omap2xxx_prm_reset_src_map - map from bits in the PRM_RSTST_WKUP
	33	* hardware register (which are specific to the OMAP2xxx SoCs) to
	34	* reset source ID bit shifts (which is an OMAP SoC-independent
	35	* enumeration)
	36	*/
	37	static struct prm_reset_src_map omap2xxx_prm_reset_src_map[] = {
	38	{ OMAP_GLOBALCOLD_RST_SHIFT, OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
	39	{ OMAP_GLOBALWARM_RST_SHIFT, OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
	40	{ OMAP24XX_SECU_VIOL_RST_SHIFT, OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
	41	{ OMAP24XX_MPU_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
	42	{ OMAP24XX_SECU_WD_RST_SHIFT, OMAP_SECU_WD_RST_SRC_ID_SHIFT },
	43	{ OMAP24XX_EXTWMPU_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT },
	44	{ -1, -1 },
	45	};
	46
	47	/**
	48	* omap2xxx_prm_read_reset_sources - return the last SoC reset source
	49	*
	50	* Return a u32 representing the last reset sources of the SoC. The
	51	* returned reset source bits are standardized across OMAP SoCs.
	52	*/
	53	static u32 omap2xxx_prm_read_reset_sources(void)
	54	{
	55	struct prm_reset_src_map *p;
	56	u32 r = 0;
	57	u32 v;
	58
	59	v = omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST);
	60
	61	p = omap2xxx_prm_reset_src_map;
	62	while (p->reg_shift >= 0 && p->std_shift >= 0) {
	63	if (v & (1 << p->reg_shift))
	64	r \|= 1 << p->std_shift;
	65	p++;
	66	}
	67
	68	return r;
	69	}
	70
d08cce6a PW	71	/**
	72	* omap2xxx_prm_dpll_reset - use DPLL reset to reboot the OMAP SoC
	73	*
	74	* Set the DPLL reset bit, which should reboot the SoC. This is the
	75	* recommended way to restart the SoC. No return value.
	76	*/
	77	void omap2xxx_prm_dpll_reset(void)
	78	{
	79	omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, WKUP_MOD,
	80	OMAP2_RM_RSTCTRL);
	81	/* OCP barrier */
	82	omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTCTRL);
	83	}
	84
4bd5259e PW	85	int omap2xxx_clkdm_sleep(struct clockdomain *clkdm)
	86	{
	87	omap2_prm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
	88	clkdm->pwrdm.ptr->prcm_offs,
	89	OMAP2_PM_PWSTCTRL);
	90	return 0;
	91	}
	92
	93	int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm)
	94	{
	95	omap2_prm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
	96	clkdm->pwrdm.ptr->prcm_offs,
	97	OMAP2_PM_PWSTCTRL);
	98	return 0;
	99	}
	100
49815399 PW	101	struct pwrdm_ops omap2_pwrdm_operations = {
	102	.pwrdm_set_next_pwrst = omap2_pwrdm_set_next_pwrst,
	103	.pwrdm_read_next_pwrst = omap2_pwrdm_read_next_pwrst,
	104	.pwrdm_read_pwrst = omap2_pwrdm_read_pwrst,
	105	.pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst,
	106	.pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst,
	107	.pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst,
	108	.pwrdm_read_mem_pwrst = omap2_pwrdm_read_mem_pwrst,
	109	.pwrdm_read_mem_retst = omap2_pwrdm_read_mem_retst,
	110	.pwrdm_wait_transition = omap2_pwrdm_wait_transition,
	111	};
2bb2a5d3 PW	112
	113	/*
	114	*
	115	*/
	116
	117	static struct prm_ll_data omap2xxx_prm_ll_data = {
	118	.read_reset_sources = &omap2xxx_prm_read_reset_sources,
	119	};
	120
63a293e0	121	int __init omap2xxx_prm_init(void)
2bb2a5d3 PW	122	{
	123	if (!cpu_is_omap24xx())
	124	return 0;
	125
	126	return prm_register(&omap2xxx_prm_ll_data);
	127	}
2bb2a5d3 PW	128
	129	static void __exit omap2xxx_prm_exit(void)
	130	{
	131	if (!cpu_is_omap24xx())
	132	return;
	133
	134	/* Should never happen */
	135	WARN(prm_unregister(&omap2xxx_prm_ll_data),
	136	"%s: prm_ll_data function pointer mismatch\n", __func__);
	137	}
	138	__exitcall(omap2xxx_prm_exit);