Commit | Line | Data |
---|---|---|
cf21405f PW |
1 | /* |
2 | * OMAP2/3 PRM module functions | |
3 | * | |
26c98c56 | 4 | * Copyright (C) 2010-2011 Texas Instruments, Inc. |
cf21405f PW |
5 | * Copyright (C) 2010 Nokia Corporation |
6 | * BenoƮt Cousson | |
7 | * Paul Walmsley | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
cf21405f PW |
15 | #include <linux/errno.h> |
16 | #include <linux/err.h> | |
59fb659b | 17 | #include <linux/io.h> |
cf21405f | 18 | |
dbc04161 | 19 | #include "common.h" |
49815399 | 20 | #include "powerdomain.h" |
59fb659b | 21 | #include "prm2xxx_3xxx.h" |
cf21405f | 22 | #include "prm-regbits-24xx.h" |
4bd5259e | 23 | #include "clockdomain.h" |
59fb659b | 24 | |
cf21405f PW |
25 | /** |
26 | * omap2_prm_is_hardreset_asserted - read the HW reset line state of | |
27 | * submodules contained in the hwmod module | |
28 | * @prm_mod: PRM submodule base (e.g. CORE_MOD) | |
29 | * @shift: register bit shift corresponding to the reset line to check | |
30 | * | |
31 | * Returns 1 if the (sub)module hardreset line is currently asserted, | |
32 | * 0 if the (sub)module hardreset line is not currently asserted, or | |
33 | * -EINVAL if called while running on a non-OMAP2/3 chip. | |
34 | */ | |
35 | int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift) | |
36 | { | |
c4d7e58f | 37 | return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, |
cf21405f PW |
38 | (1 << shift)); |
39 | } | |
40 | ||
41 | /** | |
42 | * omap2_prm_assert_hardreset - assert the HW reset line of a submodule | |
43 | * @prm_mod: PRM submodule base (e.g. CORE_MOD) | |
44 | * @shift: register bit shift corresponding to the reset line to assert | |
45 | * | |
46 | * Some IPs like dsp or iva contain processors that require an HW | |
47 | * reset line to be asserted / deasserted in order to fully enable the | |
48 | * IP. These modules may have multiple hard-reset lines that reset | |
49 | * different 'submodules' inside the IP block. This function will | |
50 | * place the submodule into reset. Returns 0 upon success or -EINVAL | |
51 | * upon an argument error. | |
52 | */ | |
53 | int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift) | |
54 | { | |
55 | u32 mask; | |
56 | ||
cf21405f | 57 | mask = 1 << shift; |
c4d7e58f | 58 | omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL); |
cf21405f PW |
59 | |
60 | return 0; | |
61 | } | |
62 | ||
63 | /** | |
64 | * omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait | |
65 | * @prm_mod: PRM submodule base (e.g. CORE_MOD) | |
cc1226e7 | 66 | * @rst_shift: register bit shift corresponding to the reset line to deassert |
67 | * @st_shift: register bit shift for the status of the deasserted submodule | |
cf21405f PW |
68 | * |
69 | * Some IPs like dsp or iva contain processors that require an HW | |
70 | * reset line to be asserted / deasserted in order to fully enable the | |
71 | * IP. These modules may have multiple hard-reset lines that reset | |
72 | * different 'submodules' inside the IP block. This function will | |
73 | * take the submodule out of reset and wait until the PRCM indicates | |
74 | * that the reset has completed before returning. Returns 0 upon success or | |
75 | * -EINVAL upon an argument error, -EEXIST if the submodule was already out | |
76 | * of reset, or -EBUSY if the submodule did not exit reset promptly. | |
77 | */ | |
cc1226e7 | 78 | int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift) |
cf21405f | 79 | { |
cc1226e7 | 80 | u32 rst, st; |
cf21405f PW |
81 | int c; |
82 | ||
cc1226e7 | 83 | rst = 1 << rst_shift; |
84 | st = 1 << st_shift; | |
cf21405f PW |
85 | |
86 | /* Check the current status to avoid de-asserting the line twice */ | |
cc1226e7 | 87 | if (omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, rst) == 0) |
cf21405f PW |
88 | return -EEXIST; |
89 | ||
90 | /* Clear the reset status by writing 1 to the status bit */ | |
cc1226e7 | 91 | omap2_prm_rmw_mod_reg_bits(0xffffffff, st, prm_mod, OMAP2_RM_RSTST); |
cf21405f | 92 | /* de-assert the reset control line */ |
cc1226e7 | 93 | omap2_prm_rmw_mod_reg_bits(rst, 0, prm_mod, OMAP2_RM_RSTCTRL); |
cf21405f | 94 | /* wait the status to be set */ |
c4d7e58f | 95 | omap_test_timeout(omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST, |
cc1226e7 | 96 | st), |
cf21405f PW |
97 | MAX_MODULE_HARDRESET_WAIT, c); |
98 | ||
99 | return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; | |
100 | } | |
58aaa599 | 101 | |
49815399 PW |
102 | |
103 | /* Powerdomain low-level functions */ | |
104 | ||
105 | /* Common functions across OMAP2 and OMAP3 */ | |
106 | int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) | |
107 | { | |
108 | omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, | |
109 | (pwrst << OMAP_POWERSTATE_SHIFT), | |
110 | pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); | |
111 | return 0; | |
112 | } | |
113 | ||
114 | int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) | |
115 | { | |
116 | return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, | |
117 | OMAP2_PM_PWSTCTRL, | |
118 | OMAP_POWERSTATE_MASK); | |
119 | } | |
120 | ||
121 | int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm) | |
122 | { | |
123 | return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, | |
124 | OMAP2_PM_PWSTST, | |
125 | OMAP_POWERSTATEST_MASK); | |
126 | } | |
127 | ||
128 | int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, | |
129 | u8 pwrst) | |
130 | { | |
131 | u32 m; | |
132 | ||
133 | m = omap2_pwrdm_get_mem_bank_onstate_mask(bank); | |
134 | ||
135 | omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, | |
136 | OMAP2_PM_PWSTCTRL); | |
137 | ||
138 | return 0; | |
139 | } | |
140 | ||
141 | int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, | |
142 | u8 pwrst) | |
143 | { | |
144 | u32 m; | |
145 | ||
146 | m = omap2_pwrdm_get_mem_bank_retst_mask(bank); | |
147 | ||
148 | omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, | |
149 | OMAP2_PM_PWSTCTRL); | |
150 | ||
151 | return 0; | |
152 | } | |
153 | ||
154 | int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) | |
155 | { | |
156 | u32 m; | |
157 | ||
158 | m = omap2_pwrdm_get_mem_bank_stst_mask(bank); | |
159 | ||
160 | return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, | |
161 | m); | |
162 | } | |
163 | ||
164 | int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) | |
165 | { | |
166 | u32 m; | |
167 | ||
168 | m = omap2_pwrdm_get_mem_bank_retst_mask(bank); | |
169 | ||
170 | return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, | |
171 | OMAP2_PM_PWSTCTRL, m); | |
172 | } | |
173 | ||
174 | int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) | |
175 | { | |
176 | u32 v; | |
177 | ||
178 | v = pwrst << __ffs(OMAP_LOGICRETSTATE_MASK); | |
179 | omap2_prm_rmw_mod_reg_bits(OMAP_LOGICRETSTATE_MASK, v, pwrdm->prcm_offs, | |
180 | OMAP2_PM_PWSTCTRL); | |
181 | ||
182 | return 0; | |
183 | } | |
184 | ||
185 | int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm) | |
186 | { | |
187 | u32 c = 0; | |
188 | ||
189 | /* | |
190 | * REVISIT: pwrdm_wait_transition() may be better implemented | |
191 | * via a callback and a periodic timer check -- how long do we expect | |
192 | * powerdomain transitions to take? | |
193 | */ | |
194 | ||
195 | /* XXX Is this udelay() value meaningful? */ | |
196 | while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) & | |
197 | OMAP_INTRANSITION_MASK) && | |
198 | (c++ < PWRDM_TRANSITION_BAILOUT)) | |
199 | udelay(1); | |
200 | ||
201 | if (c > PWRDM_TRANSITION_BAILOUT) { | |
202 | pr_err("powerdomain: %s: waited too long to complete transition\n", | |
203 | pwrdm->name); | |
204 | return -EAGAIN; | |
205 | } | |
206 | ||
207 | pr_debug("powerdomain: completed transition in %d loops\n", c); | |
208 | ||
209 | return 0; | |
210 | } | |
211 | ||
4bd5259e PW |
212 | int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1, |
213 | struct clockdomain *clkdm2) | |
214 | { | |
215 | omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit), | |
216 | clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); | |
217 | return 0; | |
218 | } | |
219 | ||
220 | int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1, | |
221 | struct clockdomain *clkdm2) | |
222 | { | |
223 | omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit), | |
224 | clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); | |
225 | return 0; | |
226 | } | |
227 | ||
228 | int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1, | |
229 | struct clockdomain *clkdm2) | |
230 | { | |
231 | return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, | |
232 | PM_WKDEP, (1 << clkdm2->dep_bit)); | |
233 | } | |
234 | ||
235 | int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm) | |
236 | { | |
237 | struct clkdm_dep *cd; | |
238 | u32 mask = 0; | |
239 | ||
240 | for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { | |
241 | if (!cd->clkdm) | |
242 | continue; /* only happens if data is erroneous */ | |
243 | ||
244 | /* PRM accesses are slow, so minimize them */ | |
245 | mask |= 1 << cd->clkdm->dep_bit; | |
246 | atomic_set(&cd->wkdep_usecount, 0); | |
247 | } | |
248 | ||
249 | omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, | |
250 | PM_WKDEP); | |
251 | return 0; | |
252 | } | |
253 |