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cf21405f PW |
1 | /* |
2 | * OMAP2/3 PRM module functions | |
3 | * | |
26c98c56 | 4 | * Copyright (C) 2010-2011 Texas Instruments, Inc. |
cf21405f PW |
5 | * Copyright (C) 2010 Nokia Corporation |
6 | * BenoƮt Cousson | |
7 | * Paul Walmsley | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
cf21405f PW |
15 | #include <linux/errno.h> |
16 | #include <linux/err.h> | |
59fb659b | 17 | #include <linux/io.h> |
cf21405f | 18 | |
49815399 | 19 | #include "powerdomain.h" |
59fb659b | 20 | #include "prm2xxx_3xxx.h" |
cf21405f | 21 | #include "prm-regbits-24xx.h" |
4bd5259e | 22 | #include "clockdomain.h" |
59fb659b | 23 | |
cf21405f PW |
24 | /** |
25 | * omap2_prm_is_hardreset_asserted - read the HW reset line state of | |
26 | * submodules contained in the hwmod module | |
27 | * @prm_mod: PRM submodule base (e.g. CORE_MOD) | |
28 | * @shift: register bit shift corresponding to the reset line to check | |
29 | * | |
30 | * Returns 1 if the (sub)module hardreset line is currently asserted, | |
31 | * 0 if the (sub)module hardreset line is not currently asserted, or | |
32 | * -EINVAL if called while running on a non-OMAP2/3 chip. | |
33 | */ | |
34 | int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift) | |
35 | { | |
c4d7e58f | 36 | return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, |
cf21405f PW |
37 | (1 << shift)); |
38 | } | |
39 | ||
40 | /** | |
41 | * omap2_prm_assert_hardreset - assert the HW reset line of a submodule | |
42 | * @prm_mod: PRM submodule base (e.g. CORE_MOD) | |
43 | * @shift: register bit shift corresponding to the reset line to assert | |
44 | * | |
45 | * Some IPs like dsp or iva contain processors that require an HW | |
46 | * reset line to be asserted / deasserted in order to fully enable the | |
47 | * IP. These modules may have multiple hard-reset lines that reset | |
48 | * different 'submodules' inside the IP block. This function will | |
49 | * place the submodule into reset. Returns 0 upon success or -EINVAL | |
50 | * upon an argument error. | |
51 | */ | |
52 | int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift) | |
53 | { | |
54 | u32 mask; | |
55 | ||
cf21405f | 56 | mask = 1 << shift; |
c4d7e58f | 57 | omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL); |
cf21405f PW |
58 | |
59 | return 0; | |
60 | } | |
61 | ||
62 | /** | |
63 | * omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait | |
64 | * @prm_mod: PRM submodule base (e.g. CORE_MOD) | |
cc1226e7 | 65 | * @rst_shift: register bit shift corresponding to the reset line to deassert |
66 | * @st_shift: register bit shift for the status of the deasserted submodule | |
cf21405f PW |
67 | * |
68 | * Some IPs like dsp or iva contain processors that require an HW | |
69 | * reset line to be asserted / deasserted in order to fully enable the | |
70 | * IP. These modules may have multiple hard-reset lines that reset | |
71 | * different 'submodules' inside the IP block. This function will | |
72 | * take the submodule out of reset and wait until the PRCM indicates | |
73 | * that the reset has completed before returning. Returns 0 upon success or | |
74 | * -EINVAL upon an argument error, -EEXIST if the submodule was already out | |
75 | * of reset, or -EBUSY if the submodule did not exit reset promptly. | |
76 | */ | |
cc1226e7 | 77 | int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift) |
cf21405f | 78 | { |
cc1226e7 | 79 | u32 rst, st; |
cf21405f PW |
80 | int c; |
81 | ||
cc1226e7 | 82 | rst = 1 << rst_shift; |
83 | st = 1 << st_shift; | |
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84 | |
85 | /* Check the current status to avoid de-asserting the line twice */ | |
cc1226e7 | 86 | if (omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, rst) == 0) |
cf21405f PW |
87 | return -EEXIST; |
88 | ||
89 | /* Clear the reset status by writing 1 to the status bit */ | |
cc1226e7 | 90 | omap2_prm_rmw_mod_reg_bits(0xffffffff, st, prm_mod, OMAP2_RM_RSTST); |
cf21405f | 91 | /* de-assert the reset control line */ |
cc1226e7 | 92 | omap2_prm_rmw_mod_reg_bits(rst, 0, prm_mod, OMAP2_RM_RSTCTRL); |
cf21405f | 93 | /* wait the status to be set */ |
c4d7e58f | 94 | omap_test_timeout(omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST, |
cc1226e7 | 95 | st), |
cf21405f PW |
96 | MAX_MODULE_HARDRESET_WAIT, c); |
97 | ||
98 | return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; | |
99 | } | |
58aaa599 | 100 | |
49815399 PW |
101 | |
102 | /* Powerdomain low-level functions */ | |
103 | ||
104 | /* Common functions across OMAP2 and OMAP3 */ | |
49815399 PW |
105 | int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, |
106 | u8 pwrst) | |
107 | { | |
108 | u32 m; | |
109 | ||
110 | m = omap2_pwrdm_get_mem_bank_onstate_mask(bank); | |
111 | ||
112 | omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, | |
113 | OMAP2_PM_PWSTCTRL); | |
114 | ||
115 | return 0; | |
116 | } | |
117 | ||
118 | int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, | |
119 | u8 pwrst) | |
120 | { | |
121 | u32 m; | |
122 | ||
123 | m = omap2_pwrdm_get_mem_bank_retst_mask(bank); | |
124 | ||
125 | omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, | |
126 | OMAP2_PM_PWSTCTRL); | |
127 | ||
128 | return 0; | |
129 | } | |
130 | ||
131 | int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) | |
132 | { | |
133 | u32 m; | |
134 | ||
135 | m = omap2_pwrdm_get_mem_bank_stst_mask(bank); | |
136 | ||
137 | return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, | |
138 | m); | |
139 | } | |
140 | ||
141 | int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) | |
142 | { | |
143 | u32 m; | |
144 | ||
145 | m = omap2_pwrdm_get_mem_bank_retst_mask(bank); | |
146 | ||
147 | return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, | |
148 | OMAP2_PM_PWSTCTRL, m); | |
149 | } | |
150 | ||
151 | int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) | |
152 | { | |
153 | u32 v; | |
154 | ||
155 | v = pwrst << __ffs(OMAP_LOGICRETSTATE_MASK); | |
156 | omap2_prm_rmw_mod_reg_bits(OMAP_LOGICRETSTATE_MASK, v, pwrdm->prcm_offs, | |
157 | OMAP2_PM_PWSTCTRL); | |
158 | ||
159 | return 0; | |
160 | } | |
161 | ||
162 | int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm) | |
163 | { | |
164 | u32 c = 0; | |
165 | ||
166 | /* | |
167 | * REVISIT: pwrdm_wait_transition() may be better implemented | |
168 | * via a callback and a periodic timer check -- how long do we expect | |
169 | * powerdomain transitions to take? | |
170 | */ | |
171 | ||
172 | /* XXX Is this udelay() value meaningful? */ | |
173 | while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) & | |
174 | OMAP_INTRANSITION_MASK) && | |
175 | (c++ < PWRDM_TRANSITION_BAILOUT)) | |
176 | udelay(1); | |
177 | ||
178 | if (c > PWRDM_TRANSITION_BAILOUT) { | |
179 | pr_err("powerdomain: %s: waited too long to complete transition\n", | |
180 | pwrdm->name); | |
181 | return -EAGAIN; | |
182 | } | |
183 | ||
184 | pr_debug("powerdomain: completed transition in %d loops\n", c); | |
185 | ||
186 | return 0; | |
187 | } | |
188 | ||
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189 | int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1, |
190 | struct clockdomain *clkdm2) | |
191 | { | |
192 | omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit), | |
193 | clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); | |
194 | return 0; | |
195 | } | |
196 | ||
197 | int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1, | |
198 | struct clockdomain *clkdm2) | |
199 | { | |
200 | omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit), | |
201 | clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); | |
202 | return 0; | |
203 | } | |
204 | ||
205 | int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1, | |
206 | struct clockdomain *clkdm2) | |
207 | { | |
208 | return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, | |
209 | PM_WKDEP, (1 << clkdm2->dep_bit)); | |
210 | } | |
211 | ||
92493870 | 212 | /* XXX Caller must hold the clkdm's powerdomain lock */ |
4bd5259e PW |
213 | int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm) |
214 | { | |
215 | struct clkdm_dep *cd; | |
216 | u32 mask = 0; | |
217 | ||
218 | for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { | |
219 | if (!cd->clkdm) | |
220 | continue; /* only happens if data is erroneous */ | |
221 | ||
222 | /* PRM accesses are slow, so minimize them */ | |
223 | mask |= 1 << cd->clkdm->dep_bit; | |
92493870 | 224 | cd->wkdep_usecount = 0; |
4bd5259e PW |
225 | } |
226 | ||
227 | omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, | |
228 | PM_WKDEP); | |
229 | return 0; | |
230 | } | |
231 |