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cf21405f PW |
1 | /* |
2 | * OMAP2/3 PRM module functions | |
3 | * | |
26c98c56 | 4 | * Copyright (C) 2010-2011 Texas Instruments, Inc. |
cf21405f PW |
5 | * Copyright (C) 2010 Nokia Corporation |
6 | * BenoƮt Cousson | |
7 | * Paul Walmsley | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
cf21405f PW |
15 | #include <linux/errno.h> |
16 | #include <linux/err.h> | |
59fb659b | 17 | #include <linux/io.h> |
cf21405f | 18 | |
49815399 | 19 | #include "powerdomain.h" |
59fb659b | 20 | #include "prm2xxx_3xxx.h" |
cf21405f | 21 | #include "prm-regbits-24xx.h" |
4bd5259e | 22 | #include "clockdomain.h" |
59fb659b | 23 | |
cf21405f PW |
24 | /** |
25 | * omap2_prm_is_hardreset_asserted - read the HW reset line state of | |
26 | * submodules contained in the hwmod module | |
cf21405f | 27 | * @shift: register bit shift corresponding to the reset line to check |
1bc28b34 TK |
28 | * @part: PRM partition, ignored for OMAP2 |
29 | * @prm_mod: PRM submodule base (e.g. CORE_MOD) | |
30 | * @offset: register offset, ignored for OMAP2 | |
cf21405f PW |
31 | * |
32 | * Returns 1 if the (sub)module hardreset line is currently asserted, | |
33 | * 0 if the (sub)module hardreset line is not currently asserted, or | |
34 | * -EINVAL if called while running on a non-OMAP2/3 chip. | |
35 | */ | |
1bc28b34 | 36 | int omap2_prm_is_hardreset_asserted(u8 shift, u8 part, s16 prm_mod, u16 offset) |
cf21405f | 37 | { |
c4d7e58f | 38 | return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, |
cf21405f PW |
39 | (1 << shift)); |
40 | } | |
41 | ||
42 | /** | |
43 | * omap2_prm_assert_hardreset - assert the HW reset line of a submodule | |
cf21405f | 44 | * @shift: register bit shift corresponding to the reset line to assert |
efd44dc3 TK |
45 | * @part: PRM partition, ignored for OMAP2 |
46 | * @prm_mod: PRM submodule base (e.g. CORE_MOD) | |
47 | * @offset: register offset, ignored for OMAP2 | |
cf21405f PW |
48 | * |
49 | * Some IPs like dsp or iva contain processors that require an HW | |
50 | * reset line to be asserted / deasserted in order to fully enable the | |
51 | * IP. These modules may have multiple hard-reset lines that reset | |
52 | * different 'submodules' inside the IP block. This function will | |
53 | * place the submodule into reset. Returns 0 upon success or -EINVAL | |
54 | * upon an argument error. | |
55 | */ | |
efd44dc3 | 56 | int omap2_prm_assert_hardreset(u8 shift, u8 part, s16 prm_mod, u16 offset) |
cf21405f PW |
57 | { |
58 | u32 mask; | |
59 | ||
cf21405f | 60 | mask = 1 << shift; |
c4d7e58f | 61 | omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL); |
cf21405f PW |
62 | |
63 | return 0; | |
64 | } | |
65 | ||
66 | /** | |
67 | * omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait | |
68 | * @prm_mod: PRM submodule base (e.g. CORE_MOD) | |
cc1226e7 | 69 | * @rst_shift: register bit shift corresponding to the reset line to deassert |
70 | * @st_shift: register bit shift for the status of the deasserted submodule | |
37fb59d7 TK |
71 | * @part: PRM partition, not used for OMAP2 |
72 | * @prm_mod: PRM submodule base (e.g. CORE_MOD) | |
73 | * @rst_offset: reset register offset, not used for OMAP2 | |
74 | * @st_offset: reset status register offset, not used for OMAP2 | |
cf21405f PW |
75 | * |
76 | * Some IPs like dsp or iva contain processors that require an HW | |
77 | * reset line to be asserted / deasserted in order to fully enable the | |
78 | * IP. These modules may have multiple hard-reset lines that reset | |
79 | * different 'submodules' inside the IP block. This function will | |
80 | * take the submodule out of reset and wait until the PRCM indicates | |
81 | * that the reset has completed before returning. Returns 0 upon success or | |
82 | * -EINVAL upon an argument error, -EEXIST if the submodule was already out | |
83 | * of reset, or -EBUSY if the submodule did not exit reset promptly. | |
84 | */ | |
37fb59d7 TK |
85 | int omap2_prm_deassert_hardreset(u8 rst_shift, u8 st_shift, u8 part, |
86 | s16 prm_mod, u16 rst_offset, u16 st_offset) | |
cf21405f | 87 | { |
cc1226e7 | 88 | u32 rst, st; |
cf21405f PW |
89 | int c; |
90 | ||
cc1226e7 | 91 | rst = 1 << rst_shift; |
92 | st = 1 << st_shift; | |
cf21405f PW |
93 | |
94 | /* Check the current status to avoid de-asserting the line twice */ | |
cc1226e7 | 95 | if (omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, rst) == 0) |
cf21405f PW |
96 | return -EEXIST; |
97 | ||
98 | /* Clear the reset status by writing 1 to the status bit */ | |
cc1226e7 | 99 | omap2_prm_rmw_mod_reg_bits(0xffffffff, st, prm_mod, OMAP2_RM_RSTST); |
cf21405f | 100 | /* de-assert the reset control line */ |
cc1226e7 | 101 | omap2_prm_rmw_mod_reg_bits(rst, 0, prm_mod, OMAP2_RM_RSTCTRL); |
cf21405f | 102 | /* wait the status to be set */ |
c4d7e58f | 103 | omap_test_timeout(omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST, |
cc1226e7 | 104 | st), |
cf21405f PW |
105 | MAX_MODULE_HARDRESET_WAIT, c); |
106 | ||
107 | return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; | |
108 | } | |
58aaa599 | 109 | |
49815399 PW |
110 | |
111 | /* Powerdomain low-level functions */ | |
112 | ||
113 | /* Common functions across OMAP2 and OMAP3 */ | |
49815399 PW |
114 | int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, |
115 | u8 pwrst) | |
116 | { | |
117 | u32 m; | |
118 | ||
119 | m = omap2_pwrdm_get_mem_bank_onstate_mask(bank); | |
120 | ||
121 | omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, | |
122 | OMAP2_PM_PWSTCTRL); | |
123 | ||
124 | return 0; | |
125 | } | |
126 | ||
127 | int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, | |
128 | u8 pwrst) | |
129 | { | |
130 | u32 m; | |
131 | ||
132 | m = omap2_pwrdm_get_mem_bank_retst_mask(bank); | |
133 | ||
134 | omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, | |
135 | OMAP2_PM_PWSTCTRL); | |
136 | ||
137 | return 0; | |
138 | } | |
139 | ||
140 | int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) | |
141 | { | |
142 | u32 m; | |
143 | ||
144 | m = omap2_pwrdm_get_mem_bank_stst_mask(bank); | |
145 | ||
146 | return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, | |
147 | m); | |
148 | } | |
149 | ||
150 | int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) | |
151 | { | |
152 | u32 m; | |
153 | ||
154 | m = omap2_pwrdm_get_mem_bank_retst_mask(bank); | |
155 | ||
156 | return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, | |
157 | OMAP2_PM_PWSTCTRL, m); | |
158 | } | |
159 | ||
160 | int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) | |
161 | { | |
162 | u32 v; | |
163 | ||
164 | v = pwrst << __ffs(OMAP_LOGICRETSTATE_MASK); | |
165 | omap2_prm_rmw_mod_reg_bits(OMAP_LOGICRETSTATE_MASK, v, pwrdm->prcm_offs, | |
166 | OMAP2_PM_PWSTCTRL); | |
167 | ||
168 | return 0; | |
169 | } | |
170 | ||
171 | int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm) | |
172 | { | |
173 | u32 c = 0; | |
174 | ||
175 | /* | |
176 | * REVISIT: pwrdm_wait_transition() may be better implemented | |
177 | * via a callback and a periodic timer check -- how long do we expect | |
178 | * powerdomain transitions to take? | |
179 | */ | |
180 | ||
181 | /* XXX Is this udelay() value meaningful? */ | |
182 | while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) & | |
183 | OMAP_INTRANSITION_MASK) && | |
184 | (c++ < PWRDM_TRANSITION_BAILOUT)) | |
185 | udelay(1); | |
186 | ||
187 | if (c > PWRDM_TRANSITION_BAILOUT) { | |
188 | pr_err("powerdomain: %s: waited too long to complete transition\n", | |
189 | pwrdm->name); | |
190 | return -EAGAIN; | |
191 | } | |
192 | ||
193 | pr_debug("powerdomain: completed transition in %d loops\n", c); | |
194 | ||
195 | return 0; | |
196 | } | |
197 | ||
4bd5259e PW |
198 | int omap2_clkdm_add_wkdep(struct clockdomain *clkdm1, |
199 | struct clockdomain *clkdm2) | |
200 | { | |
201 | omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit), | |
202 | clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); | |
203 | return 0; | |
204 | } | |
205 | ||
206 | int omap2_clkdm_del_wkdep(struct clockdomain *clkdm1, | |
207 | struct clockdomain *clkdm2) | |
208 | { | |
209 | omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit), | |
210 | clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); | |
211 | return 0; | |
212 | } | |
213 | ||
214 | int omap2_clkdm_read_wkdep(struct clockdomain *clkdm1, | |
215 | struct clockdomain *clkdm2) | |
216 | { | |
217 | return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, | |
218 | PM_WKDEP, (1 << clkdm2->dep_bit)); | |
219 | } | |
220 | ||
92493870 | 221 | /* XXX Caller must hold the clkdm's powerdomain lock */ |
4bd5259e PW |
222 | int omap2_clkdm_clear_all_wkdeps(struct clockdomain *clkdm) |
223 | { | |
224 | struct clkdm_dep *cd; | |
225 | u32 mask = 0; | |
226 | ||
227 | for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) { | |
228 | if (!cd->clkdm) | |
229 | continue; /* only happens if data is erroneous */ | |
230 | ||
231 | /* PRM accesses are slow, so minimize them */ | |
232 | mask |= 1 << cd->clkdm->dep_bit; | |
92493870 | 233 | cd->wkdep_usecount = 0; |
4bd5259e PW |
234 | } |
235 | ||
236 | omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, | |
237 | PM_WKDEP); | |
238 | return 0; | |
239 | } | |
240 |