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1 | /* |
2 | * OMAP2/3 PRM module functions | |
3 | * | |
4 | * Copyright (C) 2010 Texas Instruments, Inc. | |
5 | * Copyright (C) 2010 Nokia Corporation | |
6 | * BenoƮt Cousson | |
7 | * Paul Walmsley | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
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15 | #include <linux/errno.h> |
16 | #include <linux/err.h> | |
59fb659b | 17 | #include <linux/io.h> |
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18 | |
19 | #include <plat/common.h> | |
20 | #include <plat/cpu.h> | |
21 | #include <plat/prcm.h> | |
22 | ||
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23 | #include "vp.h" |
24 | ||
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25 | #include "prm2xxx_3xxx.h" |
26 | #include "cm2xxx_3xxx.h" | |
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27 | #include "prm-regbits-24xx.h" |
28 | #include "prm-regbits-34xx.h" | |
29 | ||
c4d7e58f | 30 | u32 omap2_prm_read_mod_reg(s16 module, u16 idx) |
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31 | { |
32 | return __raw_readl(prm_base + module + idx); | |
33 | } | |
34 | ||
c4d7e58f | 35 | void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx) |
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36 | { |
37 | __raw_writel(val, prm_base + module + idx); | |
38 | } | |
39 | ||
40 | /* Read-modify-write a register in a PRM module. Caller must lock */ | |
c4d7e58f | 41 | u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) |
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42 | { |
43 | u32 v; | |
44 | ||
c4d7e58f | 45 | v = omap2_prm_read_mod_reg(module, idx); |
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46 | v &= ~mask; |
47 | v |= bits; | |
c4d7e58f | 48 | omap2_prm_write_mod_reg(v, module, idx); |
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49 | |
50 | return v; | |
51 | } | |
52 | ||
53 | /* Read a PRM register, AND it, and shift the result down to bit 0 */ | |
c4d7e58f | 54 | u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) |
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55 | { |
56 | u32 v; | |
57 | ||
c4d7e58f | 58 | v = omap2_prm_read_mod_reg(domain, idx); |
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59 | v &= mask; |
60 | v >>= __ffs(mask); | |
61 | ||
62 | return v; | |
63 | } | |
64 | ||
c4d7e58f | 65 | u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) |
59fb659b | 66 | { |
c4d7e58f | 67 | return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx); |
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68 | } |
69 | ||
c4d7e58f | 70 | u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) |
59fb659b | 71 | { |
c4d7e58f | 72 | return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx); |
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73 | } |
74 | ||
75 | ||
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76 | /** |
77 | * omap2_prm_is_hardreset_asserted - read the HW reset line state of | |
78 | * submodules contained in the hwmod module | |
79 | * @prm_mod: PRM submodule base (e.g. CORE_MOD) | |
80 | * @shift: register bit shift corresponding to the reset line to check | |
81 | * | |
82 | * Returns 1 if the (sub)module hardreset line is currently asserted, | |
83 | * 0 if the (sub)module hardreset line is not currently asserted, or | |
84 | * -EINVAL if called while running on a non-OMAP2/3 chip. | |
85 | */ | |
86 | int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift) | |
87 | { | |
88 | if (!(cpu_is_omap24xx() || cpu_is_omap34xx())) | |
89 | return -EINVAL; | |
90 | ||
c4d7e58f | 91 | return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, |
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92 | (1 << shift)); |
93 | } | |
94 | ||
95 | /** | |
96 | * omap2_prm_assert_hardreset - assert the HW reset line of a submodule | |
97 | * @prm_mod: PRM submodule base (e.g. CORE_MOD) | |
98 | * @shift: register bit shift corresponding to the reset line to assert | |
99 | * | |
100 | * Some IPs like dsp or iva contain processors that require an HW | |
101 | * reset line to be asserted / deasserted in order to fully enable the | |
102 | * IP. These modules may have multiple hard-reset lines that reset | |
103 | * different 'submodules' inside the IP block. This function will | |
104 | * place the submodule into reset. Returns 0 upon success or -EINVAL | |
105 | * upon an argument error. | |
106 | */ | |
107 | int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift) | |
108 | { | |
109 | u32 mask; | |
110 | ||
111 | if (!(cpu_is_omap24xx() || cpu_is_omap34xx())) | |
112 | return -EINVAL; | |
113 | ||
114 | mask = 1 << shift; | |
c4d7e58f | 115 | omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL); |
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116 | |
117 | return 0; | |
118 | } | |
119 | ||
120 | /** | |
121 | * omap2_prm_deassert_hardreset - deassert a submodule hardreset line and wait | |
122 | * @prm_mod: PRM submodule base (e.g. CORE_MOD) | |
cc1226e7 | 123 | * @rst_shift: register bit shift corresponding to the reset line to deassert |
124 | * @st_shift: register bit shift for the status of the deasserted submodule | |
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125 | * |
126 | * Some IPs like dsp or iva contain processors that require an HW | |
127 | * reset line to be asserted / deasserted in order to fully enable the | |
128 | * IP. These modules may have multiple hard-reset lines that reset | |
129 | * different 'submodules' inside the IP block. This function will | |
130 | * take the submodule out of reset and wait until the PRCM indicates | |
131 | * that the reset has completed before returning. Returns 0 upon success or | |
132 | * -EINVAL upon an argument error, -EEXIST if the submodule was already out | |
133 | * of reset, or -EBUSY if the submodule did not exit reset promptly. | |
134 | */ | |
cc1226e7 | 135 | int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift) |
cf21405f | 136 | { |
cc1226e7 | 137 | u32 rst, st; |
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138 | int c; |
139 | ||
140 | if (!(cpu_is_omap24xx() || cpu_is_omap34xx())) | |
141 | return -EINVAL; | |
142 | ||
cc1226e7 | 143 | rst = 1 << rst_shift; |
144 | st = 1 << st_shift; | |
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145 | |
146 | /* Check the current status to avoid de-asserting the line twice */ | |
cc1226e7 | 147 | if (omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, rst) == 0) |
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148 | return -EEXIST; |
149 | ||
150 | /* Clear the reset status by writing 1 to the status bit */ | |
cc1226e7 | 151 | omap2_prm_rmw_mod_reg_bits(0xffffffff, st, prm_mod, OMAP2_RM_RSTST); |
cf21405f | 152 | /* de-assert the reset control line */ |
cc1226e7 | 153 | omap2_prm_rmw_mod_reg_bits(rst, 0, prm_mod, OMAP2_RM_RSTCTRL); |
cf21405f | 154 | /* wait the status to be set */ |
c4d7e58f | 155 | omap_test_timeout(omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST, |
cc1226e7 | 156 | st), |
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157 | MAX_MODULE_HARDRESET_WAIT, c); |
158 | ||
159 | return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; | |
160 | } | |
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161 | |
162 | /* PRM VP */ | |
163 | ||
164 | /* | |
165 | * struct omap3_vp - OMAP3 VP register access description. | |
166 | * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg | |
167 | */ | |
168 | struct omap3_vp { | |
169 | u32 tranxdone_status; | |
170 | }; | |
171 | ||
4bb73ade | 172 | static struct omap3_vp omap3_vp[] = { |
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173 | [OMAP3_VP_VDD_MPU_ID] = { |
174 | .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK, | |
175 | }, | |
176 | [OMAP3_VP_VDD_CORE_ID] = { | |
177 | .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK, | |
178 | }, | |
179 | }; | |
180 | ||
181 | #define MAX_VP_ID ARRAY_SIZE(omap3_vp); | |
182 | ||
183 | u32 omap3_prm_vp_check_txdone(u8 vp_id) | |
184 | { | |
185 | struct omap3_vp *vp = &omap3_vp[vp_id]; | |
186 | u32 irqstatus; | |
187 | ||
188 | irqstatus = omap2_prm_read_mod_reg(OCP_MOD, | |
189 | OMAP3_PRM_IRQSTATUS_MPU_OFFSET); | |
190 | return irqstatus & vp->tranxdone_status; | |
191 | } | |
192 | ||
193 | void omap3_prm_vp_clear_txdone(u8 vp_id) | |
194 | { | |
195 | struct omap3_vp *vp = &omap3_vp[vp_id]; | |
196 | ||
197 | omap2_prm_write_mod_reg(vp->tranxdone_status, | |
198 | OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); | |
199 | } | |
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200 | |
201 | u32 omap3_prm_vcvp_read(u8 offset) | |
202 | { | |
203 | return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset); | |
204 | } | |
205 | ||
206 | void omap3_prm_vcvp_write(u32 val, u8 offset) | |
207 | { | |
208 | omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset); | |
209 | } | |
210 | ||
211 | u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset) | |
212 | { | |
213 | return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset); | |
214 | } |