[deliverable/linux.git] / arch / arm / mach-omap2 / prm33xx.c

/*
 * AM33XX PRM functions
 *
 * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/io.h>

#include "powerdomain.h"
#include "prm33xx.h"
#include "prm-regbits-33xx.h"

/* Read a register in a PRM instance */
u32 am33xx_prm_read_reg(s16 inst, u16 idx)
{
	return readl_relaxed(prm_base + inst + idx);
}

/* Write into a register in a PRM instance */
void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
{
	writel_relaxed(val, prm_base + inst + idx);
}

/* Read-modify-write a register in PRM. Caller must lock */
u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
{
	u32 v;

	v = am33xx_prm_read_reg(inst, idx);
	v &= ~mask;
	v |= bits;
	am33xx_prm_write_reg(v, inst, idx);

	return v;
}

/**
 * am33xx_prm_is_hardreset_asserted - read the HW reset line state of
 * submodules contained in the hwmod module
 * @shift: register bit shift corresponding to the reset line to check
 * @part: PRM partition, ignored for AM33xx
 * @inst: CM instance register offset (*_INST macro)
 * @rstctrl_offs: RM_RSTCTRL register address offset for this module
 *
 * Returns 1 if the (sub)module hardreset line is currently asserted,
 * 0 if the (sub)module hardreset line is not currently asserted, or
 * -EINVAL upon parameter error.
 */
static int am33xx_prm_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
					    u16 rstctrl_offs)
{
	u32 v;

	v = am33xx_prm_read_reg(inst, rstctrl_offs);
	v &= 1 << shift;
	v >>= shift;

	return v;
}

/**
 * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule
 * @shift: register bit shift corresponding to the reset line to assert
 * @part: CM partition, ignored for AM33xx
 * @inst: CM instance register offset (*_INST macro)
 * @rstctrl_reg: RM_RSTCTRL register address for this module
 *
 * Some IPs like dsp, ipu or iva contain processors that require an HW
 * reset line to be asserted / deasserted in order to fully enable the
 * IP.  These modules may have multiple hard-reset lines that reset
 * different 'submodules' inside the IP block.  This function will
 * place the submodule into reset.  Returns 0 upon success or -EINVAL
 * upon an argument error.
 */
static int am33xx_prm_assert_hardreset(u8 shift, u8 part, s16 inst,
				       u16 rstctrl_offs)
{
	u32 mask = 1 << shift;

	am33xx_prm_rmw_reg_bits(mask, mask, inst, rstctrl_offs);

	return 0;
}

/**
 * am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and
 * wait
 * @shift: register bit shift corresponding to the reset line to deassert
 * @st_shift: reset status register bit shift corresponding to the reset line
 * @part: PRM partition, not used for AM33xx
 * @inst: CM instance register offset (*_INST macro)
 * @rstctrl_reg: RM_RSTCTRL register address for this module
 * @rstst_reg: RM_RSTST register address for this module
 *
 * Some IPs like dsp, ipu or iva contain processors that require an HW
 * reset line to be asserted / deasserted in order to fully enable the
 * IP.  These modules may have multiple hard-reset lines that reset
 * different 'submodules' inside the IP block.  This function will
 * take the submodule out of reset and wait until the PRCM indicates
 * that the reset has completed before returning.  Returns 0 upon success or
 * -EINVAL upon an argument error, -EEXIST if the submodule was already out
 * of reset, or -EBUSY if the submodule did not exit reset promptly.
 */
static int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part,
					 s16 inst, u16 rstctrl_offs,
					 u16 rstst_offs)
{
	int c;
	u32 mask = 1 << st_shift;

	/* Check the current status to avoid  de-asserting the line twice */
	if (am33xx_prm_is_hardreset_asserted(shift, 0, inst, rstctrl_offs) == 0)
		return -EEXIST;

	/* Clear the reset status by writing 1 to the status bit */
	am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs);

	/* de-assert the reset control line */
	mask = 1 << shift;

	am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);

	/* wait the status to be set */
	omap_test_timeout(am33xx_prm_is_hardreset_asserted(st_shift, 0, inst,
							   rstst_offs),
			  MAX_MODULE_HARDRESET_WAIT, c);

	return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
}

static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
{
	am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK,
				(pwrst << OMAP_POWERSTATE_SHIFT),
				pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
	return 0;
}

static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
{
	u32 v;

	v = am33xx_prm_read_reg(pwrdm->prcm_offs,  pwrdm->pwrstctrl_offs);
	v &= OMAP_POWERSTATE_MASK;
	v >>= OMAP_POWERSTATE_SHIFT;

	return v;
}

static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
{
	u32 v;

	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
	v &= OMAP_POWERSTATEST_MASK;
	v >>= OMAP_POWERSTATEST_SHIFT;

	return v;
}

static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
{
	u32 v;

	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
	v &= AM33XX_LASTPOWERSTATEENTERED_MASK;
	v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT;

	return v;
}

static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
{
	am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK,
				(1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT),
				pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
	return 0;
}

static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
{
	am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK,
				AM33XX_LASTPOWERSTATEENTERED_MASK,
				pwrdm->prcm_offs, pwrdm->pwrstst_offs);
	return 0;
}

static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
{
	u32 m;

	m = pwrdm->logicretstate_mask;
	if (!m)
		return -EINVAL;

	am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
				pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);

	return 0;
}

static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
{
	u32 v;

	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
	v &= AM33XX_LOGICSTATEST_MASK;
	v >>= AM33XX_LOGICSTATEST_SHIFT;

	return v;
}

static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
{
	u32 v, m;

	m = pwrdm->logicretstate_mask;
	if (!m)
		return -EINVAL;

	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
	v &= m;
	v >>= __ffs(m);

	return v;
}

static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
		u8 pwrst)
{
	u32 m;

	m = pwrdm->mem_on_mask[bank];
	if (!m)
		return -EINVAL;

	am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
				pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);

	return 0;
}

static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
					u8 pwrst)
{
	u32 m;

	m = pwrdm->mem_ret_mask[bank];
	if (!m)
		return -EINVAL;

	am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
				pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);

	return 0;
}

static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
{
	u32 m, v;

	m = pwrdm->mem_pwrst_mask[bank];
	if (!m)
		return -EINVAL;

	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
	v &= m;
	v >>= __ffs(m);

	return v;
}

static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
{
	u32 m, v;

	m = pwrdm->mem_retst_mask[bank];
	if (!m)
		return -EINVAL;

	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
	v &= m;
	v >>= __ffs(m);

	return v;
}

static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
{
	u32 c = 0;

	/*
	 * REVISIT: pwrdm_wait_transition() may be better implemented
	 * via a callback and a periodic timer check -- how long do we expect
	 * powerdomain transitions to take?
	 */

	/* XXX Is this udelay() value meaningful? */
	while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs)
			& OMAP_INTRANSITION_MASK) &&
			(c++ < PWRDM_TRANSITION_BAILOUT))
		udelay(1);

	if (c > PWRDM_TRANSITION_BAILOUT) {
		pr_err("powerdomain: %s: waited too long to complete transition\n",
		       pwrdm->name);
		return -EAGAIN;
	}

	pr_debug("powerdomain: completed transition in %d loops\n", c);

	return 0;
}

static int am33xx_check_vcvp(void)
{
	/* No VC/VP on am33xx devices */
	return 0;
}

struct pwrdm_ops am33xx_pwrdm_operations = {
	.pwrdm_set_next_pwrst		= am33xx_pwrdm_set_next_pwrst,
	.pwrdm_read_next_pwrst		= am33xx_pwrdm_read_next_pwrst,
	.pwrdm_read_pwrst		= am33xx_pwrdm_read_pwrst,
	.pwrdm_read_prev_pwrst		= am33xx_pwrdm_read_prev_pwrst,
	.pwrdm_set_logic_retst		= am33xx_pwrdm_set_logic_retst,
	.pwrdm_read_logic_pwrst		= am33xx_pwrdm_read_logic_pwrst,
	.pwrdm_read_logic_retst		= am33xx_pwrdm_read_logic_retst,
	.pwrdm_clear_all_prev_pwrst	= am33xx_pwrdm_clear_all_prev_pwrst,
	.pwrdm_set_lowpwrstchange	= am33xx_pwrdm_set_lowpwrstchange,
	.pwrdm_read_mem_pwrst		= am33xx_pwrdm_read_mem_pwrst,
	.pwrdm_read_mem_retst		= am33xx_pwrdm_read_mem_retst,
	.pwrdm_set_mem_onst		= am33xx_pwrdm_set_mem_onst,
	.pwrdm_set_mem_retst		= am33xx_pwrdm_set_mem_retst,
	.pwrdm_wait_transition		= am33xx_pwrdm_wait_transition,
	.pwrdm_has_voltdm		= am33xx_check_vcvp,
};

static struct prm_ll_data am33xx_prm_ll_data = {
	.assert_hardreset		= am33xx_prm_assert_hardreset,
	.deassert_hardreset		= am33xx_prm_deassert_hardreset,
	.is_hardreset_asserted		= am33xx_prm_is_hardreset_asserted,
};

int __init am33xx_prm_init(void)
{
	return prm_register(&am33xx_prm_ll_data);
}

static void __exit am33xx_prm_exit(void)
{
	prm_unregister(&am33xx_prm_ll_data);
}
__exitcall(am33xx_prm_exit);
Commit	Line	Data
ddd04b98 VH	1	/*
	2	* AM33XX PRM functions
	3	*
	4	* Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License as
	8	* published by the Free Software Foundation version 2.
	9	*
	10	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	11	* kind, whether express or implied; without even the implied warranty
	12	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*/
	15
	16	#include <linux/kernel.h>
	17	#include <linux/types.h>
	18	#include <linux/errno.h>
	19	#include <linux/err.h>
	20	#include <linux/io.h>
	21
49815399	22	#include "powerdomain.h"
ddd04b98 VH	23	#include "prm33xx.h"
	24	#include "prm-regbits-33xx.h"
	25
	26	/* Read a register in a PRM instance */
	27	u32 am33xx_prm_read_reg(s16 inst, u16 idx)
	28	{
edfaf05c	29	return readl_relaxed(prm_base + inst + idx);
ddd04b98 VH	30	}
	31
	32	/* Write into a register in a PRM instance */
	33	void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
	34	{
edfaf05c	35	writel_relaxed(val, prm_base + inst + idx);
ddd04b98 VH	36	}
	37
	38	/* Read-modify-write a register in PRM. Caller must lock */
	39	u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
	40	{
	41	u32 v;
	42
	43	v = am33xx_prm_read_reg(inst, idx);
	44	v &= ~mask;
	45	v \|= bits;
	46	am33xx_prm_write_reg(v, inst, idx);
	47
	48	return v;
	49	}
	50
	51	/**
	52	* am33xx_prm_is_hardreset_asserted - read the HW reset line state of
	53	* submodules contained in the hwmod module
	54	* @shift: register bit shift corresponding to the reset line to check
1bc28b34	55	* @part: PRM partition, ignored for AM33xx
ddd04b98 VH	56	* @inst: CM instance register offset (*_INST macro)
	57	* @rstctrl_offs: RM_RSTCTRL register address offset for this module
	58	*
	59	* Returns 1 if the (sub)module hardreset line is currently asserted,
	60	* 0 if the (sub)module hardreset line is not currently asserted, or
	61	* -EINVAL upon parameter error.
	62	*/
1bc28b34 TK	63	static int am33xx_prm_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
1bc28b34 TK	64	u16 rstctrl_offs)
ddd04b98 VH	65	{
	66	u32 v;
	67
	68	v = am33xx_prm_read_reg(inst, rstctrl_offs);
	69	v &= 1 << shift;
	70	v >>= shift;
	71
	72	return v;
	73	}
	74
	75	/**
	76	* am33xx_prm_assert_hardreset - assert the HW reset line of a submodule
	77	* @shift: register bit shift corresponding to the reset line to assert
efd44dc3	78	* @part: CM partition, ignored for AM33xx
ddd04b98 VH	79	* @inst: CM instance register offset (*_INST macro)
	80	* @rstctrl_reg: RM_RSTCTRL register address for this module
	81	*
	82	* Some IPs like dsp, ipu or iva contain processors that require an HW
	83	* reset line to be asserted / deasserted in order to fully enable the
	84	* IP. These modules may have multiple hard-reset lines that reset
	85	* different 'submodules' inside the IP block. This function will
	86	* place the submodule into reset. Returns 0 upon success or -EINVAL
	87	* upon an argument error.
	88	*/
efd44dc3 TK	89	static int am33xx_prm_assert_hardreset(u8 shift, u8 part, s16 inst,
efd44dc3 TK	90	u16 rstctrl_offs)
ddd04b98 VH	91	{
	92	u32 mask = 1 << shift;
	93
	94	am33xx_prm_rmw_reg_bits(mask, mask, inst, rstctrl_offs);
	95
	96	return 0;
	97	}
	98
	99	/**
	100	* am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and
	101	* wait
	102	* @shift: register bit shift corresponding to the reset line to deassert
37fb59d7 TK	103	* @st_shift: reset status register bit shift corresponding to the reset line
37fb59d7 TK	104	* @part: PRM partition, not used for AM33xx
ddd04b98 VH	105	* @inst: CM instance register offset (*_INST macro)
	106	* @rstctrl_reg: RM_RSTCTRL register address for this module
	107	* @rstst_reg: RM_RSTST register address for this module
	108	*
	109	* Some IPs like dsp, ipu or iva contain processors that require an HW
	110	* reset line to be asserted / deasserted in order to fully enable the
	111	* IP. These modules may have multiple hard-reset lines that reset
	112	* different 'submodules' inside the IP block. This function will
	113	* take the submodule out of reset and wait until the PRCM indicates
	114	* that the reset has completed before returning. Returns 0 upon success or
	115	* -EINVAL upon an argument error, -EEXIST if the submodule was already out
	116	* of reset, or -EBUSY if the submodule did not exit reset promptly.
	117	*/
37fb59d7 TK	118	static int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, u8 part,
	119	s16 inst, u16 rstctrl_offs,
	120	u16 rstst_offs)
ddd04b98 VH	121	{
ddd04b98 VH	122	int c;
3c06f1b8	123	u32 mask = 1 << st_shift;
ddd04b98 VH	124
ddd04b98 VH	125	/* Check the current status to avoid de-asserting the line twice */
1bc28b34	126	if (am33xx_prm_is_hardreset_asserted(shift, 0, inst, rstctrl_offs) == 0)
ddd04b98 VH	127	return -EEXIST;
	128
	129	/* Clear the reset status by writing 1 to the status bit */
	130	am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs);
3c06f1b8	131
ddd04b98	132	/* de-assert the reset control line */
3c06f1b8 VB	133	mask = 1 << shift;
3c06f1b8 VB	134
ddd04b98	135	am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
ddd04b98	136
3c06f1b8	137	/* wait the status to be set */
1bc28b34	138	omap_test_timeout(am33xx_prm_is_hardreset_asserted(st_shift, 0, inst,
ddd04b98 VH	139	rstst_offs),
	140	MAX_MODULE_HARDRESET_WAIT, c);
	141
	142	return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
	143	}
49815399 PW	144
	145	static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
	146	{
	147	am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK,
	148	(pwrst << OMAP_POWERSTATE_SHIFT),
	149	pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
	150	return 0;
	151	}
	152
	153	static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
	154	{
	155	u32 v;
	156
	157	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
	158	v &= OMAP_POWERSTATE_MASK;
	159	v >>= OMAP_POWERSTATE_SHIFT;
	160
	161	return v;
	162	}
	163
	164	static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
	165	{
	166	u32 v;
	167
	168	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
	169	v &= OMAP_POWERSTATEST_MASK;
	170	v >>= OMAP_POWERSTATEST_SHIFT;
	171
	172	return v;
	173	}
	174
	175	static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
	176	{
	177	u32 v;
	178
	179	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
	180	v &= AM33XX_LASTPOWERSTATEENTERED_MASK;
	181	v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT;
	182
	183	return v;
	184	}
	185
	186	static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
	187	{
	188	am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK,
	189	(1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT),
	190	pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
	191	return 0;
	192	}
	193
	194	static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
	195	{
	196	am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK,
	197	AM33XX_LASTPOWERSTATEENTERED_MASK,
	198	pwrdm->prcm_offs, pwrdm->pwrstst_offs);
	199	return 0;
	200	}
	201
	202	static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
	203	{
	204	u32 m;
	205
	206	m = pwrdm->logicretstate_mask;
	207	if (!m)
208	return -EINVAL;
209
210	am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
211	pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
212
213	return 0;
214	}
215
216	static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
217	{
218	u32 v;
219
220	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
221	v &= AM33XX_LOGICSTATEST_MASK;
222	v >>= AM33XX_LOGICSTATEST_SHIFT;
223
224	return v;
225	}
226
227	static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
228	{
229	u32 v, m;
230
231	m = pwrdm->logicretstate_mask;
232	if (!m)
233	return -EINVAL;
234
235	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
236	v &= m;
237	v >>= __ffs(m);
238
239	return v;
240	}
241
242	static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
243	u8 pwrst)
244	{
245	u32 m;
246
247	m = pwrdm->mem_on_mask[bank];
248	if (!m)
249	return -EINVAL;
250
251	am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
252	pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
253
254	return 0;
255	}
256
257	static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
258	u8 pwrst)
259	{
260	u32 m;
261
262	m = pwrdm->mem_ret_mask[bank];
263	if (!m)
264	return -EINVAL;
265
266	am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
267	pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
268
269	return 0;
270	}
271
272	static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
273	{
274	u32 m, v;
275
276	m = pwrdm->mem_pwrst_mask[bank];
277	if (!m)
278	return -EINVAL;
279
280	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
281	v &= m;
282	v >>= __ffs(m);
283
284	return v;
285	}
286
287	static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
288	{
289	u32 m, v;
290
291	m = pwrdm->mem_retst_mask[bank];
292	if (!m)
293	return -EINVAL;
294
295	v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
296	v &= m;
297	v >>= __ffs(m);
298
299	return v;
300	}
301
302	static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
303	{
304	u32 c = 0;
305
306	/*
307	* REVISIT: pwrdm_wait_transition() may be better implemented
308	* via a callback and a periodic timer check -- how long do we expect
309	* powerdomain transitions to take?
310	*/
311
312	/* XXX Is this udelay() value meaningful? */
313	while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs)
314	& OMAP_INTRANSITION_MASK) &&
315	(c++ < PWRDM_TRANSITION_BAILOUT))
316	udelay(1);
317
318	if (c > PWRDM_TRANSITION_BAILOUT) {
319	pr_err("powerdomain: %s: waited too long to complete transition\n",
320	pwrdm->name);
321	return -EAGAIN;
322	}
323
324	pr_debug("powerdomain: completed transition in %d loops\n", c);
325
326	return 0;
327	}
328
63b0420c RN	329	static int am33xx_check_vcvp(void)
	330	{
	331	/* No VC/VP on am33xx devices */
	332	return 0;
	333	}
	334
49815399 PW	335	struct pwrdm_ops am33xx_pwrdm_operations = {
	336	.pwrdm_set_next_pwrst = am33xx_pwrdm_set_next_pwrst,
	337	.pwrdm_read_next_pwrst = am33xx_pwrdm_read_next_pwrst,
	338	.pwrdm_read_pwrst = am33xx_pwrdm_read_pwrst,
	339	.pwrdm_read_prev_pwrst = am33xx_pwrdm_read_prev_pwrst,
	340	.pwrdm_set_logic_retst = am33xx_pwrdm_set_logic_retst,
	341	.pwrdm_read_logic_pwrst = am33xx_pwrdm_read_logic_pwrst,
	342	.pwrdm_read_logic_retst = am33xx_pwrdm_read_logic_retst,
	343	.pwrdm_clear_all_prev_pwrst = am33xx_pwrdm_clear_all_prev_pwrst,
	344	.pwrdm_set_lowpwrstchange = am33xx_pwrdm_set_lowpwrstchange,
	345	.pwrdm_read_mem_pwrst = am33xx_pwrdm_read_mem_pwrst,
	346	.pwrdm_read_mem_retst = am33xx_pwrdm_read_mem_retst,
	347	.pwrdm_set_mem_onst = am33xx_pwrdm_set_mem_onst,
	348	.pwrdm_set_mem_retst = am33xx_pwrdm_set_mem_retst,
	349	.pwrdm_wait_transition = am33xx_pwrdm_wait_transition,
63b0420c	350	.pwrdm_has_voltdm = am33xx_check_vcvp,
49815399	351	};
d9bbe84f	352
efd44dc3 TK	353	static struct prm_ll_data am33xx_prm_ll_data = {
efd44dc3 TK	354	.assert_hardreset = am33xx_prm_assert_hardreset,
37fb59d7	355	.deassert_hardreset = am33xx_prm_deassert_hardreset,
1bc28b34	356	.is_hardreset_asserted = am33xx_prm_is_hardreset_asserted,
efd44dc3	357	};
d9bbe84f TK	358
	359	int __init am33xx_prm_init(void)
	360	{
	361	return prm_register(&am33xx_prm_ll_data);
	362	}
	363
	364	static void __exit am33xx_prm_exit(void)
	365	{
	366	prm_unregister(&am33xx_prm_ll_data);
	367	}
	368	__exitcall(am33xx_prm_exit);