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ARM: OMAP: PRM: Remove hardcoding of IRQENABLE_MPU_2 and IRQSTATUS_MPU_2 register...
[deliverable/linux.git] / arch / arm / mach-omap2 / prm44xx.c
CommitLineData
0be1621a
BC		 1/*
2 * OMAP4 PRM module functions
3 *
2bb2a5d3 4 * Copyright (C) 2011-2012 Texas Instruments, Inc.
0be1621a
BC		 5 * Copyright (C) 2010 Nokia Corporation
6 * Benoît Cousson
7 * Paul Walmsley
49815399 8 * Rajendra Nayak <rnayak@ti.com>
0be1621a
BC		 9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/delay.h>
17#include <linux/errno.h>
18#include <linux/err.h>
2ace831f 19#include <linux/io.h>
a8f83aef 20#include <linux/of_irq.h>
0be1621a 21
0be1621a 22
dbc04161 23#include "soc.h"
ee0839c2
TL		 24#include "iomap.h"
25#include "common.h"
58aaa599 26#include "vp.h"
d198b514 27#include "prm44xx.h"
0be1621a 28#include "prm-regbits-44xx.h"
4bb73ade
KH		 29#include "prcm44xx.h"
30#include "prminst44xx.h"
49815399 31#include "powerdomain.h"
0be1621a 32
2bb2a5d3
PW		 33/* Static data */
34
28db51f4
TK		 35static void omap44xx_prm_read_pending_irqs(unsigned long *events);
36static void omap44xx_prm_ocp_barrier(void);
37static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask);
38static void omap44xx_prm_restore_irqen(u32 *saved_mask);
4984eeaf 39static void omap44xx_prm_reconfigure_io_chain(void);
28db51f4 40
2f31b516 41static const struct omap_prcm_irq omap4_prcm_irqs[] = {
2f31b516
TK		 42 OMAP_PRCM_IRQ("io", 9, 1),
43};
44
45static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
46 .ack = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
47 .mask = OMAP4_PRM_IRQENABLE_MPU_OFFSET,
fac03f12 48 .pm_ctrl = OMAP4_PRM_IO_PMCTRL_OFFSET,
2f31b516
TK		 49 .nr_regs = 2,
50 .irqs = omap4_prcm_irqs,
51 .nr_irqs = ARRAY_SIZE(omap4_prcm_irqs),
7d7e1eba 52 .irq = 11 + OMAP44XX_IRQ_GIC_START,
0fb22a8f 53 .xlate_irq = omap4_xlate_irq,
2f31b516
TK		 54 .read_pending_irqs = &omap44xx_prm_read_pending_irqs,
55 .ocp_barrier = &omap44xx_prm_ocp_barrier,
56 .save_and_clear_irqen = &omap44xx_prm_save_and_clear_irqen,
57 .restore_irqen = &omap44xx_prm_restore_irqen,
81243651 58 .reconfigure_io_chain = &omap44xx_prm_reconfigure_io_chain,
2f31b516
TK		 59};
60
2bb2a5d3
PW		 61/*
62 * omap44xx_prm_reset_src_map - map from bits in the PRM_RSTST
63 * hardware register (which are specific to OMAP44xx SoCs) to reset
64 * source ID bit shifts (which is an OMAP SoC-independent
65 * enumeration)
66 */
67static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
62bafd1a 68 { OMAP4430_GLOBAL_WARM_SW_RST_SHIFT,
2bb2a5d3 69 OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
62bafd1a 70 { OMAP4430_GLOBAL_COLD_RST_SHIFT,
2bb2a5d3
PW		 71 OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
72 { OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT,
73 OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
74 { OMAP4430_MPU_WDT_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
75 { OMAP4430_SECURE_WDT_RST_SHIFT, OMAP_SECU_WD_RST_SRC_ID_SHIFT },
76 { OMAP4430_EXTERNAL_WARM_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT },
77 { OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT,
78 OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT },
79 { OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT,
80 OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT },
81 { OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT,
82 OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT },
83 { OMAP4430_ICEPICK_RST_SHIFT, OMAP_ICEPICK_RST_SRC_ID_SHIFT },
84 { OMAP4430_C2C_RST_SHIFT, OMAP_C2C_RST_SRC_ID_SHIFT },
85 { -1, -1 },
86};
87
2ace831f
PW		 88/* PRM low-level functions */
89
90/* Read a register in a CM/PRM instance in the PRM module */
f3f220f0 91static u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
2ace831f 92{
edfaf05c 93 return readl_relaxed(prm_base + inst + reg);
2ace831f
PW		 94}
95
96/* Write into a register in a CM/PRM instance in the PRM module */
f3f220f0 97static void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
2ace831f 98{
edfaf05c 99 writel_relaxed(val, prm_base + inst + reg);
2ace831f
PW		 100}
101
102/* Read-modify-write a register in a PRM module. Caller must lock */
f3f220f0 103static u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
2ace831f
PW		 104{
105 u32 v;
106
107 v = omap4_prm_read_inst_reg(inst, reg);
108 v &= ~mask;
109 v |= bits;
110 omap4_prm_write_inst_reg(v, inst, reg);
111
112 return v;
113}
58aaa599
KH		 114
115/* PRM VP */
116
117/*
118 * struct omap4_vp - OMAP4 VP register access description.
119 * @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP
120 * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
121 */
122struct omap4_vp {
123 u32 irqstatus_mpu;
124 u32 tranxdone_status;
125};
126
127static struct omap4_vp omap4_vp[] = {
128 [OMAP4_VP_VDD_MPU_ID] = {
129 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET,
130 .tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK,
131 },
132 [OMAP4_VP_VDD_IVA_ID] = {
133 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
134 .tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK,
135 },
136 [OMAP4_VP_VDD_CORE_ID] = {
137 .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET,
138 .tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK,
139 },
140};
141
e9f1ddcd 142static u32 omap4_prm_vp_check_txdone(u8 vp_id)
58aaa599
KH		 143{
144 struct omap4_vp *vp = &omap4_vp[vp_id];
145 u32 irqstatus;
146
147 irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
148 OMAP4430_PRM_OCP_SOCKET_INST,
149 vp->irqstatus_mpu);
150 return irqstatus & vp->tranxdone_status;
151}
152
e9f1ddcd 153static void omap4_prm_vp_clear_txdone(u8 vp_id)
58aaa599
KH		 154{
155 struct omap4_vp *vp = &omap4_vp[vp_id];
156
157 omap4_prminst_write_inst_reg(vp->tranxdone_status,
158 OMAP4430_PRM_PARTITION,
159 OMAP4430_PRM_OCP_SOCKET_INST,
160 vp->irqstatus_mpu);
161};
4bb73ade
KH		 162
163u32 omap4_prm_vcvp_read(u8 offset)
164{
390ddc19
NM		 165 s32 inst = omap4_prmst_get_prm_dev_inst();
166
167 if (inst == PRM_INSTANCE_UNKNOWN)
168 return 0;
169
4bb73ade 170 return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
390ddc19 171 inst, offset);
4bb73ade
KH		 172}
173
174void omap4_prm_vcvp_write(u32 val, u8 offset)
175{
390ddc19
NM		 176 s32 inst = omap4_prmst_get_prm_dev_inst();
177
178 if (inst == PRM_INSTANCE_UNKNOWN)
179 return;
180
4bb73ade 181 omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION,
390ddc19 182 inst, offset);
4bb73ade
KH		 183}
184
185u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
186{
390ddc19
NM		 187 s32 inst = omap4_prmst_get_prm_dev_inst();
188
189 if (inst == PRM_INSTANCE_UNKNOWN)
190 return 0;
191
4bb73ade
KH		 192 return omap4_prminst_rmw_inst_reg_bits(mask, bits,
193 OMAP4430_PRM_PARTITION,
390ddc19 194 inst,
4bb73ade
KH		 195 offset);
196}
26c98c56
PW		 197
198static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs)
199{
200 u32 mask, st;
201
202 /* XXX read mask from RAM? */
553e3222
TK		 203 mask = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
204 irqen_offs);
205 st = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, irqst_offs);
26c98c56
PW		 206
207 return mask & st;
208}
209
210/**
211 * omap44xx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
212 * @events: ptr to two consecutive u32s, preallocated by caller
213 *
214 * Read PRM_IRQSTATUS_MPU* bits, AND'ed with the currently-enabled PRM
215 * MPU IRQs, and store the result into the two u32s pointed to by @events.
216 * No return value.
217 */
28db51f4 218static void omap44xx_prm_read_pending_irqs(unsigned long *events)
26c98c56 219{
8d4be7d8 220 int i;
26c98c56 221
8d4be7d8
K		 222 for (i = 0; i < omap4_prcm_irq_setup.nr_regs; i++)
223 events[i] = _read_pending_irq_reg(omap4_prcm_irq_setup.mask +
224 i * 4, omap4_prcm_irq_setup.ack + i * 4);
26c98c56
PW		 225}
226
227/**
228 * omap44xx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
229 *
230 * Force any buffered writes to the PRM IP block to complete. Needed
231 * by the PRM IRQ handler, which reads and writes directly to the IP
232 * block, to avoid race conditions after acknowledging or clearing IRQ
233 * bits. No return value.
234 */
28db51f4 235static void omap44xx_prm_ocp_barrier(void)
26c98c56 236{
553e3222 237 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
26c98c56
PW		 238 OMAP4_REVISION_PRM_OFFSET);
239}
91285b6f
TK		 240
241/**
242 * omap44xx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU* regs
243 * @saved_mask: ptr to a u32 array to save IRQENABLE bits
244 *
245 * Save the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers to
246 * @saved_mask. @saved_mask must be allocated by the caller.
247 * Intended to be used in the PRM interrupt handler suspend callback.
248 * The OCP barrier is needed to ensure the write to disable PRM
249 * interrupts reaches the PRM before returning; otherwise, spurious
250 * interrupts might occur. No return value.
251 */
28db51f4 252static void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask)
91285b6f 253{
8d4be7d8
K		 254 int i;
255 u16 reg;
256
257 for (i = 0; i < omap4_prcm_irq_setup.nr_regs; i++) {
258 reg = omap4_prcm_irq_setup.mask + i * 4;
259
260 saved_mask[i] =
261 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
262 reg);
263 omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST, reg);
264 }
91285b6f
TK		 265
266 /* OCP barrier */
553e3222 267 omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST,
91285b6f
TK		 268 OMAP4_REVISION_PRM_OFFSET);
269}
270
271/**
272 * omap44xx_prm_restore_irqen - set PRM_IRQENABLE_MPU* registers from args
273 * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
274 *
275 * Restore the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers from
276 * @saved_mask. Intended to be used in the PRM interrupt handler resume
277 * callback to restore values saved by omap44xx_prm_save_and_clear_irqen().
278 * No OCP barrier should be needed here; any pending PRM interrupts will fire
279 * once the writes reach the PRM. No return value.
280 */
28db51f4 281static void omap44xx_prm_restore_irqen(u32 *saved_mask)
91285b6f 282{
8d4be7d8
K		 283 int i;
284
285 for (i = 0; i < omap4_prcm_irq_setup.nr_regs; i++)
286 omap4_prm_write_inst_reg(saved_mask[i],
287 OMAP4430_PRM_OCP_SOCKET_INST,
288 omap4_prcm_irq_setup.mask + i * 4);
91285b6f 289}
2f31b516 290
dea6200b
RN		 291/**
292 * omap44xx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
293 *
294 * Clear any previously-latched I/O wakeup events and ensure that the
295 * I/O wakeup gates are aligned with the current mux settings. Works
296 * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
297 * deasserting WUCLKIN and waiting for WUCLKOUT to be deasserted.
298 * No return value. XXX Are the final two steps necessary?
299 */
4984eeaf 300static void omap44xx_prm_reconfigure_io_chain(void)
dea6200b
RN		 301{
302 int i = 0;
390ddc19
NM		 303 s32 inst = omap4_prmst_get_prm_dev_inst();
304
305 if (inst == PRM_INSTANCE_UNKNOWN)
306 return;
dea6200b
RN		 307
308 /* Trigger WUCLKIN enable */
309 omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK,
310 OMAP4430_WUCLK_CTRL_MASK,
390ddc19 311 inst,
fac03f12 312 omap4_prcm_irq_setup.pm_ctrl);
dea6200b 313 omap_test_timeout(
390ddc19 314 (((omap4_prm_read_inst_reg(inst,
fac03f12 315 omap4_prcm_irq_setup.pm_ctrl) &
dea6200b
RN		 316 OMAP4430_WUCLK_STATUS_MASK) >>
317 OMAP4430_WUCLK_STATUS_SHIFT) == 1),
318 MAX_IOPAD_LATCH_TIME, i);
319 if (i == MAX_IOPAD_LATCH_TIME)
320 pr_warn("PRM: I/O chain clock line assertion timed out\n");
321
322 /* Trigger WUCLKIN disable */
323 omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0,
390ddc19 324 inst,
fac03f12 325 omap4_prcm_irq_setup.pm_ctrl);
dea6200b 326 omap_test_timeout(
390ddc19 327 (((omap4_prm_read_inst_reg(inst,
fac03f12 328 omap4_prcm_irq_setup.pm_ctrl) &
dea6200b
RN		 329 OMAP4430_WUCLK_STATUS_MASK) >>
330 OMAP4430_WUCLK_STATUS_SHIFT) == 0),
331 MAX_IOPAD_LATCH_TIME, i);
332 if (i == MAX_IOPAD_LATCH_TIME)
333 pr_warn("PRM: I/O chain clock line deassertion timed out\n");
334
335 return;
336}
337
8a680ea2
TK		 338/**
339 * omap44xx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
340 *
341 * Activates the I/O wakeup event latches and allows events logged by
342 * those latches to signal a wakeup event to the PRCM. For I/O wakeups
343 * to occur, WAKEUPENABLE bits must be set in the pad mux registers, and
344 * omap44xx_prm_reconfigure_io_chain() must be called. No return value.
345 */
346static void __init omap44xx_prm_enable_io_wakeup(void)
347{
390ddc19
NM		 348 s32 inst = omap4_prmst_get_prm_dev_inst();
349
350 if (inst == PRM_INSTANCE_UNKNOWN)
351 return;
352
8a680ea2
TK		 353 omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK,
354 OMAP4430_GLOBAL_WUEN_MASK,
390ddc19 355 inst,
fac03f12 356 omap4_prcm_irq_setup.pm_ctrl);
8a680ea2
TK		 357}
358
2bb2a5d3
PW		 359/**
360 * omap44xx_prm_read_reset_sources - return the last SoC reset source
361 *
362 * Return a u32 representing the last reset sources of the SoC. The
363 * returned reset source bits are standardized across OMAP SoCs.
364 */
365static u32 omap44xx_prm_read_reset_sources(void)
366{
367 struct prm_reset_src_map *p;
368 u32 r = 0;
369 u32 v;
390ddc19
NM		 370 s32 inst = omap4_prmst_get_prm_dev_inst();
371
372 if (inst == PRM_INSTANCE_UNKNOWN)
373 return 0;
374
2bb2a5d3 375
390ddc19 376 v = omap4_prm_read_inst_reg(inst,
2bb2a5d3
PW		 377 OMAP4_RM_RSTST);
378
379 p = omap44xx_prm_reset_src_map;
380 while (p->reg_shift >= 0 && p->std_shift >= 0) {
381 if (v & (1 << p->reg_shift))
382 r |= 1 << p->std_shift;
383 p++;
384 }
385
386 return r;
387}
388
e6d3a8b0
RN		 389/**
390 * omap44xx_prm_was_any_context_lost_old - was module hardware context lost?
391 * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
392 * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
393 * @idx: CONTEXT register offset
394 *
395 * Return 1 if any bits were set in the *_CONTEXT_* register
396 * identified by (@part, @inst, @idx), which means that some context
397 * was lost for that module; otherwise, return 0.
398 */
399static bool omap44xx_prm_was_any_context_lost_old(u8 part, s16 inst, u16 idx)
400{
401 return (omap4_prminst_read_inst_reg(part, inst, idx)) ? 1 : 0;
402}
403
404/**
405 * omap44xx_prm_clear_context_lost_flags_old - clear context loss flags
406 * @part: PRM partition ID (e.g., OMAP4430_PRM_PARTITION)
407 * @inst: PRM instance offset (e.g., OMAP4430_PRM_MPU_INST)
408 * @idx: CONTEXT register offset
409 *
410 * Clear hardware context loss bits for the module identified by
411 * (@part, @inst, @idx). No return value. XXX Writes to reserved bits;
412 * is there a way to avoid this?
413 */
414static void omap44xx_prm_clear_context_loss_flags_old(u8 part, s16 inst,
415 u16 idx)
416{
417 omap4_prminst_write_inst_reg(0xffffffff, part, inst, idx);
418}
419
49815399
PW		 420/* Powerdomain low-level functions */
421
422static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
423{
424 omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK,
425 (pwrst << OMAP_POWERSTATE_SHIFT),
426 pwrdm->prcm_partition,
427 pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
428 return 0;
429}
430
431static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
432{
433 u32 v;
434
435 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
436 OMAP4_PM_PWSTCTRL);
437 v &= OMAP_POWERSTATE_MASK;
438 v >>= OMAP_POWERSTATE_SHIFT;
439
440 return v;
441}
442
443static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm)
444{
445 u32 v;
446
447 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
448 OMAP4_PM_PWSTST);
449 v &= OMAP_POWERSTATEST_MASK;
450 v >>= OMAP_POWERSTATEST_SHIFT;
451
452 return v;
453}
454
455static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
456{
457 u32 v;
458
459 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
460 OMAP4_PM_PWSTST);
461 v &= OMAP4430_LASTPOWERSTATEENTERED_MASK;
462 v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT;
463
464 return v;
465}
466
467static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
468{
469 omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK,
470 (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT),
471 pwrdm->prcm_partition,
472 pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL);
473 return 0;
474}
475
476static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
477{
478 omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK,
479 OMAP4430_LASTPOWERSTATEENTERED_MASK,
480 pwrdm->prcm_partition,
481 pwrdm->prcm_offs, OMAP4_PM_PWSTST);
482 return 0;
483}
484
485static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
486{
487 u32 v;
488
489 v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK);
490 omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v,
491 pwrdm->prcm_partition, pwrdm->prcm_offs,
492 OMAP4_PM_PWSTCTRL);
493
494 return 0;
495}
496
497static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
498 u8 pwrst)
499{
500 u32 m;
501
502 m = omap2_pwrdm_get_mem_bank_onstate_mask(bank);
503
504 omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
505 pwrdm->prcm_partition, pwrdm->prcm_offs,
506 OMAP4_PM_PWSTCTRL);
507
508 return 0;
509}
510
511static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
512 u8 pwrst)
513{
514 u32 m;
515
516 m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
517
518 omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)),
519 pwrdm->prcm_partition, pwrdm->prcm_offs,
520 OMAP4_PM_PWSTCTRL);
521
522 return 0;
523}
524
525static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
526{
527 u32 v;
528
529 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
530 OMAP4_PM_PWSTST);
531 v &= OMAP4430_LOGICSTATEST_MASK;
532 v >>= OMAP4430_LOGICSTATEST_SHIFT;
533
534 return v;
535}
536
537static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
538{
539 u32 v;
540
541 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
542 OMAP4_PM_PWSTCTRL);
543 v &= OMAP4430_LOGICRETSTATE_MASK;
544 v >>= OMAP4430_LOGICRETSTATE_SHIFT;
545
546 return v;
547}
548
549/**
550 * omap4_pwrdm_read_prev_logic_pwrst - read the previous logic powerstate
551 * @pwrdm: struct powerdomain * to read the state for
552 *
553 * Reads the previous logic powerstate for a powerdomain. This
554 * function must determine the previous logic powerstate by first
555 * checking the previous powerstate for the domain. If that was OFF,
556 * then logic has been lost. If previous state was RETENTION, the
557 * function reads the setting for the next retention logic state to
558 * see the actual value. In every other case, the logic is
559 * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
560 * depending whether the logic was retained or not.
561 */
562static int omap4_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
563{
564 int state;
565
566 state = omap4_pwrdm_read_prev_pwrst(pwrdm);
567
568 if (state == PWRDM_POWER_OFF)
569 return PWRDM_POWER_OFF;
570
571 if (state != PWRDM_POWER_RET)
572 return PWRDM_POWER_RET;
573
574 return omap4_pwrdm_read_logic_retst(pwrdm);
575}
576
577static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
578{
579 u32 m, v;
580
581 m = omap2_pwrdm_get_mem_bank_stst_mask(bank);
582
583 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
584 OMAP4_PM_PWSTST);
585 v &= m;
586 v >>= __ffs(m);
587
588 return v;
589}
590
591static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
592{
593 u32 m, v;
594
595 m = omap2_pwrdm_get_mem_bank_retst_mask(bank);
596
597 v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs,
598 OMAP4_PM_PWSTCTRL);
599 v &= m;
600 v >>= __ffs(m);
601
602 return v;
603}
604
605/**
606 * omap4_pwrdm_read_prev_mem_pwrst - reads the previous memory powerstate
607 * @pwrdm: struct powerdomain * to read mem powerstate for
608 * @bank: memory bank index
609 *
610 * Reads the previous memory powerstate for a powerdomain. This
611 * function must determine the previous memory powerstate by first
612 * checking the previous powerstate for the domain. If that was OFF,
613 * then logic has been lost. If previous state was RETENTION, the
614 * function reads the setting for the next memory retention state to
615 * see the actual value. In every other case, the logic is
616 * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
617 * depending whether logic was retained or not.
618 */
619static int omap4_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
620{
621 int state;
622
623 state = omap4_pwrdm_read_prev_pwrst(pwrdm);
624
625 if (state == PWRDM_POWER_OFF)
626 return PWRDM_POWER_OFF;
627
628 if (state != PWRDM_POWER_RET)
629 return PWRDM_POWER_RET;
630
631 return omap4_pwrdm_read_mem_retst(pwrdm, bank);
632}
633
634static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
635{
636 u32 c = 0;
637
638 /*
639 * REVISIT: pwrdm_wait_transition() may be better implemented
640 * via a callback and a periodic timer check -- how long do we expect
641 * powerdomain transitions to take?
642 */
643
644 /* XXX Is this udelay() value meaningful? */
645 while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition,
646 pwrdm->prcm_offs,
647 OMAP4_PM_PWSTST) &
648 OMAP_INTRANSITION_MASK) &&
649 (c++ < PWRDM_TRANSITION_BAILOUT))
650 udelay(1);
651
652 if (c > PWRDM_TRANSITION_BAILOUT) {
653 pr_err("powerdomain: %s: waited too long to complete transition\n",
654 pwrdm->name);
655 return -EAGAIN;
656 }
657
658 pr_debug("powerdomain: completed transition in %d loops\n", c);
659
660 return 0;
661}
662
9a4e301d
RN		 663static int omap4_check_vcvp(void)
664{
3381eb47
TK		 665 if (prm_features & PRM_HAS_VOLTAGE)
666 return 1;
9a4e301d 667
3381eb47 668 return 0;
9a4e301d
RN		 669}
670
49815399
PW		 671struct pwrdm_ops omap4_pwrdm_operations = {
672 .pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst,
673 .pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst,
674 .pwrdm_read_pwrst = omap4_pwrdm_read_pwrst,
675 .pwrdm_read_prev_pwrst = omap4_pwrdm_read_prev_pwrst,
676 .pwrdm_set_lowpwrstchange = omap4_pwrdm_set_lowpwrstchange,
677 .pwrdm_clear_all_prev_pwrst = omap4_pwrdm_clear_all_prev_pwrst,
678 .pwrdm_set_logic_retst = omap4_pwrdm_set_logic_retst,
679 .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst,
680 .pwrdm_read_prev_logic_pwrst = omap4_pwrdm_read_prev_logic_pwrst,
681 .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst,
682 .pwrdm_read_mem_pwrst = omap4_pwrdm_read_mem_pwrst,
683 .pwrdm_read_mem_retst = omap4_pwrdm_read_mem_retst,
684 .pwrdm_read_prev_mem_pwrst = omap4_pwrdm_read_prev_mem_pwrst,
685 .pwrdm_set_mem_onst = omap4_pwrdm_set_mem_onst,
686 .pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst,
687 .pwrdm_wait_transition = omap4_pwrdm_wait_transition,
9a4e301d 688 .pwrdm_has_voltdm = omap4_check_vcvp,
49815399
PW		 689};
690
b550e47f
TK		 691static int omap44xx_prm_late_init(void);
692
2bb2a5d3
PW		 693/*
694 * XXX document
695 */
696static struct prm_ll_data omap44xx_prm_ll_data = {
697 .read_reset_sources = &omap44xx_prm_read_reset_sources,
e6d3a8b0
RN		 698 .was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old,
699 .clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old,
b550e47f 700 .late_init = &omap44xx_prm_late_init,
efd44dc3 701 .assert_hardreset = omap4_prminst_assert_hardreset,
37fb59d7 702 .deassert_hardreset = omap4_prminst_deassert_hardreset,
1bc28b34 703 .is_hardreset_asserted = omap4_prminst_is_hardreset_asserted,
61c8621e 704 .reset_system = omap4_prminst_global_warm_sw_reset,
e9f1ddcd
TK		 705 .vp_check_txdone = omap4_prm_vp_check_txdone,
706 .vp_clear_txdone = omap4_prm_vp_clear_txdone,
2bb2a5d3 707};
49815399 708
219595b6
TK		 709static const struct omap_prcm_init_data *prm_init_data;
710
ab7b2ffc 711int __init omap44xx_prm_init(const struct omap_prcm_init_data *data)
2f31b516 712{
4e3870f3
TK		 713 omap_prm_base_init();
714
219595b6
TK		 715 prm_init_data = data;
716
8b5b9a22 717 if (data->flags & PRM_HAS_IO_WAKEUP)
2541d15f 718 prm_features |= PRM_HAS_IO_WAKEUP;
139563ad 719
8b5b9a22 720 if (data->flags & PRM_HAS_VOLTAGE)
3381eb47
TK		 721 prm_features |= PRM_HAS_VOLTAGE;
722
48e0c114
TK		 723 omap4_prminst_set_prm_dev_inst(data->device_inst_offset);
724
63a293e0
PW		 725 return prm_register(&omap44xx_prm_ll_data);
726}
727
ea351c16 728static int omap44xx_prm_late_init(void)
63a293e0 729{
a8f83aef
NM		 730 int irq_num;
731
2541d15f 732 if (!(prm_features & PRM_HAS_IO_WAKEUP))
63a293e0 733 return 0;
2bb2a5d3 734
a8f83aef
NM		 735 /* OMAP4+ is DT only now */
736 if (!of_have_populated_dt())
737 return 0;
738
219595b6
TK		 739 irq_num = of_irq_get(prm_init_data->np, 0);
740 /*
741 * Already have OMAP4 IRQ num. For all other platforms, we need
742 * IRQ numbers from DT
743 */
744 if (irq_num < 0 && !(prm_init_data->flags & PRM_IRQ_DEFAULT)) {
745 if (irq_num == -EPROBE_DEFER)
746 return irq_num;
747
748 /* Have nothing to do */
749 return 0;
750 }
751
752 /* Once OMAP4 DT is filled as well */
753 if (irq_num >= 0) {
754 omap4_prcm_irq_setup.irq = irq_num;
755 omap4_prcm_irq_setup.xlate_irq = NULL;
a8f83aef
NM		 756 }
757
139563ad
PW		 758 omap44xx_prm_enable_io_wakeup();
759
760 return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
2f31b516 761}
2bb2a5d3
PW		 762
763static void __exit omap44xx_prm_exit(void)
764{
d8871cd2 765 prm_unregister(&omap44xx_prm_ll_data);
2bb2a5d3
PW		 766}
767__exitcall(omap44xx_prm_exit);
Linux kernel - Deliverables
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