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0be1621a BC |
1 | /* |
2 | * OMAP4 PRM module functions | |
3 | * | |
eaac329d | 4 | * Copyright (C) 2011 Texas Instruments, Inc. |
0be1621a BC |
5 | * Copyright (C) 2010 Nokia Corporation |
6 | * Benoît Cousson | |
7 | * Paul Walmsley | |
49815399 | 8 | * Rajendra Nayak <rnayak@ti.com> |
0be1621a BC |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/err.h> | |
2ace831f | 19 | #include <linux/io.h> |
0be1621a | 20 | |
0be1621a BC |
21 | #include <plat/prcm.h> |
22 | ||
dbc04161 | 23 | #include "soc.h" |
ee0839c2 TL |
24 | #include "iomap.h" |
25 | #include "common.h" | |
58aaa599 | 26 | #include "vp.h" |
d198b514 | 27 | #include "prm44xx.h" |
0be1621a | 28 | #include "prm-regbits-44xx.h" |
4bb73ade KH |
29 | #include "prcm44xx.h" |
30 | #include "prminst44xx.h" | |
49815399 | 31 | #include "powerdomain.h" |
0be1621a | 32 | |
2f31b516 TK |
33 | static const struct omap_prcm_irq omap4_prcm_irqs[] = { |
34 | OMAP_PRCM_IRQ("wkup", 0, 0), | |
35 | OMAP_PRCM_IRQ("io", 9, 1), | |
36 | }; | |
37 | ||
38 | static struct omap_prcm_irq_setup omap4_prcm_irq_setup = { | |
39 | .ack = OMAP4_PRM_IRQSTATUS_MPU_OFFSET, | |
40 | .mask = OMAP4_PRM_IRQENABLE_MPU_OFFSET, | |
41 | .nr_regs = 2, | |
42 | .irqs = omap4_prcm_irqs, | |
43 | .nr_irqs = ARRAY_SIZE(omap4_prcm_irqs), | |
7d7e1eba | 44 | .irq = 11 + OMAP44XX_IRQ_GIC_START, |
2f31b516 TK |
45 | .read_pending_irqs = &omap44xx_prm_read_pending_irqs, |
46 | .ocp_barrier = &omap44xx_prm_ocp_barrier, | |
47 | .save_and_clear_irqen = &omap44xx_prm_save_and_clear_irqen, | |
48 | .restore_irqen = &omap44xx_prm_restore_irqen, | |
49 | }; | |
50 | ||
2ace831f PW |
51 | /* PRM low-level functions */ |
52 | ||
53 | /* Read a register in a CM/PRM instance in the PRM module */ | |
54 | u32 omap4_prm_read_inst_reg(s16 inst, u16 reg) | |
55 | { | |
56 | return __raw_readl(OMAP44XX_PRM_REGADDR(inst, reg)); | |
57 | } | |
58 | ||
59 | /* Write into a register in a CM/PRM instance in the PRM module */ | |
60 | void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg) | |
61 | { | |
62 | __raw_writel(val, OMAP44XX_PRM_REGADDR(inst, reg)); | |
63 | } | |
64 | ||
65 | /* Read-modify-write a register in a PRM module. Caller must lock */ | |
66 | u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg) | |
67 | { | |
68 | u32 v; | |
69 | ||
70 | v = omap4_prm_read_inst_reg(inst, reg); | |
71 | v &= ~mask; | |
72 | v |= bits; | |
73 | omap4_prm_write_inst_reg(v, inst, reg); | |
74 | ||
75 | return v; | |
76 | } | |
58aaa599 KH |
77 | |
78 | /* PRM VP */ | |
79 | ||
80 | /* | |
81 | * struct omap4_vp - OMAP4 VP register access description. | |
82 | * @irqstatus_mpu: offset to IRQSTATUS_MPU register for VP | |
83 | * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg | |
84 | */ | |
85 | struct omap4_vp { | |
86 | u32 irqstatus_mpu; | |
87 | u32 tranxdone_status; | |
88 | }; | |
89 | ||
90 | static struct omap4_vp omap4_vp[] = { | |
91 | [OMAP4_VP_VDD_MPU_ID] = { | |
92 | .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET, | |
93 | .tranxdone_status = OMAP4430_VP_MPU_TRANXDONE_ST_MASK, | |
94 | }, | |
95 | [OMAP4_VP_VDD_IVA_ID] = { | |
96 | .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET, | |
97 | .tranxdone_status = OMAP4430_VP_IVA_TRANXDONE_ST_MASK, | |
98 | }, | |
99 | [OMAP4_VP_VDD_CORE_ID] = { | |
100 | .irqstatus_mpu = OMAP4_PRM_IRQSTATUS_MPU_OFFSET, | |
101 | .tranxdone_status = OMAP4430_VP_CORE_TRANXDONE_ST_MASK, | |
102 | }, | |
103 | }; | |
104 | ||
105 | u32 omap4_prm_vp_check_txdone(u8 vp_id) | |
106 | { | |
107 | struct omap4_vp *vp = &omap4_vp[vp_id]; | |
108 | u32 irqstatus; | |
109 | ||
110 | irqstatus = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, | |
111 | OMAP4430_PRM_OCP_SOCKET_INST, | |
112 | vp->irqstatus_mpu); | |
113 | return irqstatus & vp->tranxdone_status; | |
114 | } | |
115 | ||
116 | void omap4_prm_vp_clear_txdone(u8 vp_id) | |
117 | { | |
118 | struct omap4_vp *vp = &omap4_vp[vp_id]; | |
119 | ||
120 | omap4_prminst_write_inst_reg(vp->tranxdone_status, | |
121 | OMAP4430_PRM_PARTITION, | |
122 | OMAP4430_PRM_OCP_SOCKET_INST, | |
123 | vp->irqstatus_mpu); | |
124 | }; | |
4bb73ade KH |
125 | |
126 | u32 omap4_prm_vcvp_read(u8 offset) | |
127 | { | |
128 | return omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, | |
129 | OMAP4430_PRM_DEVICE_INST, offset); | |
130 | } | |
131 | ||
132 | void omap4_prm_vcvp_write(u32 val, u8 offset) | |
133 | { | |
134 | omap4_prminst_write_inst_reg(val, OMAP4430_PRM_PARTITION, | |
135 | OMAP4430_PRM_DEVICE_INST, offset); | |
136 | } | |
137 | ||
138 | u32 omap4_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset) | |
139 | { | |
140 | return omap4_prminst_rmw_inst_reg_bits(mask, bits, | |
141 | OMAP4430_PRM_PARTITION, | |
142 | OMAP4430_PRM_DEVICE_INST, | |
143 | offset); | |
144 | } | |
26c98c56 PW |
145 | |
146 | static inline u32 _read_pending_irq_reg(u16 irqen_offs, u16 irqst_offs) | |
147 | { | |
148 | u32 mask, st; | |
149 | ||
150 | /* XXX read mask from RAM? */ | |
553e3222 TK |
151 | mask = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, |
152 | irqen_offs); | |
153 | st = omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, irqst_offs); | |
26c98c56 PW |
154 | |
155 | return mask & st; | |
156 | } | |
157 | ||
158 | /** | |
159 | * omap44xx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events | |
160 | * @events: ptr to two consecutive u32s, preallocated by caller | |
161 | * | |
162 | * Read PRM_IRQSTATUS_MPU* bits, AND'ed with the currently-enabled PRM | |
163 | * MPU IRQs, and store the result into the two u32s pointed to by @events. | |
164 | * No return value. | |
165 | */ | |
166 | void omap44xx_prm_read_pending_irqs(unsigned long *events) | |
167 | { | |
168 | events[0] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_OFFSET, | |
169 | OMAP4_PRM_IRQSTATUS_MPU_OFFSET); | |
170 | ||
171 | events[1] = _read_pending_irq_reg(OMAP4_PRM_IRQENABLE_MPU_2_OFFSET, | |
172 | OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET); | |
173 | } | |
174 | ||
175 | /** | |
176 | * omap44xx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete | |
177 | * | |
178 | * Force any buffered writes to the PRM IP block to complete. Needed | |
179 | * by the PRM IRQ handler, which reads and writes directly to the IP | |
180 | * block, to avoid race conditions after acknowledging or clearing IRQ | |
181 | * bits. No return value. | |
182 | */ | |
183 | void omap44xx_prm_ocp_barrier(void) | |
184 | { | |
553e3222 | 185 | omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, |
26c98c56 PW |
186 | OMAP4_REVISION_PRM_OFFSET); |
187 | } | |
91285b6f TK |
188 | |
189 | /** | |
190 | * omap44xx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU* regs | |
191 | * @saved_mask: ptr to a u32 array to save IRQENABLE bits | |
192 | * | |
193 | * Save the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers to | |
194 | * @saved_mask. @saved_mask must be allocated by the caller. | |
195 | * Intended to be used in the PRM interrupt handler suspend callback. | |
196 | * The OCP barrier is needed to ensure the write to disable PRM | |
197 | * interrupts reaches the PRM before returning; otherwise, spurious | |
198 | * interrupts might occur. No return value. | |
199 | */ | |
200 | void omap44xx_prm_save_and_clear_irqen(u32 *saved_mask) | |
201 | { | |
202 | saved_mask[0] = | |
553e3222 | 203 | omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, |
91285b6f TK |
204 | OMAP4_PRM_IRQSTATUS_MPU_OFFSET); |
205 | saved_mask[1] = | |
553e3222 | 206 | omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, |
91285b6f TK |
207 | OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET); |
208 | ||
553e3222 | 209 | omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST, |
91285b6f | 210 | OMAP4_PRM_IRQENABLE_MPU_OFFSET); |
553e3222 | 211 | omap4_prm_write_inst_reg(0, OMAP4430_PRM_OCP_SOCKET_INST, |
91285b6f TK |
212 | OMAP4_PRM_IRQENABLE_MPU_2_OFFSET); |
213 | ||
214 | /* OCP barrier */ | |
553e3222 | 215 | omap4_prm_read_inst_reg(OMAP4430_PRM_OCP_SOCKET_INST, |
91285b6f TK |
216 | OMAP4_REVISION_PRM_OFFSET); |
217 | } | |
218 | ||
219 | /** | |
220 | * omap44xx_prm_restore_irqen - set PRM_IRQENABLE_MPU* registers from args | |
221 | * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously | |
222 | * | |
223 | * Restore the PRM_IRQENABLE_MPU and PRM_IRQENABLE_MPU_2 registers from | |
224 | * @saved_mask. Intended to be used in the PRM interrupt handler resume | |
225 | * callback to restore values saved by omap44xx_prm_save_and_clear_irqen(). | |
226 | * No OCP barrier should be needed here; any pending PRM interrupts will fire | |
227 | * once the writes reach the PRM. No return value. | |
228 | */ | |
229 | void omap44xx_prm_restore_irqen(u32 *saved_mask) | |
230 | { | |
553e3222 | 231 | omap4_prm_write_inst_reg(saved_mask[0], OMAP4430_PRM_OCP_SOCKET_INST, |
91285b6f | 232 | OMAP4_PRM_IRQENABLE_MPU_OFFSET); |
553e3222 | 233 | omap4_prm_write_inst_reg(saved_mask[1], OMAP4430_PRM_OCP_SOCKET_INST, |
91285b6f TK |
234 | OMAP4_PRM_IRQENABLE_MPU_2_OFFSET); |
235 | } | |
2f31b516 | 236 | |
dea6200b RN |
237 | /** |
238 | * omap44xx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain | |
239 | * | |
240 | * Clear any previously-latched I/O wakeup events and ensure that the | |
241 | * I/O wakeup gates are aligned with the current mux settings. Works | |
242 | * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then | |
243 | * deasserting WUCLKIN and waiting for WUCLKOUT to be deasserted. | |
244 | * No return value. XXX Are the final two steps necessary? | |
245 | */ | |
246 | void omap44xx_prm_reconfigure_io_chain(void) | |
247 | { | |
248 | int i = 0; | |
dea6200b RN |
249 | |
250 | /* Trigger WUCLKIN enable */ | |
251 | omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, | |
252 | OMAP4430_WUCLK_CTRL_MASK, | |
253 | OMAP4430_PRM_DEVICE_INST, | |
254 | OMAP4_PRM_IO_PMCTRL_OFFSET); | |
255 | omap_test_timeout( | |
256 | (((omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, | |
257 | OMAP4_PRM_IO_PMCTRL_OFFSET) & | |
258 | OMAP4430_WUCLK_STATUS_MASK) >> | |
259 | OMAP4430_WUCLK_STATUS_SHIFT) == 1), | |
260 | MAX_IOPAD_LATCH_TIME, i); | |
261 | if (i == MAX_IOPAD_LATCH_TIME) | |
262 | pr_warn("PRM: I/O chain clock line assertion timed out\n"); | |
263 | ||
264 | /* Trigger WUCLKIN disable */ | |
265 | omap4_prm_rmw_inst_reg_bits(OMAP4430_WUCLK_CTRL_MASK, 0x0, | |
266 | OMAP4430_PRM_DEVICE_INST, | |
267 | OMAP4_PRM_IO_PMCTRL_OFFSET); | |
268 | omap_test_timeout( | |
269 | (((omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST, | |
270 | OMAP4_PRM_IO_PMCTRL_OFFSET) & | |
271 | OMAP4430_WUCLK_STATUS_MASK) >> | |
272 | OMAP4430_WUCLK_STATUS_SHIFT) == 0), | |
273 | MAX_IOPAD_LATCH_TIME, i); | |
274 | if (i == MAX_IOPAD_LATCH_TIME) | |
275 | pr_warn("PRM: I/O chain clock line deassertion timed out\n"); | |
276 | ||
277 | return; | |
278 | } | |
279 | ||
8a680ea2 TK |
280 | /** |
281 | * omap44xx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches | |
282 | * | |
283 | * Activates the I/O wakeup event latches and allows events logged by | |
284 | * those latches to signal a wakeup event to the PRCM. For I/O wakeups | |
285 | * to occur, WAKEUPENABLE bits must be set in the pad mux registers, and | |
286 | * omap44xx_prm_reconfigure_io_chain() must be called. No return value. | |
287 | */ | |
288 | static void __init omap44xx_prm_enable_io_wakeup(void) | |
289 | { | |
290 | omap4_prm_rmw_inst_reg_bits(OMAP4430_GLOBAL_WUEN_MASK, | |
291 | OMAP4430_GLOBAL_WUEN_MASK, | |
292 | OMAP4430_PRM_DEVICE_INST, | |
293 | OMAP4_PRM_IO_PMCTRL_OFFSET); | |
294 | } | |
295 | ||
49815399 PW |
296 | /* Powerdomain low-level functions */ |
297 | ||
298 | static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) | |
299 | { | |
300 | omap4_prminst_rmw_inst_reg_bits(OMAP_POWERSTATE_MASK, | |
301 | (pwrst << OMAP_POWERSTATE_SHIFT), | |
302 | pwrdm->prcm_partition, | |
303 | pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); | |
304 | return 0; | |
305 | } | |
306 | ||
307 | static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) | |
308 | { | |
309 | u32 v; | |
310 | ||
311 | v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, | |
312 | OMAP4_PM_PWSTCTRL); | |
313 | v &= OMAP_POWERSTATE_MASK; | |
314 | v >>= OMAP_POWERSTATE_SHIFT; | |
315 | ||
316 | return v; | |
317 | } | |
318 | ||
319 | static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm) | |
320 | { | |
321 | u32 v; | |
322 | ||
323 | v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, | |
324 | OMAP4_PM_PWSTST); | |
325 | v &= OMAP_POWERSTATEST_MASK; | |
326 | v >>= OMAP_POWERSTATEST_SHIFT; | |
327 | ||
328 | return v; | |
329 | } | |
330 | ||
331 | static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) | |
332 | { | |
333 | u32 v; | |
334 | ||
335 | v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, | |
336 | OMAP4_PM_PWSTST); | |
337 | v &= OMAP4430_LASTPOWERSTATEENTERED_MASK; | |
338 | v >>= OMAP4430_LASTPOWERSTATEENTERED_SHIFT; | |
339 | ||
340 | return v; | |
341 | } | |
342 | ||
343 | static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) | |
344 | { | |
345 | omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK, | |
346 | (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT), | |
347 | pwrdm->prcm_partition, | |
348 | pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); | |
349 | return 0; | |
350 | } | |
351 | ||
352 | static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) | |
353 | { | |
354 | omap4_prminst_rmw_inst_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK, | |
355 | OMAP4430_LASTPOWERSTATEENTERED_MASK, | |
356 | pwrdm->prcm_partition, | |
357 | pwrdm->prcm_offs, OMAP4_PM_PWSTST); | |
358 | return 0; | |
359 | } | |
360 | ||
361 | static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) | |
362 | { | |
363 | u32 v; | |
364 | ||
365 | v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK); | |
366 | omap4_prminst_rmw_inst_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v, | |
367 | pwrdm->prcm_partition, pwrdm->prcm_offs, | |
368 | OMAP4_PM_PWSTCTRL); | |
369 | ||
370 | return 0; | |
371 | } | |
372 | ||
373 | static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, | |
374 | u8 pwrst) | |
375 | { | |
376 | u32 m; | |
377 | ||
378 | m = omap2_pwrdm_get_mem_bank_onstate_mask(bank); | |
379 | ||
380 | omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)), | |
381 | pwrdm->prcm_partition, pwrdm->prcm_offs, | |
382 | OMAP4_PM_PWSTCTRL); | |
383 | ||
384 | return 0; | |
385 | } | |
386 | ||
387 | static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, | |
388 | u8 pwrst) | |
389 | { | |
390 | u32 m; | |
391 | ||
392 | m = omap2_pwrdm_get_mem_bank_retst_mask(bank); | |
393 | ||
394 | omap4_prminst_rmw_inst_reg_bits(m, (pwrst << __ffs(m)), | |
395 | pwrdm->prcm_partition, pwrdm->prcm_offs, | |
396 | OMAP4_PM_PWSTCTRL); | |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
401 | static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) | |
402 | { | |
403 | u32 v; | |
404 | ||
405 | v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, | |
406 | OMAP4_PM_PWSTST); | |
407 | v &= OMAP4430_LOGICSTATEST_MASK; | |
408 | v >>= OMAP4430_LOGICSTATEST_SHIFT; | |
409 | ||
410 | return v; | |
411 | } | |
412 | ||
413 | static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm) | |
414 | { | |
415 | u32 v; | |
416 | ||
417 | v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, | |
418 | OMAP4_PM_PWSTCTRL); | |
419 | v &= OMAP4430_LOGICRETSTATE_MASK; | |
420 | v >>= OMAP4430_LOGICRETSTATE_SHIFT; | |
421 | ||
422 | return v; | |
423 | } | |
424 | ||
425 | /** | |
426 | * omap4_pwrdm_read_prev_logic_pwrst - read the previous logic powerstate | |
427 | * @pwrdm: struct powerdomain * to read the state for | |
428 | * | |
429 | * Reads the previous logic powerstate for a powerdomain. This | |
430 | * function must determine the previous logic powerstate by first | |
431 | * checking the previous powerstate for the domain. If that was OFF, | |
432 | * then logic has been lost. If previous state was RETENTION, the | |
433 | * function reads the setting for the next retention logic state to | |
434 | * see the actual value. In every other case, the logic is | |
435 | * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET | |
436 | * depending whether the logic was retained or not. | |
437 | */ | |
438 | static int omap4_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) | |
439 | { | |
440 | int state; | |
441 | ||
442 | state = omap4_pwrdm_read_prev_pwrst(pwrdm); | |
443 | ||
444 | if (state == PWRDM_POWER_OFF) | |
445 | return PWRDM_POWER_OFF; | |
446 | ||
447 | if (state != PWRDM_POWER_RET) | |
448 | return PWRDM_POWER_RET; | |
449 | ||
450 | return omap4_pwrdm_read_logic_retst(pwrdm); | |
451 | } | |
452 | ||
453 | static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) | |
454 | { | |
455 | u32 m, v; | |
456 | ||
457 | m = omap2_pwrdm_get_mem_bank_stst_mask(bank); | |
458 | ||
459 | v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, | |
460 | OMAP4_PM_PWSTST); | |
461 | v &= m; | |
462 | v >>= __ffs(m); | |
463 | ||
464 | return v; | |
465 | } | |
466 | ||
467 | static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) | |
468 | { | |
469 | u32 m, v; | |
470 | ||
471 | m = omap2_pwrdm_get_mem_bank_retst_mask(bank); | |
472 | ||
473 | v = omap4_prminst_read_inst_reg(pwrdm->prcm_partition, pwrdm->prcm_offs, | |
474 | OMAP4_PM_PWSTCTRL); | |
475 | v &= m; | |
476 | v >>= __ffs(m); | |
477 | ||
478 | return v; | |
479 | } | |
480 | ||
481 | /** | |
482 | * omap4_pwrdm_read_prev_mem_pwrst - reads the previous memory powerstate | |
483 | * @pwrdm: struct powerdomain * to read mem powerstate for | |
484 | * @bank: memory bank index | |
485 | * | |
486 | * Reads the previous memory powerstate for a powerdomain. This | |
487 | * function must determine the previous memory powerstate by first | |
488 | * checking the previous powerstate for the domain. If that was OFF, | |
489 | * then logic has been lost. If previous state was RETENTION, the | |
490 | * function reads the setting for the next memory retention state to | |
491 | * see the actual value. In every other case, the logic is | |
492 | * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET | |
493 | * depending whether logic was retained or not. | |
494 | */ | |
495 | static int omap4_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) | |
496 | { | |
497 | int state; | |
498 | ||
499 | state = omap4_pwrdm_read_prev_pwrst(pwrdm); | |
500 | ||
501 | if (state == PWRDM_POWER_OFF) | |
502 | return PWRDM_POWER_OFF; | |
503 | ||
504 | if (state != PWRDM_POWER_RET) | |
505 | return PWRDM_POWER_RET; | |
506 | ||
507 | return omap4_pwrdm_read_mem_retst(pwrdm, bank); | |
508 | } | |
509 | ||
510 | static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm) | |
511 | { | |
512 | u32 c = 0; | |
513 | ||
514 | /* | |
515 | * REVISIT: pwrdm_wait_transition() may be better implemented | |
516 | * via a callback and a periodic timer check -- how long do we expect | |
517 | * powerdomain transitions to take? | |
518 | */ | |
519 | ||
520 | /* XXX Is this udelay() value meaningful? */ | |
521 | while ((omap4_prminst_read_inst_reg(pwrdm->prcm_partition, | |
522 | pwrdm->prcm_offs, | |
523 | OMAP4_PM_PWSTST) & | |
524 | OMAP_INTRANSITION_MASK) && | |
525 | (c++ < PWRDM_TRANSITION_BAILOUT)) | |
526 | udelay(1); | |
527 | ||
528 | if (c > PWRDM_TRANSITION_BAILOUT) { | |
529 | pr_err("powerdomain: %s: waited too long to complete transition\n", | |
530 | pwrdm->name); | |
531 | return -EAGAIN; | |
532 | } | |
533 | ||
534 | pr_debug("powerdomain: completed transition in %d loops\n", c); | |
535 | ||
536 | return 0; | |
537 | } | |
538 | ||
539 | struct pwrdm_ops omap4_pwrdm_operations = { | |
540 | .pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst, | |
541 | .pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst, | |
542 | .pwrdm_read_pwrst = omap4_pwrdm_read_pwrst, | |
543 | .pwrdm_read_prev_pwrst = omap4_pwrdm_read_prev_pwrst, | |
544 | .pwrdm_set_lowpwrstchange = omap4_pwrdm_set_lowpwrstchange, | |
545 | .pwrdm_clear_all_prev_pwrst = omap4_pwrdm_clear_all_prev_pwrst, | |
546 | .pwrdm_set_logic_retst = omap4_pwrdm_set_logic_retst, | |
547 | .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst, | |
548 | .pwrdm_read_prev_logic_pwrst = omap4_pwrdm_read_prev_logic_pwrst, | |
549 | .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst, | |
550 | .pwrdm_read_mem_pwrst = omap4_pwrdm_read_mem_pwrst, | |
551 | .pwrdm_read_mem_retst = omap4_pwrdm_read_mem_retst, | |
552 | .pwrdm_read_prev_mem_pwrst = omap4_pwrdm_read_prev_mem_pwrst, | |
553 | .pwrdm_set_mem_onst = omap4_pwrdm_set_mem_onst, | |
554 | .pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst, | |
555 | .pwrdm_wait_transition = omap4_pwrdm_wait_transition, | |
556 | }; | |
557 | ||
558 | ||
139563ad | 559 | static int __init omap4xxx_prm_init(void) |
2f31b516 | 560 | { |
139563ad PW |
561 | if (!cpu_is_omap44xx()) |
562 | return 0; | |
563 | ||
564 | omap44xx_prm_enable_io_wakeup(); | |
565 | ||
566 | return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup); | |
2f31b516 | 567 | } |
139563ad | 568 | subsys_initcall(omap4xxx_prm_init); |