[deliverable/linux.git] / arch / arm / mach-omap2 / prm_common.c

/*
 * OMAP2+ common Power & Reset Management (PRM) IP block functions
 *
 * Copyright (C) 2011 Texas Instruments, Inc.
 * Tero Kristo <t-kristo@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *
 * For historical purposes, the API used to configure the PRM
 * interrupt handler refers to it as the "PRCM interrupt."  The
 * underlying registers are located in the PRM on OMAP3/4.
 *
 * XXX This code should eventually be moved to a PRM driver.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/slab.h>

#include "../plat-omap/common.h"
#include <plat/prcm.h>

#include "prm2xxx_3xxx.h"
#include "prm2xxx.h"
#include "prm3xxx.h"
#include "prm44xx.h"

/*
 * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
 * XXX this is technically not needed, since
 * omap_prcm_register_chain_handler() could allocate this based on the
 * actual amount of memory needed for the SoC
 */
#define OMAP_PRCM_MAX_NR_PENDING_REG		2

/*
 * prcm_irq_chips: an array of all of the "generic IRQ chips" in use
 * by the PRCM interrupt handler code.  There will be one 'chip' per
 * PRM_{IRQSTATUS,IRQENABLE}_MPU register pair.  (So OMAP3 will have
 * one "chip" and OMAP4 will have two.)
 */
static struct irq_chip_generic **prcm_irq_chips;

/*
 * prcm_irq_setup: the PRCM IRQ parameters for the hardware the code
 * is currently running on.  Defined and passed by initialization code
 * that calls omap_prcm_register_chain_handler().
 */
static struct omap_prcm_irq_setup *prcm_irq_setup;

/*
 * prm_ll_data: function pointers to SoC-specific implementations of
 * common PRM functions
 */
static struct prm_ll_data null_prm_ll_data;
static struct prm_ll_data *prm_ll_data = &null_prm_ll_data;

/* Private functions */

/*
 * Move priority events from events to priority_events array
 */
static void omap_prcm_events_filter_priority(unsigned long *events,
	unsigned long *priority_events)
{
	int i;

	for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
		priority_events[i] =
			events[i] & prcm_irq_setup->priority_mask[i];
		events[i] ^= priority_events[i];
	}
}

/*
 * PRCM Interrupt Handler
 *
 * This is a common handler for the OMAP PRCM interrupts. Pending
 * interrupts are detected by a call to prcm_pending_events and
 * dispatched accordingly. Clearing of the wakeup events should be
 * done by the SoC specific individual handlers.
 */
static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG];
	unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
	struct irq_chip *chip = irq_desc_get_chip(desc);
	unsigned int virtirq;
	int nr_irq = prcm_irq_setup->nr_regs * 32;

	/*
	 * If we are suspended, mask all interrupts from PRCM level,
	 * this does not ack them, and they will be pending until we
	 * re-enable the interrupts, at which point the
	 * omap_prcm_irq_handler will be executed again.  The
	 * _save_and_clear_irqen() function must ensure that the PRM
	 * write to disable all IRQs has reached the PRM before
	 * returning, or spurious PRCM interrupts may occur during
	 * suspend.
	 */
	if (prcm_irq_setup->suspended) {
		prcm_irq_setup->save_and_clear_irqen(prcm_irq_setup->saved_mask);
		prcm_irq_setup->suspend_save_flag = true;
	}

	/*
	 * Loop until all pending irqs are handled, since
	 * generic_handle_irq() can cause new irqs to come
	 */
	while (!prcm_irq_setup->suspended) {
		prcm_irq_setup->read_pending_irqs(pending);

		/* No bit set, then all IRQs are handled */
		if (find_first_bit(pending, nr_irq) >= nr_irq)
			break;

		omap_prcm_events_filter_priority(pending, priority_pending);

		/*
		 * Loop on all currently pending irqs so that new irqs
		 * cannot starve previously pending irqs
		 */

		/* Serve priority events first */
		for_each_set_bit(virtirq, priority_pending, nr_irq)
			generic_handle_irq(prcm_irq_setup->base_irq + virtirq);

		/* Serve normal events next */
		for_each_set_bit(virtirq, pending, nr_irq)
			generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
	}
	if (chip->irq_ack)
		chip->irq_ack(&desc->irq_data);
	if (chip->irq_eoi)
		chip->irq_eoi(&desc->irq_data);
	chip->irq_unmask(&desc->irq_data);

	prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */
}

/* Public functions */

/**
 * omap_prcm_event_to_irq - given a PRCM event name, returns the
 * corresponding IRQ on which the handler should be registered
 * @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq
 *
 * Returns the Linux internal IRQ ID corresponding to @name upon success,
 * or -ENOENT upon failure.
 */
int omap_prcm_event_to_irq(const char *name)
{
	int i;

	if (!prcm_irq_setup || !name)
		return -ENOENT;

	for (i = 0; i < prcm_irq_setup->nr_irqs; i++)
		if (!strcmp(prcm_irq_setup->irqs[i].name, name))
			return prcm_irq_setup->base_irq +
				prcm_irq_setup->irqs[i].offset;

	return -ENOENT;
}

/**
 * omap_prcm_irq_cleanup - reverses memory allocated and other steps
 * done by omap_prcm_register_chain_handler()
 *
 * No return value.
 */
void omap_prcm_irq_cleanup(void)
{
	int i;

	if (!prcm_irq_setup) {
		pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n");
		return;
	}

	if (prcm_irq_chips) {
		for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
			if (prcm_irq_chips[i])
				irq_remove_generic_chip(prcm_irq_chips[i],
					0xffffffff, 0, 0);
			prcm_irq_chips[i] = NULL;
		}
		kfree(prcm_irq_chips);
		prcm_irq_chips = NULL;
	}

	kfree(prcm_irq_setup->saved_mask);
	prcm_irq_setup->saved_mask = NULL;

	kfree(prcm_irq_setup->priority_mask);
	prcm_irq_setup->priority_mask = NULL;

	irq_set_chained_handler(prcm_irq_setup->irq, NULL);

	if (prcm_irq_setup->base_irq > 0)
		irq_free_descs(prcm_irq_setup->base_irq,
			prcm_irq_setup->nr_regs * 32);
	prcm_irq_setup->base_irq = 0;
}

void omap_prcm_irq_prepare(void)
{
	prcm_irq_setup->suspended = true;
}

void omap_prcm_irq_complete(void)
{
	prcm_irq_setup->suspended = false;

	/* If we have not saved the masks, do not attempt to restore */
	if (!prcm_irq_setup->suspend_save_flag)
		return;

	prcm_irq_setup->suspend_save_flag = false;

	/*
	 * Re-enable all masked PRCM irq sources, this causes the PRCM
	 * interrupt to fire immediately if the events were masked
	 * previously in the chain handler
	 */
	prcm_irq_setup->restore_irqen(prcm_irq_setup->saved_mask);
}

/**
 * omap_prcm_register_chain_handler - initializes the prcm chained interrupt
 * handler based on provided parameters
 * @irq_setup: hardware data about the underlying PRM/PRCM
 *
 * Set up the PRCM chained interrupt handler on the PRCM IRQ.  Sets up
 * one generic IRQ chip per PRM interrupt status/enable register pair.
 * Returns 0 upon success, -EINVAL if called twice or if invalid
 * arguments are passed, or -ENOMEM on any other error.
 */
int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
{
	int nr_regs;
	u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
	int offset, i;
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	if (!irq_setup)
		return -EINVAL;

	nr_regs = irq_setup->nr_regs;

	if (prcm_irq_setup) {
		pr_err("PRCM: already initialized; won't reinitialize\n");
		return -EINVAL;
	}

	if (nr_regs > OMAP_PRCM_MAX_NR_PENDING_REG) {
		pr_err("PRCM: nr_regs too large\n");
		return -EINVAL;
	}

	prcm_irq_setup = irq_setup;

	prcm_irq_chips = kzalloc(sizeof(void *) * nr_regs, GFP_KERNEL);
	prcm_irq_setup->saved_mask = kzalloc(sizeof(u32) * nr_regs, GFP_KERNEL);
	prcm_irq_setup->priority_mask = kzalloc(sizeof(u32) * nr_regs,
		GFP_KERNEL);

	if (!prcm_irq_chips || !prcm_irq_setup->saved_mask ||
	    !prcm_irq_setup->priority_mask) {
		pr_err("PRCM: kzalloc failed\n");
		goto err;
	}

	memset(mask, 0, sizeof(mask));

	for (i = 0; i < irq_setup->nr_irqs; i++) {
		offset = irq_setup->irqs[i].offset;
		mask[offset >> 5] |= 1 << (offset & 0x1f);
		if (irq_setup->irqs[i].priority)
			irq_setup->priority_mask[offset >> 5] |=
				1 << (offset & 0x1f);
	}

	irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler);

	irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
		0);

	if (irq_setup->base_irq < 0) {
		pr_err("PRCM: failed to allocate irq descs: %d\n",
			irq_setup->base_irq);
		goto err;
	}

	for (i = 0; i < irq_setup->nr_regs; i++) {
		gc = irq_alloc_generic_chip("PRCM", 1,
			irq_setup->base_irq + i * 32, prm_base,
			handle_level_irq);

		if (!gc) {
			pr_err("PRCM: failed to allocate generic chip\n");
			goto err;
		}
		ct = gc->chip_types;
		ct->chip.irq_ack = irq_gc_ack_set_bit;
		ct->chip.irq_mask = irq_gc_mask_clr_bit;
		ct->chip.irq_unmask = irq_gc_mask_set_bit;

		ct->regs.ack = irq_setup->ack + i * 4;
		ct->regs.mask = irq_setup->mask + i * 4;

		irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0);
		prcm_irq_chips[i] = gc;
	}

	return 0;

err:
	omap_prcm_irq_cleanup();
	return -ENOMEM;
}

/**
 * prm_read_reset_sources - return the sources of the SoC's last reset
 *
 * Return a u32 bitmask representing the reset sources that caused the
 * SoC to reset.  The low-level per-SoC functions called by this
 * function remap the SoC-specific reset source bits into an
 * OMAP-common set of reset source bits, defined in
 * arch/arm/mach-omap2/prm.h.  Returns the standardized reset source
 * u32 bitmask from the hardware upon success, or returns (1 <<
 * OMAP_UNKNOWN_RST_SRC_ID_SHIFT) if no low-level read_reset_sources()
 * function was registered.
 */
u32 prm_read_reset_sources(void)
{
	u32 ret = 1 << OMAP_UNKNOWN_RST_SRC_ID_SHIFT;

	if (prm_ll_data->read_reset_sources)
		ret = prm_ll_data->read_reset_sources();
	else
		WARN_ONCE(1, "prm: %s: no mapping function defined for reset sources\n", __func__);

	return ret;
}

/**
 * prm_register - register per-SoC low-level data with the PRM
 * @pld: low-level per-SoC OMAP PRM data & function pointers to register
 *
 * Register per-SoC low-level OMAP PRM data and function pointers with
 * the OMAP PRM common interface.  The caller must keep the data
 * pointed to by @pld valid until it calls prm_unregister() and
 * it returns successfully.  Returns 0 upon success, -EINVAL if @pld
 * is NULL, or -EEXIST if prm_register() has already been called
 * without an intervening prm_unregister().
 */
int prm_register(struct prm_ll_data *pld)
{
	if (!pld)
		return -EINVAL;

	if (prm_ll_data != &null_prm_ll_data)
		return -EEXIST;

	prm_ll_data = pld;

	return 0;
}

/**
 * prm_unregister - unregister per-SoC low-level data & function pointers
 * @pld: low-level per-SoC OMAP PRM data & function pointers to unregister
 *
 * Unregister per-SoC low-level OMAP PRM data and function pointers
 * that were previously registered with prm_register().  The
 * caller may not destroy any of the data pointed to by @pld until
 * this function returns successfully.  Returns 0 upon success, or
 * -EINVAL if @pld is NULL or if @pld does not match the struct
 * prm_ll_data * previously registered by prm_register().
 */
int prm_unregister(struct prm_ll_data *pld)
{
	if (!pld || prm_ll_data != pld)
		return -EINVAL;

	prm_ll_data = &null_prm_ll_data;

	return 0;
}
Commit	Line	Data
0a84a91c TK	1	/*
	2	* OMAP2+ common Power & Reset Management (PRM) IP block functions
	3	*
	4	* Copyright (C) 2011 Texas Instruments, Inc.
	5	* Tero Kristo <t-kristo@ti.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	*
	12	* For historical purposes, the API used to configure the PRM
	13	* interrupt handler refers to it as the "PRCM interrupt." The
	14	* underlying registers are located in the PRM on OMAP3/4.
	15	*
	16	* XXX This code should eventually be moved to a PRM driver.
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/init.h>
	22	#include <linux/io.h>
	23	#include <linux/irq.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/slab.h>
	26
e6a6e5ad	27	#include "../plat-omap/common.h"
0a84a91c	28	#include <plat/prcm.h>
0a84a91c TK	29
0a84a91c TK	30	#include "prm2xxx_3xxx.h"
2bb2a5d3 PW	31	#include "prm2xxx.h"
2bb2a5d3 PW	32	#include "prm3xxx.h"
0a84a91c TK	33	#include "prm44xx.h"
	34
	35	/*
	36	* OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
	37	* XXX this is technically not needed, since
	38	* omap_prcm_register_chain_handler() could allocate this based on the
	39	* actual amount of memory needed for the SoC
	40	*/
	41	#define OMAP_PRCM_MAX_NR_PENDING_REG 2
	42
	43	/*
	44	* prcm_irq_chips: an array of all of the "generic IRQ chips" in use
	45	* by the PRCM interrupt handler code. There will be one 'chip' per
	46	* PRM_{IRQSTATUS,IRQENABLE}_MPU register pair. (So OMAP3 will have
	47	* one "chip" and OMAP4 will have two.)
	48	*/
	49	static struct irq_chip_generic **prcm_irq_chips;
	50
	51	/*
	52	* prcm_irq_setup: the PRCM IRQ parameters for the hardware the code
	53	* is currently running on. Defined and passed by initialization code
	54	* that calls omap_prcm_register_chain_handler().
	55	*/
	56	static struct omap_prcm_irq_setup *prcm_irq_setup;
	57
e24c3573 PW	58	/*
	59	* prm_ll_data: function pointers to SoC-specific implementations of
	60	* common PRM functions
	61	*/
	62	static struct prm_ll_data null_prm_ll_data;
	63	static struct prm_ll_data *prm_ll_data = &null_prm_ll_data;
	64
0a84a91c TK	65	/* Private functions */
	66
	67	/*
	68	* Move priority events from events to priority_events array
	69	*/
	70	static void omap_prcm_events_filter_priority(unsigned long *events,
	71	unsigned long *priority_events)
	72	{
	73	int i;
	74
	75	for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
	76	priority_events[i] =
	77	events[i] & prcm_irq_setup->priority_mask[i];
	78	events[i] ^= priority_events[i];
	79	}
	80	}
	81
	82	/*
	83	* PRCM Interrupt Handler
	84	*
	85	* This is a common handler for the OMAP PRCM interrupts. Pending
	86	* interrupts are detected by a call to prcm_pending_events and
	87	* dispatched accordingly. Clearing of the wakeup events should be
	88	* done by the SoC specific individual handlers.
	89	*/
	90	static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
	91	{
	92	unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG];
	93	unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
	94	struct irq_chip *chip = irq_desc_get_chip(desc);
	95	unsigned int virtirq;
b56f2cb7	96	int nr_irq = prcm_irq_setup->nr_regs * 32;
0a84a91c	97
91285b6f TK	98	/*
	99	* If we are suspended, mask all interrupts from PRCM level,
	100	* this does not ack them, and they will be pending until we
	101	* re-enable the interrupts, at which point the
	102	* omap_prcm_irq_handler will be executed again. The
	103	* _save_and_clear_irqen() function must ensure that the PRM
	104	* write to disable all IRQs has reached the PRM before
	105	* returning, or spurious PRCM interrupts may occur during
	106	* suspend.
	107	*/
	108	if (prcm_irq_setup->suspended) {
	109	prcm_irq_setup->save_and_clear_irqen(prcm_irq_setup->saved_mask);
	110	prcm_irq_setup->suspend_save_flag = true;
	111	}
	112
0a84a91c TK	113	/*
	114	* Loop until all pending irqs are handled, since
	115	* generic_handle_irq() can cause new irqs to come
	116	*/
91285b6f	117	while (!prcm_irq_setup->suspended) {
0a84a91c TK	118	prcm_irq_setup->read_pending_irqs(pending);
	119
	120	/* No bit set, then all IRQs are handled */
b56f2cb7	121	if (find_first_bit(pending, nr_irq) >= nr_irq)
0a84a91c TK	122	break;
	123
	124	omap_prcm_events_filter_priority(pending, priority_pending);
	125
	126	/*
	127	* Loop on all currently pending irqs so that new irqs
	128	* cannot starve previously pending irqs
	129	*/
	130
	131	/* Serve priority events first */
b56f2cb7	132	for_each_set_bit(virtirq, priority_pending, nr_irq)
0a84a91c TK	133	generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
	134
	135	/* Serve normal events next */
b56f2cb7	136	for_each_set_bit(virtirq, pending, nr_irq)
0a84a91c TK	137	generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
	138	}
	139	if (chip->irq_ack)
	140	chip->irq_ack(&desc->irq_data);
	141	if (chip->irq_eoi)
	142	chip->irq_eoi(&desc->irq_data);
	143	chip->irq_unmask(&desc->irq_data);
	144
	145	prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */
	146	}
	147
	148	/* Public functions */
	149
	150	/**
	151	* omap_prcm_event_to_irq - given a PRCM event name, returns the
	152	* corresponding IRQ on which the handler should be registered
	153	* @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq
	154	*
	155	* Returns the Linux internal IRQ ID corresponding to @name upon success,
	156	* or -ENOENT upon failure.
	157	*/
	158	int omap_prcm_event_to_irq(const char *name)
	159	{
	160	int i;
	161
	162	if (!prcm_irq_setup \|\| !name)
	163	return -ENOENT;
	164
	165	for (i = 0; i < prcm_irq_setup->nr_irqs; i++)
	166	if (!strcmp(prcm_irq_setup->irqs[i].name, name))
	167	return prcm_irq_setup->base_irq +
	168	prcm_irq_setup->irqs[i].offset;
	169
	170	return -ENOENT;
	171	}
	172
	173	/**
	174	* omap_prcm_irq_cleanup - reverses memory allocated and other steps
	175	* done by omap_prcm_register_chain_handler()
	176	*
	177	* No return value.
	178	*/
	179	void omap_prcm_irq_cleanup(void)
	180	{
	181	int i;
	182
	183	if (!prcm_irq_setup) {
	184	pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n");
	185	return;
	186	}
	187
	188	if (prcm_irq_chips) {
	189	for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
	190	if (prcm_irq_chips[i])
	191	irq_remove_generic_chip(prcm_irq_chips[i],
	192	0xffffffff, 0, 0);
	193	prcm_irq_chips[i] = NULL;
	194	}
	195	kfree(prcm_irq_chips);
	196	prcm_irq_chips = NULL;
	197	}
	198
91285b6f TK	199	kfree(prcm_irq_setup->saved_mask);
	200	prcm_irq_setup->saved_mask = NULL;
	201
0a84a91c TK	202	kfree(prcm_irq_setup->priority_mask);
	203	prcm_irq_setup->priority_mask = NULL;
	204
	205	irq_set_chained_handler(prcm_irq_setup->irq, NULL);
	206
	207	if (prcm_irq_setup->base_irq > 0)
	208	irq_free_descs(prcm_irq_setup->base_irq,
	209	prcm_irq_setup->nr_regs * 32);
	210	prcm_irq_setup->base_irq = 0;
	211	}
	212
91285b6f TK	213	void omap_prcm_irq_prepare(void)
	214	{
	215	prcm_irq_setup->suspended = true;
	216	}
	217
	218	void omap_prcm_irq_complete(void)
	219	{
	220	prcm_irq_setup->suspended = false;
	221
	222	/* If we have not saved the masks, do not attempt to restore */
	223	if (!prcm_irq_setup->suspend_save_flag)
	224	return;
	225
	226	prcm_irq_setup->suspend_save_flag = false;
	227
	228	/*
	229	* Re-enable all masked PRCM irq sources, this causes the PRCM
	230	* interrupt to fire immediately if the events were masked
	231	* previously in the chain handler
	232	*/
	233	prcm_irq_setup->restore_irqen(prcm_irq_setup->saved_mask);
	234	}
	235
0a84a91c TK	236	/**
	237	* omap_prcm_register_chain_handler - initializes the prcm chained interrupt
	238	* handler based on provided parameters
	239	* @irq_setup: hardware data about the underlying PRM/PRCM
	240	*
	241	* Set up the PRCM chained interrupt handler on the PRCM IRQ. Sets up
	242	* one generic IRQ chip per PRM interrupt status/enable register pair.
	243	* Returns 0 upon success, -EINVAL if called twice or if invalid
	244	* arguments are passed, or -ENOMEM on any other error.
	245	*/
	246	int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
	247	{
eeb3711b	248	int nr_regs;
0a84a91c TK	249	u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
	250	int offset, i;
	251	struct irq_chip_generic *gc;
	252	struct irq_chip_type *ct;
	253
	254	if (!irq_setup)
	255	return -EINVAL;
	256
eeb3711b PW	257	nr_regs = irq_setup->nr_regs;
eeb3711b PW	258
0a84a91c TK	259	if (prcm_irq_setup) {
	260	pr_err("PRCM: already initialized; won't reinitialize\n");
	261	return -EINVAL;
	262	}
	263
	264	if (nr_regs > OMAP_PRCM_MAX_NR_PENDING_REG) {
	265	pr_err("PRCM: nr_regs too large\n");
	266	return -EINVAL;
	267	}
	268
	269	prcm_irq_setup = irq_setup;
	270
	271	prcm_irq_chips = kzalloc(sizeof(void ) nr_regs, GFP_KERNEL);
91285b6f	272	prcm_irq_setup->saved_mask = kzalloc(sizeof(u32) * nr_regs, GFP_KERNEL);
0a84a91c TK	273	prcm_irq_setup->priority_mask = kzalloc(sizeof(u32) * nr_regs,
	274	GFP_KERNEL);
	275
91285b6f TK	276	if (!prcm_irq_chips \|\| !prcm_irq_setup->saved_mask \|\|
91285b6f TK	277	!prcm_irq_setup->priority_mask) {
0a84a91c TK	278	pr_err("PRCM: kzalloc failed\n");
	279	goto err;
	280	}
	281
	282	memset(mask, 0, sizeof(mask));
	283
	284	for (i = 0; i < irq_setup->nr_irqs; i++) {
	285	offset = irq_setup->irqs[i].offset;
	286	mask[offset >> 5] \|= 1 << (offset & 0x1f);
	287	if (irq_setup->irqs[i].priority)
	288	irq_setup->priority_mask[offset >> 5] \|=
	289	1 << (offset & 0x1f);
	290	}
	291
	292	irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler);
	293
	294	irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
	295	0);
	296
	297	if (irq_setup->base_irq < 0) {
	298	pr_err("PRCM: failed to allocate irq descs: %d\n",
	299	irq_setup->base_irq);
	300	goto err;
	301	}
	302
4ba7c3c3	303	for (i = 0; i < irq_setup->nr_regs; i++) {
0a84a91c TK	304	gc = irq_alloc_generic_chip("PRCM", 1,
	305	irq_setup->base_irq + i * 32, prm_base,
	306	handle_level_irq);
	307
	308	if (!gc) {
	309	pr_err("PRCM: failed to allocate generic chip\n");
	310	goto err;
	311	}
	312	ct = gc->chip_types;
	313	ct->chip.irq_ack = irq_gc_ack_set_bit;
	314	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	315	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	316
	317	ct->regs.ack = irq_setup->ack + i * 4;
	318	ct->regs.mask = irq_setup->mask + i * 4;
	319
	320	irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0);
	321	prcm_irq_chips[i] = gc;
	322	}
	323
	324	return 0;
	325
	326	err:
	327	omap_prcm_irq_cleanup();
	328	return -ENOMEM;
	329	}
3f4990f4	330
2bb2a5d3 PW	331	/**
	332	* prm_read_reset_sources - return the sources of the SoC's last reset
	333	*
	334	* Return a u32 bitmask representing the reset sources that caused the
	335	* SoC to reset. The low-level per-SoC functions called by this
	336	* function remap the SoC-specific reset source bits into an
	337	* OMAP-common set of reset source bits, defined in
	338	* arch/arm/mach-omap2/prm.h. Returns the standardized reset source
	339	* u32 bitmask from the hardware upon success, or returns (1 <<
	340	* OMAP_UNKNOWN_RST_SRC_ID_SHIFT) if no low-level read_reset_sources()
	341	* function was registered.
3f4990f4	342	*/
2bb2a5d3	343	u32 prm_read_reset_sources(void)
3f4990f4	344	{
2bb2a5d3	345	u32 ret = 1 << OMAP_UNKNOWN_RST_SRC_ID_SHIFT;
3f4990f4	346
2bb2a5d3 PW	347	if (prm_ll_data->read_reset_sources)
	348	ret = prm_ll_data->read_reset_sources();
	349	else
	350	WARN_ONCE(1, "prm: %s: no mapping function defined for reset sources\n", __func__);
3f4990f4	351
2bb2a5d3	352	return ret;
3f4990f4 S	353	}
3f4990f4 S	354
e24c3573 PW	355	/**
	356	* prm_register - register per-SoC low-level data with the PRM
	357	* @pld: low-level per-SoC OMAP PRM data & function pointers to register
	358	*
	359	* Register per-SoC low-level OMAP PRM data and function pointers with
	360	* the OMAP PRM common interface. The caller must keep the data
	361	* pointed to by @pld valid until it calls prm_unregister() and
	362	* it returns successfully. Returns 0 upon success, -EINVAL if @pld
	363	* is NULL, or -EEXIST if prm_register() has already been called
	364	* without an intervening prm_unregister().
	365	*/
	366	int prm_register(struct prm_ll_data *pld)
3f4990f4	367	{
e24c3573 PW	368	if (!pld)
e24c3573 PW	369	return -EINVAL;
3f4990f4	370
e24c3573 PW	371	if (prm_ll_data != &null_prm_ll_data)
e24c3573 PW	372	return -EEXIST;
3f4990f4	373
e24c3573	374	prm_ll_data = pld;
3f4990f4	375
3f4990f4 S	376	return 0;
	377	}
	378
e24c3573 PW	379	/**
	380	* prm_unregister - unregister per-SoC low-level data & function pointers
	381	* @pld: low-level per-SoC OMAP PRM data & function pointers to unregister
	382	*
	383	* Unregister per-SoC low-level OMAP PRM data and function pointers
	384	* that were previously registered with prm_register(). The
	385	* caller may not destroy any of the data pointed to by @pld until
	386	* this function returns successfully. Returns 0 upon success, or
	387	* -EINVAL if @pld is NULL or if @pld does not match the struct
	388	* prm_ll_data * previously registered by prm_register().
	389	*/
	390	int prm_unregister(struct prm_ll_data *pld)
3f4990f4	391	{
e24c3573 PW	392	if (!pld \|\| prm_ll_data != pld)
	393	return -EINVAL;
	394
	395	prm_ll_data = &null_prm_ll_data;
3f4990f4	396
3f4990f4 S	397	return 0;
3f4990f4 S	398	}