[deliverable/linux.git] / arch / arm / mach-omap2 / prm_common.c

/*
 * OMAP2+ common Power & Reset Management (PRM) IP block functions
 *
 * Copyright (C) 2011 Texas Instruments, Inc.
 * Tero Kristo <t-kristo@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *
 * For historical purposes, the API used to configure the PRM
 * interrupt handler refers to it as the "PRCM interrupt."  The
 * underlying registers are located in the PRM on OMAP3/4.
 *
 * XXX This code should eventually be moved to a PRM driver.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/slab.h>

#include "../plat-omap/common.h"

#include "prm2xxx_3xxx.h"
#include "prm2xxx.h"
#include "prm3xxx.h"
#include "prm44xx.h"
#include "common.h"

/*
 * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
 * XXX this is technically not needed, since
 * omap_prcm_register_chain_handler() could allocate this based on the
 * actual amount of memory needed for the SoC
 */
#define OMAP_PRCM_MAX_NR_PENDING_REG		2

/*
 * prcm_irq_chips: an array of all of the "generic IRQ chips" in use
 * by the PRCM interrupt handler code.  There will be one 'chip' per
 * PRM_{IRQSTATUS,IRQENABLE}_MPU register pair.  (So OMAP3 will have
 * one "chip" and OMAP4 will have two.)
 */
static struct irq_chip_generic **prcm_irq_chips;

/*
 * prcm_irq_setup: the PRCM IRQ parameters for the hardware the code
 * is currently running on.  Defined and passed by initialization code
 * that calls omap_prcm_register_chain_handler().
 */
static struct omap_prcm_irq_setup *prcm_irq_setup;

/* prm_base: base virtual address of the PRM IP block */
void __iomem *prm_base;

/*
 * prm_ll_data: function pointers to SoC-specific implementations of
 * common PRM functions
 */
static struct prm_ll_data null_prm_ll_data;
static struct prm_ll_data *prm_ll_data = &null_prm_ll_data;

/* Private functions */

/*
 * Move priority events from events to priority_events array
 */
static void omap_prcm_events_filter_priority(unsigned long *events,
	unsigned long *priority_events)
{
	int i;

	for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
		priority_events[i] =
			events[i] & prcm_irq_setup->priority_mask[i];
		events[i] ^= priority_events[i];
	}
}

/*
 * PRCM Interrupt Handler
 *
 * This is a common handler for the OMAP PRCM interrupts. Pending
 * interrupts are detected by a call to prcm_pending_events and
 * dispatched accordingly. Clearing of the wakeup events should be
 * done by the SoC specific individual handlers.
 */
static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG];
	unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
	struct irq_chip *chip = irq_desc_get_chip(desc);
	unsigned int virtirq;
	int nr_irq = prcm_irq_setup->nr_regs * 32;

	/*
	 * If we are suspended, mask all interrupts from PRCM level,
	 * this does not ack them, and they will be pending until we
	 * re-enable the interrupts, at which point the
	 * omap_prcm_irq_handler will be executed again.  The
	 * _save_and_clear_irqen() function must ensure that the PRM
	 * write to disable all IRQs has reached the PRM before
	 * returning, or spurious PRCM interrupts may occur during
	 * suspend.
	 */
	if (prcm_irq_setup->suspended) {
		prcm_irq_setup->save_and_clear_irqen(prcm_irq_setup->saved_mask);
		prcm_irq_setup->suspend_save_flag = true;
	}

	/*
	 * Loop until all pending irqs are handled, since
	 * generic_handle_irq() can cause new irqs to come
	 */
	while (!prcm_irq_setup->suspended) {
		prcm_irq_setup->read_pending_irqs(pending);

		/* No bit set, then all IRQs are handled */
		if (find_first_bit(pending, nr_irq) >= nr_irq)
			break;

		omap_prcm_events_filter_priority(pending, priority_pending);

		/*
		 * Loop on all currently pending irqs so that new irqs
		 * cannot starve previously pending irqs
		 */

		/* Serve priority events first */
		for_each_set_bit(virtirq, priority_pending, nr_irq)
			generic_handle_irq(prcm_irq_setup->base_irq + virtirq);

		/* Serve normal events next */
		for_each_set_bit(virtirq, pending, nr_irq)
			generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
	}
	if (chip->irq_ack)
		chip->irq_ack(&desc->irq_data);
	if (chip->irq_eoi)
		chip->irq_eoi(&desc->irq_data);
	chip->irq_unmask(&desc->irq_data);

	prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */
}

/* Public functions */

/**
 * omap_prcm_event_to_irq - given a PRCM event name, returns the
 * corresponding IRQ on which the handler should be registered
 * @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq
 *
 * Returns the Linux internal IRQ ID corresponding to @name upon success,
 * or -ENOENT upon failure.
 */
int omap_prcm_event_to_irq(const char *name)
{
	int i;

	if (!prcm_irq_setup || !name)
		return -ENOENT;

	for (i = 0; i < prcm_irq_setup->nr_irqs; i++)
		if (!strcmp(prcm_irq_setup->irqs[i].name, name))
			return prcm_irq_setup->base_irq +
				prcm_irq_setup->irqs[i].offset;

	return -ENOENT;
}

/**
 * omap_prcm_irq_cleanup - reverses memory allocated and other steps
 * done by omap_prcm_register_chain_handler()
 *
 * No return value.
 */
void omap_prcm_irq_cleanup(void)
{
	int i;

	if (!prcm_irq_setup) {
		pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n");
		return;
	}

	if (prcm_irq_chips) {
		for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
			if (prcm_irq_chips[i])
				irq_remove_generic_chip(prcm_irq_chips[i],
					0xffffffff, 0, 0);
			prcm_irq_chips[i] = NULL;
		}
		kfree(prcm_irq_chips);
		prcm_irq_chips = NULL;
	}

	kfree(prcm_irq_setup->saved_mask);
	prcm_irq_setup->saved_mask = NULL;

	kfree(prcm_irq_setup->priority_mask);
	prcm_irq_setup->priority_mask = NULL;

	irq_set_chained_handler(prcm_irq_setup->irq, NULL);

	if (prcm_irq_setup->base_irq > 0)
		irq_free_descs(prcm_irq_setup->base_irq,
			prcm_irq_setup->nr_regs * 32);
	prcm_irq_setup->base_irq = 0;
}

void omap_prcm_irq_prepare(void)
{
	prcm_irq_setup->suspended = true;
}

void omap_prcm_irq_complete(void)
{
	prcm_irq_setup->suspended = false;

	/* If we have not saved the masks, do not attempt to restore */
	if (!prcm_irq_setup->suspend_save_flag)
		return;

	prcm_irq_setup->suspend_save_flag = false;

	/*
	 * Re-enable all masked PRCM irq sources, this causes the PRCM
	 * interrupt to fire immediately if the events were masked
	 * previously in the chain handler
	 */
	prcm_irq_setup->restore_irqen(prcm_irq_setup->saved_mask);
}

/**
 * omap_prcm_register_chain_handler - initializes the prcm chained interrupt
 * handler based on provided parameters
 * @irq_setup: hardware data about the underlying PRM/PRCM
 *
 * Set up the PRCM chained interrupt handler on the PRCM IRQ.  Sets up
 * one generic IRQ chip per PRM interrupt status/enable register pair.
 * Returns 0 upon success, -EINVAL if called twice or if invalid
 * arguments are passed, or -ENOMEM on any other error.
 */
int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
{
	int nr_regs;
	u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
	int offset, i;
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	if (!irq_setup)
		return -EINVAL;

	nr_regs = irq_setup->nr_regs;

	if (prcm_irq_setup) {
		pr_err("PRCM: already initialized; won't reinitialize\n");
		return -EINVAL;
	}

	if (nr_regs > OMAP_PRCM_MAX_NR_PENDING_REG) {
		pr_err("PRCM: nr_regs too large\n");
		return -EINVAL;
	}

	prcm_irq_setup = irq_setup;

	prcm_irq_chips = kzalloc(sizeof(void *) * nr_regs, GFP_KERNEL);
	prcm_irq_setup->saved_mask = kzalloc(sizeof(u32) * nr_regs, GFP_KERNEL);
	prcm_irq_setup->priority_mask = kzalloc(sizeof(u32) * nr_regs,
		GFP_KERNEL);

	if (!prcm_irq_chips || !prcm_irq_setup->saved_mask ||
	    !prcm_irq_setup->priority_mask) {
		pr_err("PRCM: kzalloc failed\n");
		goto err;
	}

	memset(mask, 0, sizeof(mask));

	for (i = 0; i < irq_setup->nr_irqs; i++) {
		offset = irq_setup->irqs[i].offset;
		mask[offset >> 5] |= 1 << (offset & 0x1f);
		if (irq_setup->irqs[i].priority)
			irq_setup->priority_mask[offset >> 5] |=
				1 << (offset & 0x1f);
	}

	irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler);

	irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
		0);

	if (irq_setup->base_irq < 0) {
		pr_err("PRCM: failed to allocate irq descs: %d\n",
			irq_setup->base_irq);
		goto err;
	}

	for (i = 0; i < irq_setup->nr_regs; i++) {
		gc = irq_alloc_generic_chip("PRCM", 1,
			irq_setup->base_irq + i * 32, prm_base,
			handle_level_irq);

		if (!gc) {
			pr_err("PRCM: failed to allocate generic chip\n");
			goto err;
		}
		ct = gc->chip_types;
		ct->chip.irq_ack = irq_gc_ack_set_bit;
		ct->chip.irq_mask = irq_gc_mask_clr_bit;
		ct->chip.irq_unmask = irq_gc_mask_set_bit;

		ct->regs.ack = irq_setup->ack + i * 4;
		ct->regs.mask = irq_setup->mask + i * 4;

		irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0);
		prcm_irq_chips[i] = gc;
	}

	return 0;

err:
	omap_prcm_irq_cleanup();
	return -ENOMEM;
}

/**
 * omap2_set_globals_prm - set the PRM base address (for early use)
 * @prm: PRM base virtual address
 *
 * XXX Will be replaced when the PRM/CM drivers are completed.
 */
void __init omap2_set_globals_prm(void __iomem *prm)
{
	prm_base = prm;
}

/**
 * prm_read_reset_sources - return the sources of the SoC's last reset
 *
 * Return a u32 bitmask representing the reset sources that caused the
 * SoC to reset.  The low-level per-SoC functions called by this
 * function remap the SoC-specific reset source bits into an
 * OMAP-common set of reset source bits, defined in
 * arch/arm/mach-omap2/prm.h.  Returns the standardized reset source
 * u32 bitmask from the hardware upon success, or returns (1 <<
 * OMAP_UNKNOWN_RST_SRC_ID_SHIFT) if no low-level read_reset_sources()
 * function was registered.
 */
u32 prm_read_reset_sources(void)
{
	u32 ret = 1 << OMAP_UNKNOWN_RST_SRC_ID_SHIFT;

	if (prm_ll_data->read_reset_sources)
		ret = prm_ll_data->read_reset_sources();
	else
		WARN_ONCE(1, "prm: %s: no mapping function defined for reset sources\n", __func__);

	return ret;
}

/**
 * prm_register - register per-SoC low-level data with the PRM
 * @pld: low-level per-SoC OMAP PRM data & function pointers to register
 *
 * Register per-SoC low-level OMAP PRM data and function pointers with
 * the OMAP PRM common interface.  The caller must keep the data
 * pointed to by @pld valid until it calls prm_unregister() and
 * it returns successfully.  Returns 0 upon success, -EINVAL if @pld
 * is NULL, or -EEXIST if prm_register() has already been called
 * without an intervening prm_unregister().
 */
int prm_register(struct prm_ll_data *pld)
{
	if (!pld)
		return -EINVAL;

	if (prm_ll_data != &null_prm_ll_data)
		return -EEXIST;

	prm_ll_data = pld;

	return 0;
}

/**
 * prm_unregister - unregister per-SoC low-level data & function pointers
 * @pld: low-level per-SoC OMAP PRM data & function pointers to unregister
 *
 * Unregister per-SoC low-level OMAP PRM data and function pointers
 * that were previously registered with prm_register().  The
 * caller may not destroy any of the data pointed to by @pld until
 * this function returns successfully.  Returns 0 upon success, or
 * -EINVAL if @pld is NULL or if @pld does not match the struct
 * prm_ll_data * previously registered by prm_register().
 */
int prm_unregister(struct prm_ll_data *pld)
{
	if (!pld || prm_ll_data != pld)
		return -EINVAL;

	prm_ll_data = &null_prm_ll_data;

	return 0;
}
Commit	Line	Data
0a84a91c TK	1	/*
	2	* OMAP2+ common Power & Reset Management (PRM) IP block functions
	3	*
	4	* Copyright (C) 2011 Texas Instruments, Inc.
	5	* Tero Kristo <t-kristo@ti.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	*
	12	* For historical purposes, the API used to configure the PRM
	13	* interrupt handler refers to it as the "PRCM interrupt." The
	14	* underlying registers are located in the PRM on OMAP3/4.
	15	*
	16	* XXX This code should eventually be moved to a PRM driver.
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/init.h>
	22	#include <linux/io.h>
	23	#include <linux/irq.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/slab.h>
	26
e6a6e5ad	27	#include "../plat-omap/common.h"
0a84a91c TK	28
0a84a91c TK	29	#include "prm2xxx_3xxx.h"
2bb2a5d3 PW	30	#include "prm2xxx.h"
2bb2a5d3 PW	31	#include "prm3xxx.h"
0a84a91c	32	#include "prm44xx.h"
d9a16f9a	33	#include "common.h"
0a84a91c TK	34
	35	/*
	36	* OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
	37	* XXX this is technically not needed, since
	38	* omap_prcm_register_chain_handler() could allocate this based on the
	39	* actual amount of memory needed for the SoC
	40	*/
	41	#define OMAP_PRCM_MAX_NR_PENDING_REG 2
	42
	43	/*
	44	* prcm_irq_chips: an array of all of the "generic IRQ chips" in use
	45	* by the PRCM interrupt handler code. There will be one 'chip' per
	46	* PRM_{IRQSTATUS,IRQENABLE}_MPU register pair. (So OMAP3 will have
	47	* one "chip" and OMAP4 will have two.)
	48	*/
	49	static struct irq_chip_generic **prcm_irq_chips;
	50
	51	/*
	52	* prcm_irq_setup: the PRCM IRQ parameters for the hardware the code
	53	* is currently running on. Defined and passed by initialization code
	54	* that calls omap_prcm_register_chain_handler().
	55	*/
	56	static struct omap_prcm_irq_setup *prcm_irq_setup;
	57
d9a16f9a PW	58	/* prm_base: base virtual address of the PRM IP block */
	59	void __iomem *prm_base;
	60
e24c3573 PW	61	/*
	62	* prm_ll_data: function pointers to SoC-specific implementations of
	63	* common PRM functions
	64	*/
	65	static struct prm_ll_data null_prm_ll_data;
	66	static struct prm_ll_data *prm_ll_data = &null_prm_ll_data;
	67
0a84a91c TK	68	/* Private functions */
	69
	70	/*
	71	* Move priority events from events to priority_events array
	72	*/
	73	static void omap_prcm_events_filter_priority(unsigned long *events,
	74	unsigned long *priority_events)
	75	{
	76	int i;
	77
	78	for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
	79	priority_events[i] =
	80	events[i] & prcm_irq_setup->priority_mask[i];
	81	events[i] ^= priority_events[i];
	82	}
	83	}
	84
	85	/*
	86	* PRCM Interrupt Handler
	87	*
	88	* This is a common handler for the OMAP PRCM interrupts. Pending
	89	* interrupts are detected by a call to prcm_pending_events and
	90	* dispatched accordingly. Clearing of the wakeup events should be
	91	* done by the SoC specific individual handlers.
	92	*/
	93	static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
	94	{
	95	unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG];
	96	unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
	97	struct irq_chip *chip = irq_desc_get_chip(desc);
	98	unsigned int virtirq;
b56f2cb7	99	int nr_irq = prcm_irq_setup->nr_regs * 32;
0a84a91c	100
91285b6f TK	101	/*
	102	* If we are suspended, mask all interrupts from PRCM level,
	103	* this does not ack them, and they will be pending until we
	104	* re-enable the interrupts, at which point the
	105	* omap_prcm_irq_handler will be executed again. The
	106	* _save_and_clear_irqen() function must ensure that the PRM
	107	* write to disable all IRQs has reached the PRM before
	108	* returning, or spurious PRCM interrupts may occur during
	109	* suspend.
	110	*/
	111	if (prcm_irq_setup->suspended) {
	112	prcm_irq_setup->save_and_clear_irqen(prcm_irq_setup->saved_mask);
	113	prcm_irq_setup->suspend_save_flag = true;
	114	}
	115
0a84a91c TK	116	/*
	117	* Loop until all pending irqs are handled, since
	118	* generic_handle_irq() can cause new irqs to come
	119	*/
91285b6f	120	while (!prcm_irq_setup->suspended) {
0a84a91c TK	121	prcm_irq_setup->read_pending_irqs(pending);
	122
	123	/* No bit set, then all IRQs are handled */
b56f2cb7	124	if (find_first_bit(pending, nr_irq) >= nr_irq)
0a84a91c TK	125	break;
	126
	127	omap_prcm_events_filter_priority(pending, priority_pending);
	128
	129	/*
	130	* Loop on all currently pending irqs so that new irqs
	131	* cannot starve previously pending irqs
	132	*/
	133
	134	/* Serve priority events first */
b56f2cb7	135	for_each_set_bit(virtirq, priority_pending, nr_irq)
0a84a91c TK	136	generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
	137
	138	/* Serve normal events next */
b56f2cb7	139	for_each_set_bit(virtirq, pending, nr_irq)
0a84a91c TK	140	generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
	141	}
	142	if (chip->irq_ack)
	143	chip->irq_ack(&desc->irq_data);
	144	if (chip->irq_eoi)
	145	chip->irq_eoi(&desc->irq_data);
	146	chip->irq_unmask(&desc->irq_data);
	147
	148	prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */
	149	}
	150
	151	/* Public functions */
	152
	153	/**
	154	* omap_prcm_event_to_irq - given a PRCM event name, returns the
	155	* corresponding IRQ on which the handler should be registered
	156	* @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq
	157	*
	158	* Returns the Linux internal IRQ ID corresponding to @name upon success,
	159	* or -ENOENT upon failure.
	160	*/
	161	int omap_prcm_event_to_irq(const char *name)
	162	{
	163	int i;
	164
	165	if (!prcm_irq_setup \|\| !name)
	166	return -ENOENT;
	167
	168	for (i = 0; i < prcm_irq_setup->nr_irqs; i++)
	169	if (!strcmp(prcm_irq_setup->irqs[i].name, name))
	170	return prcm_irq_setup->base_irq +
	171	prcm_irq_setup->irqs[i].offset;
	172
	173	return -ENOENT;
	174	}
	175
	176	/**
	177	* omap_prcm_irq_cleanup - reverses memory allocated and other steps
	178	* done by omap_prcm_register_chain_handler()
	179	*
	180	* No return value.
	181	*/
	182	void omap_prcm_irq_cleanup(void)
	183	{
	184	int i;
	185
	186	if (!prcm_irq_setup) {
	187	pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n");
	188	return;
	189	}
	190
	191	if (prcm_irq_chips) {
	192	for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
	193	if (prcm_irq_chips[i])
	194	irq_remove_generic_chip(prcm_irq_chips[i],
	195	0xffffffff, 0, 0);
	196	prcm_irq_chips[i] = NULL;
	197	}
	198	kfree(prcm_irq_chips);
	199	prcm_irq_chips = NULL;
	200	}
	201
91285b6f TK	202	kfree(prcm_irq_setup->saved_mask);
	203	prcm_irq_setup->saved_mask = NULL;
	204
0a84a91c TK	205	kfree(prcm_irq_setup->priority_mask);
	206	prcm_irq_setup->priority_mask = NULL;
	207
	208	irq_set_chained_handler(prcm_irq_setup->irq, NULL);
	209
	210	if (prcm_irq_setup->base_irq > 0)
	211	irq_free_descs(prcm_irq_setup->base_irq,
	212	prcm_irq_setup->nr_regs * 32);
	213	prcm_irq_setup->base_irq = 0;
	214	}
	215
91285b6f TK	216	void omap_prcm_irq_prepare(void)
	217	{
	218	prcm_irq_setup->suspended = true;
	219	}
	220
	221	void omap_prcm_irq_complete(void)
	222	{
	223	prcm_irq_setup->suspended = false;
	224
	225	/* If we have not saved the masks, do not attempt to restore */
	226	if (!prcm_irq_setup->suspend_save_flag)
	227	return;
	228
	229	prcm_irq_setup->suspend_save_flag = false;
	230
	231	/*
	232	* Re-enable all masked PRCM irq sources, this causes the PRCM
	233	* interrupt to fire immediately if the events were masked
	234	* previously in the chain handler
	235	*/
	236	prcm_irq_setup->restore_irqen(prcm_irq_setup->saved_mask);
	237	}
	238
0a84a91c TK	239	/**
	240	* omap_prcm_register_chain_handler - initializes the prcm chained interrupt
	241	* handler based on provided parameters
	242	* @irq_setup: hardware data about the underlying PRM/PRCM
	243	*
	244	* Set up the PRCM chained interrupt handler on the PRCM IRQ. Sets up
	245	* one generic IRQ chip per PRM interrupt status/enable register pair.
	246	* Returns 0 upon success, -EINVAL if called twice or if invalid
	247	* arguments are passed, or -ENOMEM on any other error.
	248	*/
	249	int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
	250	{
eeb3711b	251	int nr_regs;
0a84a91c TK	252	u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
	253	int offset, i;
	254	struct irq_chip_generic *gc;
	255	struct irq_chip_type *ct;
	256
	257	if (!irq_setup)
	258	return -EINVAL;
	259
eeb3711b PW	260	nr_regs = irq_setup->nr_regs;
eeb3711b PW	261
0a84a91c TK	262	if (prcm_irq_setup) {
	263	pr_err("PRCM: already initialized; won't reinitialize\n");
	264	return -EINVAL;
	265	}
	266
	267	if (nr_regs > OMAP_PRCM_MAX_NR_PENDING_REG) {
	268	pr_err("PRCM: nr_regs too large\n");
	269	return -EINVAL;
	270	}
	271
	272	prcm_irq_setup = irq_setup;
	273
	274	prcm_irq_chips = kzalloc(sizeof(void ) nr_regs, GFP_KERNEL);
91285b6f	275	prcm_irq_setup->saved_mask = kzalloc(sizeof(u32) * nr_regs, GFP_KERNEL);
0a84a91c TK	276	prcm_irq_setup->priority_mask = kzalloc(sizeof(u32) * nr_regs,
	277	GFP_KERNEL);
	278
91285b6f TK	279	if (!prcm_irq_chips \|\| !prcm_irq_setup->saved_mask \|\|
91285b6f TK	280	!prcm_irq_setup->priority_mask) {
0a84a91c TK	281	pr_err("PRCM: kzalloc failed\n");
	282	goto err;
	283	}
	284
	285	memset(mask, 0, sizeof(mask));
	286
	287	for (i = 0; i < irq_setup->nr_irqs; i++) {
	288	offset = irq_setup->irqs[i].offset;
	289	mask[offset >> 5] \|= 1 << (offset & 0x1f);
	290	if (irq_setup->irqs[i].priority)
	291	irq_setup->priority_mask[offset >> 5] \|=
	292	1 << (offset & 0x1f);
	293	}
	294
	295	irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler);
	296
	297	irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
	298	0);
	299
	300	if (irq_setup->base_irq < 0) {
	301	pr_err("PRCM: failed to allocate irq descs: %d\n",
	302	irq_setup->base_irq);
	303	goto err;
	304	}
	305
4ba7c3c3	306	for (i = 0; i < irq_setup->nr_regs; i++) {
0a84a91c TK	307	gc = irq_alloc_generic_chip("PRCM", 1,
	308	irq_setup->base_irq + i * 32, prm_base,
	309	handle_level_irq);
	310
	311	if (!gc) {
	312	pr_err("PRCM: failed to allocate generic chip\n");
	313	goto err;
	314	}
	315	ct = gc->chip_types;
	316	ct->chip.irq_ack = irq_gc_ack_set_bit;
	317	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	318	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	319
	320	ct->regs.ack = irq_setup->ack + i * 4;
	321	ct->regs.mask = irq_setup->mask + i * 4;
	322
	323	irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0);
	324	prcm_irq_chips[i] = gc;
	325	}
	326
	327	return 0;
	328
	329	err:
	330	omap_prcm_irq_cleanup();
	331	return -ENOMEM;
	332	}
3f4990f4	333
d9a16f9a PW	334	/**
	335	* omap2_set_globals_prm - set the PRM base address (for early use)
	336	* @prm: PRM base virtual address
	337	*
	338	* XXX Will be replaced when the PRM/CM drivers are completed.
	339	*/
	340	void __init omap2_set_globals_prm(void __iomem *prm)
	341	{
	342	prm_base = prm;
	343	}
	344
2bb2a5d3 PW	345	/**
	346	* prm_read_reset_sources - return the sources of the SoC's last reset
	347	*
	348	* Return a u32 bitmask representing the reset sources that caused the
	349	* SoC to reset. The low-level per-SoC functions called by this
	350	* function remap the SoC-specific reset source bits into an
	351	* OMAP-common set of reset source bits, defined in
	352	* arch/arm/mach-omap2/prm.h. Returns the standardized reset source
	353	* u32 bitmask from the hardware upon success, or returns (1 <<
	354	* OMAP_UNKNOWN_RST_SRC_ID_SHIFT) if no low-level read_reset_sources()
	355	* function was registered.
3f4990f4	356	*/
2bb2a5d3	357	u32 prm_read_reset_sources(void)
3f4990f4	358	{
2bb2a5d3	359	u32 ret = 1 << OMAP_UNKNOWN_RST_SRC_ID_SHIFT;
3f4990f4	360
2bb2a5d3 PW	361	if (prm_ll_data->read_reset_sources)
	362	ret = prm_ll_data->read_reset_sources();
	363	else
	364	WARN_ONCE(1, "prm: %s: no mapping function defined for reset sources\n", __func__);
3f4990f4	365
2bb2a5d3	366	return ret;
3f4990f4 S	367	}
3f4990f4 S	368
e24c3573 PW	369	/**
	370	* prm_register - register per-SoC low-level data with the PRM
	371	* @pld: low-level per-SoC OMAP PRM data & function pointers to register
	372	*
	373	* Register per-SoC low-level OMAP PRM data and function pointers with
	374	* the OMAP PRM common interface. The caller must keep the data
	375	* pointed to by @pld valid until it calls prm_unregister() and
	376	* it returns successfully. Returns 0 upon success, -EINVAL if @pld
	377	* is NULL, or -EEXIST if prm_register() has already been called
	378	* without an intervening prm_unregister().
	379	*/
	380	int prm_register(struct prm_ll_data *pld)
3f4990f4	381	{
e24c3573 PW	382	if (!pld)
e24c3573 PW	383	return -EINVAL;
3f4990f4	384
e24c3573 PW	385	if (prm_ll_data != &null_prm_ll_data)
e24c3573 PW	386	return -EEXIST;
3f4990f4	387
e24c3573	388	prm_ll_data = pld;
3f4990f4	389
3f4990f4 S	390	return 0;
	391	}
	392
e24c3573 PW	393	/**
	394	* prm_unregister - unregister per-SoC low-level data & function pointers
	395	* @pld: low-level per-SoC OMAP PRM data & function pointers to unregister
	396	*
	397	* Unregister per-SoC low-level OMAP PRM data and function pointers
	398	* that were previously registered with prm_register(). The
	399	* caller may not destroy any of the data pointed to by @pld until
	400	* this function returns successfully. Returns 0 upon success, or
	401	* -EINVAL if @pld is NULL or if @pld does not match the struct
	402	* prm_ll_data * previously registered by prm_register().
	403	*/
	404	int prm_unregister(struct prm_ll_data *pld)
3f4990f4	405	{
e24c3573 PW	406	if (!pld \|\| prm_ll_data != pld)
	407	return -EINVAL;
	408
	409	prm_ll_data = &null_prm_ll_data;
3f4990f4	410
3f4990f4 S	411	return 0;
3f4990f4 S	412	}