[deliverable/linux.git] / arch / arm / mach-omap2 / prm_common.c

/*
 * OMAP2+ common Power & Reset Management (PRM) IP block functions
 *
 * Copyright (C) 2011 Texas Instruments, Inc.
 * Tero Kristo <t-kristo@ti.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *
 * For historical purposes, the API used to configure the PRM
 * interrupt handler refers to it as the "PRCM interrupt."  The
 * underlying registers are located in the PRM on OMAP3/4.
 *
 * XXX This code should eventually be moved to a PRM driver.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/slab.h>

#include <plat/common.h>
#include <plat/prcm.h>

#include "prm2xxx_3xxx.h"
#include "prm44xx.h"

/*
 * OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
 * XXX this is technically not needed, since
 * omap_prcm_register_chain_handler() could allocate this based on the
 * actual amount of memory needed for the SoC
 */
#define OMAP_PRCM_MAX_NR_PENDING_REG		2

/*
 * prcm_irq_chips: an array of all of the "generic IRQ chips" in use
 * by the PRCM interrupt handler code.  There will be one 'chip' per
 * PRM_{IRQSTATUS,IRQENABLE}_MPU register pair.  (So OMAP3 will have
 * one "chip" and OMAP4 will have two.)
 */
static struct irq_chip_generic **prcm_irq_chips;

/*
 * prcm_irq_setup: the PRCM IRQ parameters for the hardware the code
 * is currently running on.  Defined and passed by initialization code
 * that calls omap_prcm_register_chain_handler().
 */
static struct omap_prcm_irq_setup *prcm_irq_setup;

/*
 * prm_ll_data: function pointers to SoC-specific implementations of
 * common PRM functions
 */
static struct prm_ll_data null_prm_ll_data;
static struct prm_ll_data *prm_ll_data = &null_prm_ll_data;

/* Private functions */

/*
 * Move priority events from events to priority_events array
 */
static void omap_prcm_events_filter_priority(unsigned long *events,
	unsigned long *priority_events)
{
	int i;

	for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
		priority_events[i] =
			events[i] & prcm_irq_setup->priority_mask[i];
		events[i] ^= priority_events[i];
	}
}

/*
 * PRCM Interrupt Handler
 *
 * This is a common handler for the OMAP PRCM interrupts. Pending
 * interrupts are detected by a call to prcm_pending_events and
 * dispatched accordingly. Clearing of the wakeup events should be
 * done by the SoC specific individual handlers.
 */
static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG];
	unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
	struct irq_chip *chip = irq_desc_get_chip(desc);
	unsigned int virtirq;
	int nr_irq = prcm_irq_setup->nr_regs * 32;

	/*
	 * If we are suspended, mask all interrupts from PRCM level,
	 * this does not ack them, and they will be pending until we
	 * re-enable the interrupts, at which point the
	 * omap_prcm_irq_handler will be executed again.  The
	 * _save_and_clear_irqen() function must ensure that the PRM
	 * write to disable all IRQs has reached the PRM before
	 * returning, or spurious PRCM interrupts may occur during
	 * suspend.
	 */
	if (prcm_irq_setup->suspended) {
		prcm_irq_setup->save_and_clear_irqen(prcm_irq_setup->saved_mask);
		prcm_irq_setup->suspend_save_flag = true;
	}

	/*
	 * Loop until all pending irqs are handled, since
	 * generic_handle_irq() can cause new irqs to come
	 */
	while (!prcm_irq_setup->suspended) {
		prcm_irq_setup->read_pending_irqs(pending);

		/* No bit set, then all IRQs are handled */
		if (find_first_bit(pending, nr_irq) >= nr_irq)
			break;

		omap_prcm_events_filter_priority(pending, priority_pending);

		/*
		 * Loop on all currently pending irqs so that new irqs
		 * cannot starve previously pending irqs
		 */

		/* Serve priority events first */
		for_each_set_bit(virtirq, priority_pending, nr_irq)
			generic_handle_irq(prcm_irq_setup->base_irq + virtirq);

		/* Serve normal events next */
		for_each_set_bit(virtirq, pending, nr_irq)
			generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
	}
	if (chip->irq_ack)
		chip->irq_ack(&desc->irq_data);
	if (chip->irq_eoi)
		chip->irq_eoi(&desc->irq_data);
	chip->irq_unmask(&desc->irq_data);

	prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */
}

/* Public functions */

/**
 * omap_prcm_event_to_irq - given a PRCM event name, returns the
 * corresponding IRQ on which the handler should be registered
 * @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq
 *
 * Returns the Linux internal IRQ ID corresponding to @name upon success,
 * or -ENOENT upon failure.
 */
int omap_prcm_event_to_irq(const char *name)
{
	int i;

	if (!prcm_irq_setup || !name)
		return -ENOENT;

	for (i = 0; i < prcm_irq_setup->nr_irqs; i++)
		if (!strcmp(prcm_irq_setup->irqs[i].name, name))
			return prcm_irq_setup->base_irq +
				prcm_irq_setup->irqs[i].offset;

	return -ENOENT;
}

/**
 * omap_prcm_irq_cleanup - reverses memory allocated and other steps
 * done by omap_prcm_register_chain_handler()
 *
 * No return value.
 */
void omap_prcm_irq_cleanup(void)
{
	int i;

	if (!prcm_irq_setup) {
		pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n");
		return;
	}

	if (prcm_irq_chips) {
		for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
			if (prcm_irq_chips[i])
				irq_remove_generic_chip(prcm_irq_chips[i],
					0xffffffff, 0, 0);
			prcm_irq_chips[i] = NULL;
		}
		kfree(prcm_irq_chips);
		prcm_irq_chips = NULL;
	}

	kfree(prcm_irq_setup->saved_mask);
	prcm_irq_setup->saved_mask = NULL;

	kfree(prcm_irq_setup->priority_mask);
	prcm_irq_setup->priority_mask = NULL;

	irq_set_chained_handler(prcm_irq_setup->irq, NULL);

	if (prcm_irq_setup->base_irq > 0)
		irq_free_descs(prcm_irq_setup->base_irq,
			prcm_irq_setup->nr_regs * 32);
	prcm_irq_setup->base_irq = 0;
}

void omap_prcm_irq_prepare(void)
{
	prcm_irq_setup->suspended = true;
}

void omap_prcm_irq_complete(void)
{
	prcm_irq_setup->suspended = false;

	/* If we have not saved the masks, do not attempt to restore */
	if (!prcm_irq_setup->suspend_save_flag)
		return;

	prcm_irq_setup->suspend_save_flag = false;

	/*
	 * Re-enable all masked PRCM irq sources, this causes the PRCM
	 * interrupt to fire immediately if the events were masked
	 * previously in the chain handler
	 */
	prcm_irq_setup->restore_irqen(prcm_irq_setup->saved_mask);
}

/**
 * omap_prcm_register_chain_handler - initializes the prcm chained interrupt
 * handler based on provided parameters
 * @irq_setup: hardware data about the underlying PRM/PRCM
 *
 * Set up the PRCM chained interrupt handler on the PRCM IRQ.  Sets up
 * one generic IRQ chip per PRM interrupt status/enable register pair.
 * Returns 0 upon success, -EINVAL if called twice or if invalid
 * arguments are passed, or -ENOMEM on any other error.
 */
int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
{
	int nr_regs;
	u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
	int offset, i;
	struct irq_chip_generic *gc;
	struct irq_chip_type *ct;

	if (!irq_setup)
		return -EINVAL;

	nr_regs = irq_setup->nr_regs;

	if (prcm_irq_setup) {
		pr_err("PRCM: already initialized; won't reinitialize\n");
		return -EINVAL;
	}

	if (nr_regs > OMAP_PRCM_MAX_NR_PENDING_REG) {
		pr_err("PRCM: nr_regs too large\n");
		return -EINVAL;
	}

	prcm_irq_setup = irq_setup;

	prcm_irq_chips = kzalloc(sizeof(void *) * nr_regs, GFP_KERNEL);
	prcm_irq_setup->saved_mask = kzalloc(sizeof(u32) * nr_regs, GFP_KERNEL);
	prcm_irq_setup->priority_mask = kzalloc(sizeof(u32) * nr_regs,
		GFP_KERNEL);

	if (!prcm_irq_chips || !prcm_irq_setup->saved_mask ||
	    !prcm_irq_setup->priority_mask) {
		pr_err("PRCM: kzalloc failed\n");
		goto err;
	}

	memset(mask, 0, sizeof(mask));

	for (i = 0; i < irq_setup->nr_irqs; i++) {
		offset = irq_setup->irqs[i].offset;
		mask[offset >> 5] |= 1 << (offset & 0x1f);
		if (irq_setup->irqs[i].priority)
			irq_setup->priority_mask[offset >> 5] |=
				1 << (offset & 0x1f);
	}

	irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler);

	irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
		0);

	if (irq_setup->base_irq < 0) {
		pr_err("PRCM: failed to allocate irq descs: %d\n",
			irq_setup->base_irq);
		goto err;
	}

	for (i = 0; i < irq_setup->nr_regs; i++) {
		gc = irq_alloc_generic_chip("PRCM", 1,
			irq_setup->base_irq + i * 32, prm_base,
			handle_level_irq);

		if (!gc) {
			pr_err("PRCM: failed to allocate generic chip\n");
			goto err;
		}
		ct = gc->chip_types;
		ct->chip.irq_ack = irq_gc_ack_set_bit;
		ct->chip.irq_mask = irq_gc_mask_clr_bit;
		ct->chip.irq_unmask = irq_gc_mask_set_bit;

		ct->regs.ack = irq_setup->ack + i * 4;
		ct->regs.mask = irq_setup->mask + i * 4;

		irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0);
		prcm_irq_chips[i] = gc;
	}

	return 0;

err:
	omap_prcm_irq_cleanup();
	return -ENOMEM;
}

/**
 * prm_register - register per-SoC low-level data with the PRM
 * @pld: low-level per-SoC OMAP PRM data & function pointers to register
 *
 * Register per-SoC low-level OMAP PRM data and function pointers with
 * the OMAP PRM common interface.  The caller must keep the data
 * pointed to by @pld valid until it calls prm_unregister() and
 * it returns successfully.  Returns 0 upon success, -EINVAL if @pld
 * is NULL, or -EEXIST if prm_register() has already been called
 * without an intervening prm_unregister().
 */
int prm_register(struct prm_ll_data *pld)
{
	if (!pld)
		return -EINVAL;

	if (prm_ll_data != &null_prm_ll_data)
		return -EEXIST;

	prm_ll_data = pld;

	return 0;
}

/**
 * prm_unregister - unregister per-SoC low-level data & function pointers
 * @pld: low-level per-SoC OMAP PRM data & function pointers to unregister
 *
 * Unregister per-SoC low-level OMAP PRM data and function pointers
 * that were previously registered with prm_register().  The
 * caller may not destroy any of the data pointed to by @pld until
 * this function returns successfully.  Returns 0 upon success, or
 * -EINVAL if @pld is NULL or if @pld does not match the struct
 * prm_ll_data * previously registered by prm_register().
 */
int prm_unregister(struct prm_ll_data *pld)
{
	if (!pld || prm_ll_data != pld)
		return -EINVAL;

	prm_ll_data = &null_prm_ll_data;

	return 0;
}
Commit	Line	Data
0a84a91c TK	1	/*
	2	* OMAP2+ common Power & Reset Management (PRM) IP block functions
	3	*
	4	* Copyright (C) 2011 Texas Instruments, Inc.
	5	* Tero Kristo <t-kristo@ti.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	*
	12	* For historical purposes, the API used to configure the PRM
	13	* interrupt handler refers to it as the "PRCM interrupt." The
	14	* underlying registers are located in the PRM on OMAP3/4.
	15	*
	16	* XXX This code should eventually be moved to a PRM driver.
	17	*/
	18
	19	#include <linux/kernel.h>
	20	#include <linux/module.h>
	21	#include <linux/init.h>
	22	#include <linux/io.h>
	23	#include <linux/irq.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/slab.h>
	26
0a84a91c TK	27	#include <plat/common.h>
0a84a91c TK	28	#include <plat/prcm.h>
0a84a91c TK	29
	30	#include "prm2xxx_3xxx.h"
	31	#include "prm44xx.h"
	32
	33	/*
	34	* OMAP_PRCM_MAX_NR_PENDING_REG: maximum number of PRM_IRQ*_MPU regs
	35	* XXX this is technically not needed, since
	36	* omap_prcm_register_chain_handler() could allocate this based on the
	37	* actual amount of memory needed for the SoC
	38	*/
	39	#define OMAP_PRCM_MAX_NR_PENDING_REG 2
	40
	41	/*
	42	* prcm_irq_chips: an array of all of the "generic IRQ chips" in use
	43	* by the PRCM interrupt handler code. There will be one 'chip' per
	44	* PRM_{IRQSTATUS,IRQENABLE}_MPU register pair. (So OMAP3 will have
	45	* one "chip" and OMAP4 will have two.)
	46	*/
	47	static struct irq_chip_generic **prcm_irq_chips;
	48
	49	/*
	50	* prcm_irq_setup: the PRCM IRQ parameters for the hardware the code
	51	* is currently running on. Defined and passed by initialization code
	52	* that calls omap_prcm_register_chain_handler().
	53	*/
	54	static struct omap_prcm_irq_setup *prcm_irq_setup;
	55
e24c3573 PW	56	/*
	57	* prm_ll_data: function pointers to SoC-specific implementations of
	58	* common PRM functions
	59	*/
	60	static struct prm_ll_data null_prm_ll_data;
	61	static struct prm_ll_data *prm_ll_data = &null_prm_ll_data;
	62
0a84a91c TK	63	/* Private functions */
	64
	65	/*
	66	* Move priority events from events to priority_events array
	67	*/
	68	static void omap_prcm_events_filter_priority(unsigned long *events,
	69	unsigned long *priority_events)
	70	{
	71	int i;
	72
	73	for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
	74	priority_events[i] =
	75	events[i] & prcm_irq_setup->priority_mask[i];
	76	events[i] ^= priority_events[i];
	77	}
	78	}
	79
	80	/*
	81	* PRCM Interrupt Handler
	82	*
	83	* This is a common handler for the OMAP PRCM interrupts. Pending
	84	* interrupts are detected by a call to prcm_pending_events and
	85	* dispatched accordingly. Clearing of the wakeup events should be
	86	* done by the SoC specific individual handlers.
	87	*/
	88	static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
	89	{
	90	unsigned long pending[OMAP_PRCM_MAX_NR_PENDING_REG];
	91	unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
	92	struct irq_chip *chip = irq_desc_get_chip(desc);
	93	unsigned int virtirq;
b56f2cb7	94	int nr_irq = prcm_irq_setup->nr_regs * 32;
0a84a91c	95
91285b6f TK	96	/*
	97	* If we are suspended, mask all interrupts from PRCM level,
	98	* this does not ack them, and they will be pending until we
	99	* re-enable the interrupts, at which point the
	100	* omap_prcm_irq_handler will be executed again. The
	101	* _save_and_clear_irqen() function must ensure that the PRM
	102	* write to disable all IRQs has reached the PRM before
	103	* returning, or spurious PRCM interrupts may occur during
	104	* suspend.
	105	*/
	106	if (prcm_irq_setup->suspended) {
	107	prcm_irq_setup->save_and_clear_irqen(prcm_irq_setup->saved_mask);
	108	prcm_irq_setup->suspend_save_flag = true;
	109	}
	110
0a84a91c TK	111	/*
	112	* Loop until all pending irqs are handled, since
	113	* generic_handle_irq() can cause new irqs to come
	114	*/
91285b6f	115	while (!prcm_irq_setup->suspended) {
0a84a91c TK	116	prcm_irq_setup->read_pending_irqs(pending);
	117
	118	/* No bit set, then all IRQs are handled */
b56f2cb7	119	if (find_first_bit(pending, nr_irq) >= nr_irq)
0a84a91c TK	120	break;
	121
	122	omap_prcm_events_filter_priority(pending, priority_pending);
	123
	124	/*
	125	* Loop on all currently pending irqs so that new irqs
	126	* cannot starve previously pending irqs
	127	*/
	128
	129	/* Serve priority events first */
b56f2cb7	130	for_each_set_bit(virtirq, priority_pending, nr_irq)
0a84a91c TK	131	generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
	132
	133	/* Serve normal events next */
b56f2cb7	134	for_each_set_bit(virtirq, pending, nr_irq)
0a84a91c TK	135	generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
	136	}
	137	if (chip->irq_ack)
	138	chip->irq_ack(&desc->irq_data);
	139	if (chip->irq_eoi)
	140	chip->irq_eoi(&desc->irq_data);
	141	chip->irq_unmask(&desc->irq_data);
	142
	143	prcm_irq_setup->ocp_barrier(); /* avoid spurious IRQs */
	144	}
	145
	146	/* Public functions */
	147
	148	/**
	149	* omap_prcm_event_to_irq - given a PRCM event name, returns the
	150	* corresponding IRQ on which the handler should be registered
	151	* @name: name of the PRCM interrupt bit to look up - see struct omap_prcm_irq
	152	*
	153	* Returns the Linux internal IRQ ID corresponding to @name upon success,
	154	* or -ENOENT upon failure.
	155	*/
	156	int omap_prcm_event_to_irq(const char *name)
	157	{
	158	int i;
	159
	160	if (!prcm_irq_setup \|\| !name)
	161	return -ENOENT;
	162
	163	for (i = 0; i < prcm_irq_setup->nr_irqs; i++)
	164	if (!strcmp(prcm_irq_setup->irqs[i].name, name))
	165	return prcm_irq_setup->base_irq +
	166	prcm_irq_setup->irqs[i].offset;
	167
	168	return -ENOENT;
	169	}
	170
	171	/**
	172	* omap_prcm_irq_cleanup - reverses memory allocated and other steps
	173	* done by omap_prcm_register_chain_handler()
	174	*
	175	* No return value.
	176	*/
	177	void omap_prcm_irq_cleanup(void)
	178	{
	179	int i;
	180
	181	if (!prcm_irq_setup) {
	182	pr_err("PRCM: IRQ handler not initialized; cannot cleanup\n");
	183	return;
	184	}
	185
	186	if (prcm_irq_chips) {
	187	for (i = 0; i < prcm_irq_setup->nr_regs; i++) {
	188	if (prcm_irq_chips[i])
	189	irq_remove_generic_chip(prcm_irq_chips[i],
	190	0xffffffff, 0, 0);
	191	prcm_irq_chips[i] = NULL;
	192	}
	193	kfree(prcm_irq_chips);
	194	prcm_irq_chips = NULL;
	195	}
	196
91285b6f TK	197	kfree(prcm_irq_setup->saved_mask);
	198	prcm_irq_setup->saved_mask = NULL;
	199
0a84a91c TK	200	kfree(prcm_irq_setup->priority_mask);
	201	prcm_irq_setup->priority_mask = NULL;
	202
	203	irq_set_chained_handler(prcm_irq_setup->irq, NULL);
	204
	205	if (prcm_irq_setup->base_irq > 0)
	206	irq_free_descs(prcm_irq_setup->base_irq,
	207	prcm_irq_setup->nr_regs * 32);
	208	prcm_irq_setup->base_irq = 0;
	209	}
	210
91285b6f TK	211	void omap_prcm_irq_prepare(void)
	212	{
	213	prcm_irq_setup->suspended = true;
	214	}
	215
	216	void omap_prcm_irq_complete(void)
	217	{
	218	prcm_irq_setup->suspended = false;
	219
	220	/* If we have not saved the masks, do not attempt to restore */
	221	if (!prcm_irq_setup->suspend_save_flag)
	222	return;
	223
	224	prcm_irq_setup->suspend_save_flag = false;
	225
	226	/*
	227	* Re-enable all masked PRCM irq sources, this causes the PRCM
	228	* interrupt to fire immediately if the events were masked
	229	* previously in the chain handler
	230	*/
	231	prcm_irq_setup->restore_irqen(prcm_irq_setup->saved_mask);
	232	}
	233
0a84a91c TK	234	/**
	235	* omap_prcm_register_chain_handler - initializes the prcm chained interrupt
	236	* handler based on provided parameters
	237	* @irq_setup: hardware data about the underlying PRM/PRCM
	238	*
	239	* Set up the PRCM chained interrupt handler on the PRCM IRQ. Sets up
	240	* one generic IRQ chip per PRM interrupt status/enable register pair.
	241	* Returns 0 upon success, -EINVAL if called twice or if invalid
	242	* arguments are passed, or -ENOMEM on any other error.
	243	*/
	244	int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
	245	{
eeb3711b	246	int nr_regs;
0a84a91c TK	247	u32 mask[OMAP_PRCM_MAX_NR_PENDING_REG];
	248	int offset, i;
	249	struct irq_chip_generic *gc;
	250	struct irq_chip_type *ct;
	251
	252	if (!irq_setup)
	253	return -EINVAL;
	254
eeb3711b PW	255	nr_regs = irq_setup->nr_regs;
eeb3711b PW	256
0a84a91c TK	257	if (prcm_irq_setup) {
	258	pr_err("PRCM: already initialized; won't reinitialize\n");
	259	return -EINVAL;
	260	}
	261
	262	if (nr_regs > OMAP_PRCM_MAX_NR_PENDING_REG) {
	263	pr_err("PRCM: nr_regs too large\n");
	264	return -EINVAL;
	265	}
	266
	267	prcm_irq_setup = irq_setup;
	268
	269	prcm_irq_chips = kzalloc(sizeof(void ) nr_regs, GFP_KERNEL);
91285b6f	270	prcm_irq_setup->saved_mask = kzalloc(sizeof(u32) * nr_regs, GFP_KERNEL);
0a84a91c TK	271	prcm_irq_setup->priority_mask = kzalloc(sizeof(u32) * nr_regs,
	272	GFP_KERNEL);
	273
91285b6f TK	274	if (!prcm_irq_chips \|\| !prcm_irq_setup->saved_mask \|\|
91285b6f TK	275	!prcm_irq_setup->priority_mask) {
0a84a91c TK	276	pr_err("PRCM: kzalloc failed\n");
	277	goto err;
	278	}
	279
	280	memset(mask, 0, sizeof(mask));
	281
	282	for (i = 0; i < irq_setup->nr_irqs; i++) {
	283	offset = irq_setup->irqs[i].offset;
	284	mask[offset >> 5] \|= 1 << (offset & 0x1f);
	285	if (irq_setup->irqs[i].priority)
	286	irq_setup->priority_mask[offset >> 5] \|=
	287	1 << (offset & 0x1f);
	288	}
	289
	290	irq_set_chained_handler(irq_setup->irq, omap_prcm_irq_handler);
	291
	292	irq_setup->base_irq = irq_alloc_descs(-1, 0, irq_setup->nr_regs * 32,
	293	0);
	294
	295	if (irq_setup->base_irq < 0) {
	296	pr_err("PRCM: failed to allocate irq descs: %d\n",
	297	irq_setup->base_irq);
	298	goto err;
	299	}
	300
4ba7c3c3	301	for (i = 0; i < irq_setup->nr_regs; i++) {
0a84a91c TK	302	gc = irq_alloc_generic_chip("PRCM", 1,
	303	irq_setup->base_irq + i * 32, prm_base,
	304	handle_level_irq);
	305
	306	if (!gc) {
	307	pr_err("PRCM: failed to allocate generic chip\n");
	308	goto err;
	309	}
	310	ct = gc->chip_types;
	311	ct->chip.irq_ack = irq_gc_ack_set_bit;
	312	ct->chip.irq_mask = irq_gc_mask_clr_bit;
	313	ct->chip.irq_unmask = irq_gc_mask_set_bit;
	314
	315	ct->regs.ack = irq_setup->ack + i * 4;
	316	ct->regs.mask = irq_setup->mask + i * 4;
	317
	318	irq_setup_generic_chip(gc, mask[i], 0, IRQ_NOREQUEST, 0);
	319	prcm_irq_chips[i] = gc;
	320	}
	321
	322	return 0;
	323
	324	err:
	325	omap_prcm_irq_cleanup();
	326	return -ENOMEM;
	327	}
e24c3573 PW	328
	329	/**
	330	* prm_register - register per-SoC low-level data with the PRM
	331	* @pld: low-level per-SoC OMAP PRM data & function pointers to register
	332	*
	333	* Register per-SoC low-level OMAP PRM data and function pointers with
	334	* the OMAP PRM common interface. The caller must keep the data
	335	* pointed to by @pld valid until it calls prm_unregister() and
	336	* it returns successfully. Returns 0 upon success, -EINVAL if @pld
	337	* is NULL, or -EEXIST if prm_register() has already been called
	338	* without an intervening prm_unregister().
	339	*/
	340	int prm_register(struct prm_ll_data *pld)
	341	{
	342	if (!pld)
	343	return -EINVAL;
	344
	345	if (prm_ll_data != &null_prm_ll_data)
	346	return -EEXIST;
	347
	348	prm_ll_data = pld;
	349
	350	return 0;
	351	}
	352
	353	/**
	354	* prm_unregister - unregister per-SoC low-level data & function pointers
	355	* @pld: low-level per-SoC OMAP PRM data & function pointers to unregister
	356	*
	357	* Unregister per-SoC low-level OMAP PRM data and function pointers
	358	* that were previously registered with prm_register(). The
	359	* caller may not destroy any of the data pointed to by @pld until
	360	* this function returns successfully. Returns 0 upon success, or
	361	* -EINVAL if @pld is NULL or if @pld does not match the struct
	362	* prm_ll_data * previously registered by prm_register().
	363	*/
	364	int prm_unregister(struct prm_ll_data *pld)
	365	{
	366	if (!pld \|\| prm_ll_data != pld)
	367	return -EINVAL;
	368
	369	prm_ll_data = &null_prm_ll_data;
	370
	371	return 0;
	372	}