[deliverable/linux.git] / arch / arm / mach-omap2 / prminst44xx.c

/*
 * OMAP4 PRM instance functions
 *
 * Copyright (C) 2009 Nokia Corporation
 * Copyright (C) 2011 Texas Instruments, Inc.
 * Paul Walmsley
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/err.h>
#include <linux/io.h>

#include "iomap.h"
#include "common.h"
#include "prcm-common.h"
#include "prm44xx.h"
#include "prm54xx.h"
#include "prm7xx.h"
#include "prminst44xx.h"
#include "prm-regbits-44xx.h"
#include "prcm44xx.h"
#include "prcm43xx.h"
#include "prcm_mpu44xx.h"
#include "soc.h"

static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS];

/**
 * omap_prm_base_init - Populates the prm partitions
 *
 * Populates the base addresses of the _prm_bases
 * array used for read/write of prm module registers.
 */
void omap_prm_base_init(void)
{
	_prm_bases[OMAP4430_PRM_PARTITION] = prm_base;
	_prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
}

/* Read a register in a PRM instance */
u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
{
	BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
	       part == OMAP4430_INVALID_PRCM_PARTITION ||
	       !_prm_bases[part]);
	return readl_relaxed(_prm_bases[part] + inst + idx);
}

/* Write into a register in a PRM instance */
void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
{
	BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
	       part == OMAP4430_INVALID_PRCM_PARTITION ||
	       !_prm_bases[part]);
	writel_relaxed(val, _prm_bases[part] + inst + idx);
}

/* Read-modify-write a register in PRM. Caller must lock */
u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
				    u16 idx)
{
	u32 v;

	v = omap4_prminst_read_inst_reg(part, inst, idx);
	v &= ~mask;
	v |= bits;
	omap4_prminst_write_inst_reg(v, part, inst, idx);

	return v;
}

/*
 * Address offset (in bytes) between the reset control and the reset
 * status registers: 4 bytes on OMAP4
 */
#define OMAP4_RST_CTRL_ST_OFFSET		4

/**
 * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
 * submodules contained in the hwmod module
 * @rstctrl_reg: RM_RSTCTRL register address for this module
 * @shift: register bit shift corresponding to the reset line to check
 *
 * Returns 1 if the (sub)module hardreset line is currently asserted,
 * 0 if the (sub)module hardreset line is not currently asserted, or
 * -EINVAL upon parameter error.
 */
int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
					u16 rstctrl_offs)
{
	u32 v;

	v = omap4_prminst_read_inst_reg(part, inst, rstctrl_offs);
	v &= 1 << shift;
	v >>= shift;

	return v;
}

/**
 * omap4_prminst_assert_hardreset - assert the HW reset line of a submodule
 * @rstctrl_reg: RM_RSTCTRL register address for this module
 * @shift: register bit shift corresponding to the reset line to assert
 *
 * Some IPs like dsp, ipu or iva contain processors that require an HW
 * reset line to be asserted / deasserted in order to fully enable the
 * IP.  These modules may have multiple hard-reset lines that reset
 * different 'submodules' inside the IP block.  This function will
 * place the submodule into reset.  Returns 0 upon success or -EINVAL
 * upon an argument error.
 */
int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
				   u16 rstctrl_offs)
{
	u32 mask = 1 << shift;

	omap4_prminst_rmw_inst_reg_bits(mask, mask, part, inst, rstctrl_offs);

	return 0;
}

/**
 * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
 * wait
 * @rstctrl_reg: RM_RSTCTRL register address for this module
 * @shift: register bit shift corresponding to the reset line to deassert
 *
 * Some IPs like dsp, ipu or iva contain processors that require an HW
 * reset line to be asserted / deasserted in order to fully enable the
 * IP.  These modules may have multiple hard-reset lines that reset
 * different 'submodules' inside the IP block.  This function will
 * take the submodule out of reset and wait until the PRCM indicates
 * that the reset has completed before returning.  Returns 0 upon success or
 * -EINVAL upon an argument error, -EEXIST if the submodule was already out
 * of reset, or -EBUSY if the submodule did not exit reset promptly.
 */
int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
				     u16 rstctrl_offs)
{
	int c;
	u32 mask = 1 << shift;
	u16 rstst_offs = rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET;

	/* Check the current status to avoid de-asserting the line twice */
	if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
						rstctrl_offs) == 0)
		return -EEXIST;

	/* Clear the reset status by writing 1 to the status bit */
	omap4_prminst_rmw_inst_reg_bits(0xffffffff, mask, part, inst,
					rstst_offs);
	/* de-assert the reset control line */
	omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
	/* wait the status to be set */
	omap_test_timeout(omap4_prminst_is_hardreset_asserted(shift, part, inst,
							      rstst_offs),
			  MAX_MODULE_HARDRESET_WAIT, c);

	return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
}


void omap4_prminst_global_warm_sw_reset(void)
{
	u32 v;
	s16 dev_inst;

	if (cpu_is_omap44xx())
		dev_inst = OMAP4430_PRM_DEVICE_INST;
	else if (soc_is_omap54xx())
		dev_inst = OMAP54XX_PRM_DEVICE_INST;
	else if (soc_is_dra7xx())
		dev_inst = DRA7XX_PRM_DEVICE_INST;
	else if (soc_is_am43xx())
		dev_inst = AM43XX_PRM_DEVICE_INST;
	else
		return;

	v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, dev_inst,
					OMAP4_PRM_RSTCTRL_OFFSET);
	v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
	omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
				 dev_inst,
				 OMAP4_PRM_RSTCTRL_OFFSET);

	/* OCP barrier */
	v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
				    dev_inst,
				    OMAP4_PRM_RSTCTRL_OFFSET);
}
Commit	Line	Data
2ace831f PW	1	/*
	2	* OMAP4 PRM instance functions
	3	*
	4	* Copyright (C) 2009 Nokia Corporation
eaac329d	5	* Copyright (C) 2011 Texas Instruments, Inc.
2ace831f PW	6	* Paul Walmsley
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/types.h>
	15	#include <linux/errno.h>
	16	#include <linux/err.h>
	17	#include <linux/io.h>
	18
ee0839c2	19	#include "iomap.h"
4e65331c	20	#include "common.h"
610eb8c2	21	#include "prcm-common.h"
2ace831f	22	#include "prm44xx.h"
1d597b07 RN	23	#include "prm54xx.h"
1d597b07 RN	24	#include "prm7xx.h"
2ace831f PW	25	#include "prminst44xx.h"
	26	#include "prm-regbits-44xx.h"
	27	#include "prcm44xx.h"
a7daf64a	28	#include "prcm43xx.h"
2ace831f	29	#include "prcm_mpu44xx.h"
1d597b07	30	#include "soc.h"
2ace831f	31
610eb8c2 S	32	static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
	33
	34	/**
	35	* omap_prm_base_init - Populates the prm partitions
	36	*
	37	* Populates the base addresses of the _prm_bases
	38	* array used for read/write of prm module registers.
	39	*/
	40	void omap_prm_base_init(void)
	41	{
	42	_prm_bases[OMAP4430_PRM_PARTITION] = prm_base;
	43	_prm_bases[OMAP4430_PRCM_MPU_PARTITION] = prcm_mpu_base;
	44	}
2ace831f PW	45
	46	/* Read a register in a PRM instance */
	47	u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
	48	{
	49	BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS \|\|
	50	part == OMAP4430_INVALID_PRCM_PARTITION \|\|
	51	!_prm_bases[part]);
edfaf05c	52	return readl_relaxed(_prm_bases[part] + inst + idx);
2ace831f PW	53	}
	54
	55	/* Write into a register in a PRM instance */
	56	void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
	57	{
	58	BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS \|\|
	59	part == OMAP4430_INVALID_PRCM_PARTITION \|\|
	60	!_prm_bases[part]);
edfaf05c	61	writel_relaxed(val, _prm_bases[part] + inst + idx);
2ace831f PW	62	}
	63
	64	/* Read-modify-write a register in PRM. Caller must lock */
	65	u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
eaac329d	66	u16 idx)
2ace831f PW	67	{
	68	u32 v;
	69
	70	v = omap4_prminst_read_inst_reg(part, inst, idx);
	71	v &= ~mask;
	72	v \|= bits;
	73	omap4_prminst_write_inst_reg(v, part, inst, idx);
	74
	75	return v;
	76	}
eaac329d BC	77
	78	/*
	79	* Address offset (in bytes) between the reset control and the reset
	80	* status registers: 4 bytes on OMAP4
	81	*/
	82	#define OMAP4_RST_CTRL_ST_OFFSET 4
	83
	84	/**
	85	* omap4_prminst_is_hardreset_asserted - read the HW reset line state of
	86	* submodules contained in the hwmod module
	87	* @rstctrl_reg: RM_RSTCTRL register address for this module
	88	* @shift: register bit shift corresponding to the reset line to check
	89	*
	90	* Returns 1 if the (sub)module hardreset line is currently asserted,
	91	* 0 if the (sub)module hardreset line is not currently asserted, or
	92	* -EINVAL upon parameter error.
	93	*/
	94	int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
	95	u16 rstctrl_offs)
	96	{
	97	u32 v;
	98
	99	v = omap4_prminst_read_inst_reg(part, inst, rstctrl_offs);
	100	v &= 1 << shift;
	101	v >>= shift;
	102
	103	return v;
	104	}
	105
	106	/**
	107	* omap4_prminst_assert_hardreset - assert the HW reset line of a submodule
	108	* @rstctrl_reg: RM_RSTCTRL register address for this module
	109	* @shift: register bit shift corresponding to the reset line to assert
	110	*
	111	* Some IPs like dsp, ipu or iva contain processors that require an HW
	112	* reset line to be asserted / deasserted in order to fully enable the
	113	* IP. These modules may have multiple hard-reset lines that reset
	114	* different 'submodules' inside the IP block. This function will
	115	* place the submodule into reset. Returns 0 upon success or -EINVAL
	116	* upon an argument error.
	117	*/
	118	int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
	119	u16 rstctrl_offs)
	120	{
	121	u32 mask = 1 << shift;
	122
	123	omap4_prminst_rmw_inst_reg_bits(mask, mask, part, inst, rstctrl_offs);
	124
	125	return 0;
	126	}
	127
	128	/**
	129	* omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
	130	* wait
	131	* @rstctrl_reg: RM_RSTCTRL register address for this module
	132	* @shift: register bit shift corresponding to the reset line to deassert
	133	*
	134	* Some IPs like dsp, ipu or iva contain processors that require an HW
	135	* reset line to be asserted / deasserted in order to fully enable the
	136	* IP. These modules may have multiple hard-reset lines that reset
	137	* different 'submodules' inside the IP block. This function will
	138	* take the submodule out of reset and wait until the PRCM indicates
	139	* that the reset has completed before returning. Returns 0 upon success or
	140	* -EINVAL upon an argument error, -EEXIST if the submodule was already out
141	* of reset, or -EBUSY if the submodule did not exit reset promptly.
142	*/
143	int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
144	u16 rstctrl_offs)
145	{
146	int c;
147	u32 mask = 1 << shift;
148	u16 rstst_offs = rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET;
149
150	/* Check the current status to avoid de-asserting the line twice */
151	if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
152	rstctrl_offs) == 0)
153	return -EEXIST;
154
155	/* Clear the reset status by writing 1 to the status bit */
156	omap4_prminst_rmw_inst_reg_bits(0xffffffff, mask, part, inst,
157	rstst_offs);
158	/* de-assert the reset control line */
159	omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
160	/* wait the status to be set */
161	omap_test_timeout(omap4_prminst_is_hardreset_asserted(shift, part, inst,
162	rstst_offs),
163	MAX_MODULE_HARDRESET_WAIT, c);
164
165	return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
166	}
e54433f1 BC	167
	168
	169	void omap4_prminst_global_warm_sw_reset(void)
	170	{
	171	u32 v;
1d597b07 RN	172	s16 dev_inst;
	173
	174	if (cpu_is_omap44xx())
	175	dev_inst = OMAP4430_PRM_DEVICE_INST;
	176	else if (soc_is_omap54xx())
	177	dev_inst = OMAP54XX_PRM_DEVICE_INST;
	178	else if (soc_is_dra7xx())
	179	dev_inst = DRA7XX_PRM_DEVICE_INST;
a7daf64a LV	180	else if (soc_is_am43xx())
a7daf64a LV	181	dev_inst = AM43XX_PRM_DEVICE_INST;
1d597b07 RN	182	else
	183	return;
	184
	185	v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, dev_inst,
	186	OMAP4_PRM_RSTCTRL_OFFSET);
e54433f1 BC	187	v \|= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
e54433f1 BC	188	omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
18ba7b9d	189	dev_inst,
e54433f1 BC	190	OMAP4_PRM_RSTCTRL_OFFSET);
	191
	192	/* OCP barrier */
	193	v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
18ba7b9d	194	dev_inst,
e54433f1 BC	195	OMAP4_PRM_RSTCTRL_OFFSET);
e54433f1 BC	196	}