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f2ab9977 PW |
1 | /* |
2 | * SMS/SDRC (SDRAM controller) common code for OMAP2/3 | |
3 | * | |
4 | * Copyright (C) 2005, 2008 Texas Instruments Inc. | |
5 | * Copyright (C) 2005, 2008 Nokia Corporation | |
6 | * | |
7 | * Tony Lindgren <tony@atomide.com> | |
8 | * Paul Walmsley | |
9 | * Richard Woodruff <r-woodruff2@ti.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
87246b75 | 15 | #undef DEBUG |
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16 | |
17 | #include <linux/module.h> | |
18 | #include <linux/kernel.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/list.h> | |
21 | #include <linux/errno.h> | |
22 | #include <linux/delay.h> | |
23 | #include <linux/clk.h> | |
24 | #include <linux/io.h> | |
25 | ||
622297fd | 26 | #include "../plat-omap/sram.h" |
f2ab9977 | 27 | |
a135eaae PW |
28 | #include "common.h" |
29 | #include "clock.h" | |
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30 | #include "sdrc.h" |
31 | ||
58cda884 | 32 | static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1; |
87246b75 | 33 | |
f2ab9977 PW |
34 | void __iomem *omap2_sdrc_base; |
35 | void __iomem *omap2_sms_base; | |
36 | ||
8a917d2f KJ |
37 | struct omap2_sms_regs { |
38 | u32 sms_sysconfig; | |
39 | }; | |
40 | ||
41 | static struct omap2_sms_regs sms_context; | |
42 | ||
98cfe5ab PW |
43 | /* SDRC_POWER register bits */ |
44 | #define SDRC_POWER_EXTCLKDIS_SHIFT 3 | |
45 | #define SDRC_POWER_PWDENA_SHIFT 2 | |
46 | #define SDRC_POWER_PAGEPOLICY_SHIFT 0 | |
87246b75 | 47 | |
8a917d2f KJ |
48 | /** |
49 | * omap2_sms_save_context - Save SMS registers | |
50 | * | |
51 | * Save SMS registers that need to be restored after off mode. | |
52 | */ | |
53 | void omap2_sms_save_context(void) | |
54 | { | |
55 | sms_context.sms_sysconfig = sms_read_reg(SMS_SYSCONFIG); | |
56 | } | |
57 | ||
58 | /** | |
59 | * omap2_sms_restore_context - Restore SMS registers | |
60 | * | |
61 | * Restore SMS registers that need to be Restored after off mode. | |
62 | */ | |
63 | void omap2_sms_restore_context(void) | |
64 | { | |
65 | sms_write_reg(sms_context.sms_sysconfig, SMS_SYSCONFIG); | |
66 | } | |
67 | ||
87246b75 PW |
68 | /** |
69 | * omap2_sdrc_get_params - return SDRC register values for a given clock rate | |
70 | * @r: SDRC clock rate (in Hz) | |
58cda884 JP |
71 | * @sdrc_cs0: chip select 0 ram timings ** |
72 | * @sdrc_cs1: chip select 1 ram timings ** | |
87246b75 PW |
73 | * |
74 | * Return pre-calculated values for the SDRC_ACTIM_CTRLA, | |
58cda884 JP |
75 | * SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01] |
76 | * structs,for a given SDRC clock rate 'r'. | |
77 | * These parameters control various timing delays in the SDRAM controller | |
78 | * that are expressed in terms of the number of SDRC clock cycles to | |
79 | * wait; hence the clock rate dependency. | |
80 | * | |
81 | * Supports 2 different timing parameters for both chip selects. | |
82 | * | |
83 | * Note 1: the sdrc_init_params_cs[01] must be sorted rate descending. | |
84 | * Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size | |
85 | * as sdrc_init_params_cs_0. | |
86 | * | |
87 | * Fills in the struct omap_sdrc_params * for each chip select. | |
88 | * Returns 0 upon success or -1 upon failure. | |
87246b75 | 89 | */ |
58cda884 JP |
90 | int omap2_sdrc_get_params(unsigned long r, |
91 | struct omap_sdrc_params **sdrc_cs0, | |
92 | struct omap_sdrc_params **sdrc_cs1) | |
87246b75 | 93 | { |
58cda884 | 94 | struct omap_sdrc_params *sp0, *sp1; |
87246b75 | 95 | |
58cda884 JP |
96 | if (!sdrc_init_params_cs0) |
97 | return -1; | |
8bd22949 | 98 | |
58cda884 JP |
99 | sp0 = sdrc_init_params_cs0; |
100 | sp1 = sdrc_init_params_cs1; | |
87246b75 | 101 | |
58cda884 JP |
102 | while (sp0->rate && sp0->rate != r) { |
103 | sp0++; | |
104 | if (sdrc_init_params_cs1) | |
105 | sp1++; | |
106 | } | |
87246b75 | 107 | |
58cda884 JP |
108 | if (!sp0->rate) |
109 | return -1; | |
87246b75 | 110 | |
58cda884 JP |
111 | *sdrc_cs0 = sp0; |
112 | *sdrc_cs1 = sp1; | |
113 | return 0; | |
87246b75 PW |
114 | } |
115 | ||
116 | ||
b6a4226c | 117 | void __init omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms) |
f2ab9977 | 118 | { |
b6a4226c PW |
119 | omap2_sdrc_base = sdrc; |
120 | omap2_sms_base = sms; | |
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121 | } |
122 | ||
98cfe5ab PW |
123 | /** |
124 | * omap2_sdrc_init - initialize SMS, SDRC devices on boot | |
58cda884 JP |
125 | * @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params |
126 | * Support for 2 chip selects timings | |
98cfe5ab PW |
127 | * |
128 | * Turn on smart idle modes for SDRAM scheduler and controller. | |
129 | * Program a known-good configuration for the SDRC to deal with buggy | |
130 | * bootloaders. | |
131 | */ | |
58cda884 JP |
132 | void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, |
133 | struct omap_sdrc_params *sdrc_cs1) | |
f2ab9977 PW |
134 | { |
135 | u32 l; | |
136 | ||
137 | l = sms_read_reg(SMS_SYSCONFIG); | |
138 | l &= ~(0x3 << 3); | |
139 | l |= (0x2 << 3); | |
140 | sms_write_reg(l, SMS_SYSCONFIG); | |
141 | ||
142 | l = sdrc_read_reg(SDRC_SYSCONFIG); | |
143 | l &= ~(0x3 << 3); | |
144 | l |= (0x2 << 3); | |
145 | sdrc_write_reg(l, SDRC_SYSCONFIG); | |
87246b75 | 146 | |
58cda884 JP |
147 | sdrc_init_params_cs0 = sdrc_cs0; |
148 | sdrc_init_params_cs1 = sdrc_cs1; | |
98cfe5ab PW |
149 | |
150 | /* XXX Enable SRFRONIDLEREQ here also? */ | |
75f251e3 PW |
151 | /* |
152 | * PWDENA should not be set due to 34xx erratum 1.150 - PWDENA | |
153 | * can cause random memory corruption | |
154 | */ | |
98cfe5ab | 155 | l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) | |
98cfe5ab PW |
156 | (1 << SDRC_POWER_PAGEPOLICY_SHIFT); |
157 | sdrc_write_reg(l, SDRC_POWER); | |
8a917d2f | 158 | omap2_sms_save_context(); |
f2ab9977 | 159 | } |